UPD78F9222MC(T)-5A4-A NEC, UPD78F9222MC(T)-5A4-A Datasheet - Page 33

• Manufacturer Part Number: UPD78F9222MC(T)-5A4-A
• Description: 8BIT MCU, 4K FLASH, 256B RAM, 78F9222
• Manufacturer: NEC

Specifications of UPD78F9222MC(T)-5A4-A

• Controller Family/series: UPD78
• No. Of I/o's: 17
• Ram Memory Size: 256Byte
• Cpu Speed: 10MHz
• No. Of Timers: 4
• No. Of: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 4KB
• Oscillator Type: External, Internal

3.2 Processor Registers
3.2.1 Control registers
control registers include a program counter, a program status word, and a stack pointer.
The 78K0S/KA1+ provides the following on-chip processor registers.
The control registers have special functions to control the program sequence statuses and stack memory. The
(1) Program counter (PC)
(2) Program status word (PSW)
PC
The program counter is a 16-bit register which holds the address information of the next program to be
executed.
In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to
be fetched. When a branch instruction is executed, immediate data or register contents are set.
Reset signal generation sets the reset vector table values at addresses 0000H and 0001H to the program
counter.
The program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution.
Program status word contents are stored in stack area upon interrupt request generation or PUSH PSW
instruction execution and are restored upon execution of the RETI and POP PSW instructions.
Reset signal generation sets PSW to 02H.
(a) Interrupt enable flag (IE)
(b) Zero flag (Z)
(c) Auxiliary carry flag (AC)
PC15
15
This flag controls interrupt request acknowledge operations of the CPU.
When IE = 0, the interrupt disabled (DI) status is set. All interrupt requests are disabled.
When IE = 1, the interrupt enabled (EI) status is set. Interrupt request acknowledgment is controlled with
an interrupt mask flag for various interrupt sources.
This flag is reset to 0 upon DI instruction execution or interrupt acknowledgment and is set to 1 upon EI
instruction execution.
When the operation result is zero, this flag is set to 1. It is reset to 0 in all other cases.
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set to 1. It is reset to 0 in all
other cases.
PC14
PC13 PC12 PC11 PC10 PC9
PSW
Figure 3-6. Program Status Word Configuration
IE
7
Figure 3-5. Program Counter Configuration
CHAPTER 3 CPU ARCHITECTURE
Z
User’s Manual U16898EJ5V0UD
0
PC8
AC
PC7
0
PC6
0
PC5
1
PC4
CY
PC3
0
PC2
PC1
PC0
0
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