UPD78F9222MC(T)-5A4-A NEC, UPD78F9222MC(T)-5A4-A Datasheet - Page 106

• Manufacturer Part Number: UPD78F9222MC(T)-5A4-A
• Description: 8BIT MCU, 4K FLASH, 256B RAM, 78F9222
• Manufacturer: NEC

Specifications of UPD78F9222MC(T)-5A4-A

• Controller Family/series: UPD78
• No. Of I/o's: 17
• Ram Memory Size: 256Byte
• Cpu Speed: 10MHz
• No. Of Timers: 4
• No. Of: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 4KB
• Oscillator Type: External, Internal

106
CR010 capture value
CR000 capture value
(4) Pulse width measurement by means of restart
TM00 count value
CRC00
TI000 pin input
Note The carry flag is set to 1. Ignore this setting.
Specify both the rising and falling edges as the valid edges of the TI000 pin, by using bits 4 and 5 (ES000 and
ES010) of PRM00.
When a valid edge of the TI000 pin is detected, the count value of 16-bit timer/counter 00 (TM00) is taken into
16-bit timer capture/compare register 010 (CR010), and then the pulse width of the signal input to the TI000
pin is measured by clearing TM00 and restarting the count.
Sampling is performed at the interval selected by prescaler mode register 00 (PRM00) and a capture operation
is only performed when a valid level of the TI000 pin is detected twice, thus eliminating noise with a short
pulse width.
Caution The measurable pulse width in this operation example is up to 1 cycle of the timer counter.
Count clock
INTTM010
Figure 6-25. Control Register Settings for Pulse Width Measurement by Means of Restart
Figure 6-24. Timing of Pulse Width Measurement Operation by Free-Running Counter
7
0
6
0
0000H
t
and Two Capture Registers (with Rising Edge Specified)
5
0
0001H
(a) Capture/compare control register 00 (CRC00)
4
0
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
3
0
(with Rising Edge Specified) (1/2)
D0
CRC002
(D1 − D0) × t
D0
User’s Manual U16898EJ5V0UD
D0 + 1
1
CRC001
1
CRC000
D1
1
D1
D1 + 1
CR000 used as capture register
Captures to CR000 at inverse edge to valid edge of TI000
CR010 used as capture register
(D2 − D1) × t
FFFFH
0000H
Note
D2
(D3 − D2) × t
D2 + 1
D2
D3
Note
.
D3