UPD78F9222MC(T)-5A4-A NEC, UPD78F9222MC(T)-5A4-A Datasheet - Page 302

• Manufacturer Part Number: UPD78F9222MC(T)-5A4-A
• Description: 8BIT MCU, 4K FLASH, 256B RAM, 78F9222
• Manufacturer: NEC

Specifications of UPD78F9222MC(T)-5A4-A

• Controller Family/series: UPD78
• No. Of I/o's: 17
• Ram Memory Size: 256Byte
• Cpu Speed: 10MHz
• No. Of Timers: 4
• No. Of: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 4KB
• Oscillator Type: External, Internal

18.8.9 Example of internal verify operation in self programming mode
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Examples of the internal verify 1 and 2 operations in self programming mode are explained below.
• Internal verify 1
<1> Set 01H (internal verify) to the flash program command register (FLCMD).
<2> Set the block number for which internal verify is performed, to flash address pointer H (FLAPH).
<3> Set 00H to the flash address pointer L (FLAPL).
<4> Write the same value as that of FLAPH to the flash address pointer H compare register (FLAPHC).
<5> Set FFH to the flash address pointer L compare register (FLAPLC).
<6> Clear the flash status register (PFS).
<7> Write ACH to the watchdog timer enable register (WDTE) (clear and restart the watchdog timer counter)
<8> Execute the HALT instruction then start self programming. (Execute an instruction immediately after the
<9> Check if a self programming error has occurred using bit 1 (VCERR) and bit 2 (WEPRERR) of PFS.
<10> Internal verify processing is terminated abnormally.
<11> Internal verify processing is terminated normally.
• Internal verify 2
<1> Set 02H (internal verify 2) to the flash program command register (FLCMD).
<2> Set the block number for which internal verify is performed, to flash address pointer H (FLAPH).
<3> Set the verify start address to the flash address pointer L (FLAPL).
<4> Write the same value as that of FLAPH to the flash address pointer H compare register (FLAPHC).
<5> Set the verify end address to the flash address pointer L compare register (FLAPLC).
<6> Clear the flash status register (PFS).
<7> Write ACH to the watchdog timer enable register (WDTE) (clear and restart the watchdog timer counter)
<8> Execute the HALT instruction then start self programming. (Execute an instruction immediately after the HALT
<9> Check if a self programming error has occurred using bit 1 (VCERR) and bit 2 (WEPRERR) of PFS.
<10> Internal verify processing is terminated abnormally.
<11> Internal verify processing is terminated normally.
Note This setting is not required when the watchdog timer is not used.
HALT instruction if self programming has been executed.)
Abnormal → <10>
Normal
instruction if self programming has been executed.)
Abnormal → <10>
Normal
→ <11>
→ <11>
CHAPTER 18 FLASH MEMORY
User’s Manual U16898EJ5V0UD
Note
Note
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