UPD78F9222MC(T)-5A4-A NEC, UPD78F9222MC(T)-5A4-A Datasheet - Page 181

• Manufacturer Part Number: UPD78F9222MC(T)-5A4-A
• Description: 8BIT MCU, 4K FLASH, 256B RAM, 78F9222
• Manufacturer: NEC

Specifications of UPD78F9222MC(T)-5A4-A

• Controller Family/series: UPD78
• No. Of I/o's: 17
• Ram Memory Size: 256Byte
• Cpu Speed: 10MHz
• No. Of Timers: 4
• No. Of: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 4KB
• Oscillator Type: External, Internal

(INTP0). The length of the synchronous field transmitted from the LIN master can be measured using the external
event capture operation of 16-bit timer/event counter 00, and the baud rate error can be calculated.
timer/event counter 00 by port input switch control (ISC0/ISC1), without connecting RxD6 and INTP0/TI000 externally.
Reception interrupt
The flow for reception processing is described below.
<1> The wakeup signal is detected at the edge of the pin, and enables UART6 and sets the SBF reception mode.
<2> Reception continues until the STOP bit is detected. When an SBF with low-level data of 11 bits or more has
<3> If SBF reception has been completed correctly, an interrupt request signal is output.
<4> Calculate the baud rate error from the bit interval of the synchronous field, disable UART6 after SF reception,
<5> Distinguish the checksum field by software. Also perform processing by software to initialize UART6 after
Figure 11-3 illustrates the port configuration for LIN reception operation.
The wakeup signal transmitted from the LIN master is received by detecting the edge of the external interrupt
The input signal of the reception port input (RxD6) can be input to the external interrupt (INTP0) and 16-bit
Edge detection
Capture timer
been detected, it is assumed that SBF reception has been completed correctly, and an interrupt request signal
is output. If an SBF with low-level data of less than 11 bits has been detected, it is assumed that an SBF
reception error has occurred. The interrupt request signal is not output and the SBF reception mode is
restored.
and then re-set baud rate generator control register 6 (BRGC6).
timer/event counter 00 during SBF reception completion interrupt processing, and measure the bit width
(pulse width) of the sync field (refer to 6.4.3 Pulse width measurement operations). Detection of errors
OVE6, PE6, and FE6 is suppressed, and error detection processing of UART communication and data
transfer of the shift register and RXB6 is not performed. The shift register holds the reset value FFH.
reception of the checksum field and to set the SBF reception mode again.
(INTSR6)
(INTP0)
LIN bus
(input)
RXD6
Disable
signal frame
<1>
Wakeup
Enable
CHAPTER 11 SERIAL INTERFACE UART6
Figure 11-2. LIN Reception Operation
Disable
SBF reception
Synchronous
break field
User’s Manual U16898EJ5V0UD
13 bits
<2>
<3>
Synchronous
reception
field
SF
Enable
<4>
reception
Identifier
field
ID
Data field
reception
Data
Data field Checksum
reception
Data
Start the 16-bit
reception
Data
field
<5>
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