UPD78F9222MC(T)-5A4-A NEC, UPD78F9222MC(T)-5A4-A Datasheet - Page 224

8BIT MCU, 4K FLASH, 256B RAM, 78F9222

UPD78F9222MC(T)-5A4-A

Manufacturer Part Number
UPD78F9222MC(T)-5A4-A
Description
8BIT MCU, 4K FLASH, 256B RAM, 78F9222
Manufacturer
NEC
Datasheet

Specifications of UPD78F9222MC(T)-5A4-A

Controller Family/series
UPD78
No. Of I/o's
17
Ram Memory Size
256Byte
Cpu Speed
10MHz
No. Of Timers
4
No. Of
RoHS Compliant
Core Size
8bit
Program Memory Size
4KB
Oscillator Type
External, Internal

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224
Address: FFEDH
Symbol
INTM1
Symbol
(4)
(5)
PSW
External interrupt mode register 1 (INTM1)
INTM1 is used to specify the valid edge for INTP3.
INTM1 is set with an 8-bit memory manipulation instruction.
Reset signal generation clears INTM1 to 00H.
Program status word (PSW)
The program status word is used to hold the instruction execution result and the current status of the interrupt
requests. The IE flag, used to enable and disable maskable interrupts, is mapped to PSW.
PSW can be read- and write-accessed in 8-bit units, as well as using bit manipulation instructions and
dedicated instructions (EI and DI). When a vectored interrupt is acknowledged, the PSW is automatically
saved to a stack, and the IE flag is reset to 0.
Reset signal generation sets PSW to 02H.
Cautions 1. Be sure to clear bits 2 to 7 to 0.
ES31
IE
IE
7
0
0
0
1
1
7
0
1
Disabled
Enabled
After reset: 00H
Z
6
ES30
2. Before setting INTM1, set PMK3 to 1 to disable interrupts.
6
0
0
1
0
1
Figure 12-5. Format of External Interrupt Mode Register 1 (INTM1)
To enable interrupts, clear PIF3 to 0, then clear PMK3 to 0.
5
0
Falling edge
Rising edge
Setting prohibited
Both rising and falling edges
Figure 12-6. Program Status Word (PSW) Configuration
5
0
AC
4
R/W
3
0
CHAPTER 12 INTERRUPT FUNCTIONS
4
0
Whether to enable/disable interrupt acknowledgment
2
0
User’s Manual U16898EJ5V0UD
3
0
1
1
CY
2
0
0
INTP3 valid edge selection
ES31
After reset
Used in the execution of ordinary instructions
1
02H
ES30
0

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