UPD78F9222MC(T)-5A4-A NEC, UPD78F9222MC(T)-5A4-A Datasheet - Page 333

• Manufacturer Part Number: UPD78F9222MC(T)-5A4-A
• Description: 8BIT MCU, 4K FLASH, 256B RAM, 78F9222
• Manufacturer: NEC

Specifications of UPD78F9222MC(T)-5A4-A

• Controller Family/series: UPD78
• No. Of I/o's: 17
• Ram Memory Size: 256Byte
• Cpu Speed: 10MHz
• No. Of Timers: 4
• No. Of: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 4KB
• Oscillator Type: External, Internal

CMP
ADDW
SUBW
CMPW
INC
DEC
INCW
DECW
ROR
ROL
RORC
ROLC
SET1
CLR1
SET1
CLR1
NOT1
Mnemonic
Remark
A, #byte
saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
AX, #word
AX, #word
AX, #word
r
saddr
r
saddr
rp
rp
A, 1
A, 1
A, 1
A, 1
saddr.bit
sfr.bit
A.bit
PSW.bit
[HL].bit
saddr.bit
sfr.bit
A.bit
PSW.bit
[HL].bit
CY
CY
CY
One instruction clock cycle is one CPU clock cycle (f
register (PCC).
Operand
CHAPTER 20 INSTRUCTION SET OVERVIEW
Bytes
2
3
2
2
3
1
2
3
3
3
2
2
2
2
1
1
1
1
1
1
3
3
2
3
2
3
3
2
3
2
1
1
1
User’s Manual U16898EJ5V0UD
Clocks
10
10
4
6
4
4
8
6
6
6
6
6
4
4
4
4
4
4
2
2
2
2
6
6
4
6
6
6
4
6
2
2
2
(saddr) − byte
A − r
A − (HL)
AX, CY ← AX + word
AX, CY ← AX − word
AX − word
r ← r + 1
(saddr) ← (saddr) + 1
r ← r − 1
(saddr) ← (saddr) − 1
rp ← rp + 1
rp ← rp − 1
(CY, A
(CY, A
(CY ← A
(CY ← A
(saddr.bit) ← 1
sfr.bit ← 1
A.bit ← 1
PSW.bit ← 1
(HL).bit ← 1
(saddr.bit) ← 0
sfr.bit ← 0
A.bit ← 0
PSW.bit ← 0
(HL).bit ← 0
CY ← 1
CY ← 0
CY ← CY
A − byte
A − (saddr)
A − (addr16)
A − (HL + byte)
7
0
← A
← A
0
7
, A
, A
0
7
7
0
, A
, A
← CY, A
← CY, A
CPU
m−1
m+1
) selected by the processor clock control
← A
← A
Operation
m−1
m+1
m
m
) × 1
) × 1
← A
← A
m
m
) × 1
) × 1
Z
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
Flag
AC CY
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
333
×
×
×
×
×
×
×
1
0
×
×
×
×
×
×
×
×
×
×