PC97338VJG National Semiconductor, PC97338VJG Datasheet
PC97338VJG
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PC97338VJG Summary of contents
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... Micro- processor Address Data and Control Plug and Play Support IRQ Input DMA IRQ Channels Signals ® TRI-STATE is a registered trademark of National Semiconductor Corporation. ® ® ® ® IBM , MicroChannel , PC-AT and PS/2 ® ® Microsoft and Windows are registered trademarks of Microsoft Corporation. ...
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A new, high performance, on-chip Floppy Disk Controller (FDC) provides: — Software compatibility with the PC8477, which contains a superset of the floppy disk controller functions in the DP8473, the NEC PD765A and the N82077 — A modifiable 13-bit address ...
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Clock X1(CLKIN) MR AEN A0-A15 D0- IOCHRDY ZWS IRQ3-7, 9-12 DACK0,1,2,3 DRQ0,1,2,3 External SIRQI1,2,3 Device PD0/INDEX PD1/TRK0 PD2/WP PD3/RDATA PD4/DSKCHG PD5/MSEN0 PD6/DRATE0 Parallel PD7/MSEN1 SLIN/STEP/ASTRB Port STB/WRITE AFD/DENSEL/DSTRB Connector INIT/DIR ACK/DR1 ERR/HDSEL SLCT/WGATE PE/WDATA BUSY/MTR1/WAIT PNF ...
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... Selection Logic CFG0 External Power Down Control Basic Configuration CS0,1 SIN1 SOUT1 RTS1 BOUT1/DTR1 CTS1 DSR1 DCD1 RI1 IRTX IRRX1,2 IRSL0-2/ID0-2 PC97338VLJ PC97338VJG Super I/O SIN2 SOUT2 RTS2 BOUT2/DTR2 CTS2 DSR2 DCD2 RI2 RDATA WDATA WGATE HDSEL DIR STEP TRK0 INDEX DSKCHG ...
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Pin Descriptions 1.1 CONNECTION DIAGRAMS ............................................................................................................. 18 1.2 SIGNAL/PIN DESCRIPTIONS .......................................................................................................... 22 2.0 Configuration 2.1 OVERVIEW ...................................................................................................................................... 36 2.2 CONFIGURATION REGISTER SETUP ........................................................................................... 36 2.2.1 Hardware Device Configuration .............................................................................................. 36 2.2.2 Software Device Configuration ................................................................................................ 38 2.2.3 Updating Configuration ...
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SIO Base Address Low Byte Register (SBAL), Index 4Ah .................................................... 63 2.3.32 SIO Base Address High Byte Register (SBAH), Index 4Bh .................................................. 63 2.3.33 System IRQ Input 1 Configuration Register (SIRQ1), Index 4Ch .......................................... 63 2.3.34 System IRQ Input ...
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The CONFIGURE Command .................................................................................................. 94 3.6.3 The DUMPREG Command ..................................................................................................... 95 3.6.4 The FORMAT TRACK Command ........................................................................................... 96 3.6.5 The INVALID Command ......................................................................................................... 99 3.6.6 The LOCK Command ............................................................................................................ 100 3.6.7 The MODE Command ........................................................................................................... 100 3.6.8 The NSC ...
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EPP Data Port 3, Offset 7 ................................................................................................... 131 4.3.11 EPP Mode Transfer Operations .......................................................................................... 131 4.4 EXTENDED CAPABILITIES PARALLEL PORT (ECP) MODES .................................................... 133 4.4.1 Accessing the ECP Registers ............................................................................................... 134 4.4.2 Software Operation in ECP Modes ....................................................................................... 134 ...
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ARCHITECTURAL DESCRIPTION .............................................................................................. 153 5.14 BANK 0 ......................................................................................................................................... 153 5.14.1 TXD/RXD – Transmit/Receive Data Ports ........................................................................... 153 5.14.2 IER – Interrupt Enable Register .......................................................................................... 154 5.14.3 EIR/FCR – Event Identification/FIFO Control Registers ...................................................... 154 5.14.4 LCR/BSR – Link Control/Bank ...
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IRTXMC – Infrared Transmitter Modulator Control Register ............................................... 178 5.21.3 RCCFG – CEIR Configuration Register .............................................................................. 179 5.21.4 LCR/BSR – Link Control/Bank Select Registers ................................................................. 179 5.21.5 IRCFG [1–4] – Infrared Interface Configuration Registers .................................................. 179 5.22 SERIAL COMMUNICATION ...
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AC ELECTRICAL CHARACTERISTICS ......................................................................................... 202 8.3.1 AC Test Conditions T A 8.4 SWITCHING CHARACTERISTICS ................................................................................................ 203 8.4.1 Timing Table ......................................................................................................................... 203 8.4.2 Timing Diagrams .................................................................................................................. 207 9.0 Appendix A COMPARISON OF PC87338 AND PC97338 ....................................................................................... 216 = 0 C ...
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FIGURE 1 Plug and Play Protocol Flowchart .................................................................................................. 39 FIGURE 2 LFSR Circuit ................................................................................................................................... 40 FIGURE 3 FER Register Bitmap ..................................................................................................................... 45 FIGURE 4 FAR Register Bitmap ..................................................................................................................... 47 FIGURE 5 PTR Register Bitmap ..................................................................................................................... 48 FIGURE 6 FCR Register ...
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FIGURE 50 DSR Register Bitmap ................................................................................................................... 82 FIGURE 51 FDC Data Register Bitmap ........................................................................................................... 83 FIGURE 52 DIR Register Bitmap .................................................................................................................... 84 FIGURE 53 CCR Register Bitmap ................................................................................................................... 84 FIGURE 54 ST0 Result Phase Register Bitmap .............................................................................................. 88 FIGURE 55 ...
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FIGURE 88 Extended Control Register 1 ...................................................................................................... 166 FIGURE 88 DMA Control Signals Routing .................................................................................................... 167 FIGURE 88 Extended Control Register 2 ...................................................................................................... 167 FIGURE 88 Transmit FIFO Level ................................................................................................................. 168 FIGURE 88 Receive FIFO Level .................................................................................................................. 168 FIGURE 88 ...
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TABLE 1 Signal/Pin Description Table ............................................................................................................ 22 TABLE 2 Multi-Function Pins (Excluding Strap Pins) ...................................................................................... 34 TABLE 3 IRQ12, A15-11 / SCC2 / Infrared Pin Allocation ............................................................................... 35 TABLE 4 SCC2 Mode Configurations 1 ........................................................................................................... 35 TABLE 5 SCC2 Mode ...
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TABLE 50 Effect of GDC Bits on FORMAT TRACK and WRITE DATA Commands .................................... 104 TABLE 51 Skip Control Effect on READ DATA Command ........................................................................... 107 TABLE 52 Result Phase Termination Values with No Error .......................................................................... 108 TABLE 53 SK ...
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TABLE 101 Interrupt Support in Legacy Mode for IRQ 5, 12 and 15 ........................................................... 191 TABLE 102 TRI-STATE Condition for Interrupts in Legacy Mode ................................................................. 19 2 TABLE 103 Interrupt Support in Plug and Play Mode for IRQ3 ...
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Pin Descriptions 1.1 CONNECTION DIAGRAMS SLIN/STEP/ASTRB 81 SLCT/WGATE 82 ...
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AFD/DSTRB/DENSEL ERR/HDSEL 77 78 INIT/DIR SLIN/STEP/ASTRB 79 SLCT/WGATE 80 PE/WDATA 81 BUSY/WAIT/MTR1 82 ACK/DR1 ...
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SLIN/STEP/ASTRB 81 SLCT/WGATE 82 PE/WDATA 83 BUSY/WAIT/MTR1 84 ACK/DR1 85 ...
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... IRQ5/ADRATE0 96 VDD 97 IRQ4 98 IRQ3 99 MR 100 Thin Quad Flatpack (TQFP), JEDEC PC97338VJG Order Number PC97338VJG See NS Package Number VJG100A 21 50 DRATE0/MSEN0 49 DRA TE1/MSEN1/CS0/SIRQI2/DACK3 48 VDD 47 DRV2/PNF/DR23/SIRQI3/IRSL2/ID2 46 DENSEL/ADRATE1 45 INDEX 44 MTR0 43 DR1/PD ...
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SIGNAL/PIN DESCRIPTIONS Table 1 lists the signals of the Chip in alphabetical order. It also shows the pin associated with each signal for the Plastic Quad Flatpack, (PQFP) and Thin Quad Flatpack (TQFP) options. The I/O column describes whether ...
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I/O and PQFP TQFP Symbol Pin Pin Group # ASTRB 81 79 Group 11 BADDR0 74 72 BADDR1 73 71 Group 1 BOUT1 73 (71) 71 (69) BOUT2 65 (63) 63 (61) Group 7 BUSY 84 82 Group 2 CFG0 ...
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I/O and PQFP TQFP Symbol Pin Pin Group # CTS1 72 70 CTS2 64 62 Group I Group ...
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I/O and PQFP TQFP Symbol Pin Pin Group # DCD1 77 75 DCD2 69 67 Group 1 DENSEL 48 46 (Normal Group 10 Mode) (PPM 78 76 Mode) Group 10 DIR 41 39 (Normal Group 10 Mode) (PPM 80 78 ...
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I/O and PQFP TQFP Symbol Pin Pin Group # DRATE0 52 50 DRATE1 51 49 Group 8 (Normal Mode) DRATE0 87 85 (PPM Group 8 Mode) DRQ0 56 54 DRQ1 33 31 Group 6 DRQ2 4 2 DRQ3 60 58 ...
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I/O and PQFP TQFP Symbol Pin Pin Group # DTR1 71 69 DTR2 63 61 Group 7 ERR 79 77 Group 3 HDSEL 34 32 (Normal Group 10 Mode) (PPM 79 77 Mode) Group 10 ID2 ...
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I/O and PQFP TQFP Symbol Pin Pin Group # IRQ3 1 99 I/O IRQ4 100 98 Group 6 IRQ5 98 96 IRQ6 97 95 IRQ7 96 94 IRQ9 57 55 IRQ10 58 56 IRQ11 59 57 IRQ12 68 66 IRQ15 ...
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I/O and PQFP TQFP Symbol Pin Pin Group # IRRX1 67 65 IRRX2 68 66 Group 1 IRSL0 68 66 IRSL1 8 6 Group 12 IRSL2 IRTX 65 63 Group 100 ...
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I/O and PQFP TQFP Symbol Pin Pin Group # Group 10 PD0 94 92 I/O PD1 93 91 Group 1 PD2 92 90 and PD3 91 89 Group 11 PD4 89 87 PD5 88 86 PD6 87 ...
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I/O and PQFP TQFP Symbol Pin Pin Group # RTS1 74 72 RTS2 66 64 Group 7 SIN1 75 73 SIN2 67 65 Group 1 SIRQI1 60 58 SIRQI2 51 49 Group 1 SIRQI3 49 47 SLCT 82 80 Group ...
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I/O and PQFP TQFP Symbol Pin Pin Group # (PPM 81 79 Mode) Group Group 1 TRK0 37 35 (Normal Group 4 Mode) (PPM 93 91 Mode) Group 4 VDD 50 48 VSS 42 ...
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I/O and PQFP TQFP Symbol Pin Pin Group # Group 1 WRITE 95 93 Group Group 5 ZWS 3 1 Group 13 I Write. This active low input signal indicates a write from ...
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TABLE 2. Multi-Function Pins (Excluding Strap Pins) PQFP Pin TQFP Pin 3 1 CS1/ZWS 8 6 IRSL1/ID1 (in PC97338) MTR1/IDLE/IRSL2 (and ID2 in PC97338 DR1/ DENSEL/ADRATE1 49 47 DRV2/PNF/DR23/SIRQI3/IRSL2 (and ID2 in PC97338) 51 ...
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TABLE 3. PQFP Pin TQFP Pin DTR2 or BOUT2 is selected on the pin via the SCC2 registers in PC97338 only. See Section 5. TABLE 4. Pin Reset Value ...
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Configuration 2.1 OVERVIEW The configuration register set consists of 37 registers, which control the Chip set-up. Setup values stored in these registers enable or disable major functions, such as FDC, SCCs and the parallel port, and set functional parameters ...
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Symbol Description ASC Advanced SuperI/O Chip Configuration CLK Clock Control CS0CF Chip Select 0 Configuration CS0HA Chip Select 0 Base Address, High CS0LA Chip Select 0 Base Address, Low CS1CF Chip Select 1 Configuration CS1HA Chip Select 1 Base Address, ...
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Software Device Configuration Besides the three hardware-configured registers, all Legacy-mode access to the configuration registers is achieved by the use of an INDEX and DATA register pair. Each configuration register is indicated by the value loaded into the INDEX ...
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Plug and Play Protocol The following protocol is based on the Plug and Play ISA Specification 1.0a. It should be applied on power- up, if during reset BADDR1 = 0 and BADDR0 = not applicable otherwise. ...
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The Linear Feedback Shift Register (LFSR) The LFSR is an 8-bit shift register that resets to the value of 0x6A. (See Figure 2.) The feedback taps for this shift register are taken from register bits 1 and 0 of LFSR. ...
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Configuration Register Bitmaps Reset Required Parallel Port Enable SCC1 Enable SCC2 Enable FDC Enable FDC Four-Drive Encoding Select FDC Secondary Address Reserved Reserved ...
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Advanced SuperI/O Chip Configuration Register Reset Required Select IRQ5 or ADRATE0 Reserved Enhanced TDR Support PNF Status Select DENSEL or ADRATE1 ECP CNFGA Bit ...
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Register 1 (SCF1 Reset Required Reserved ECP DMA Number Parallel Port DMA Plug and Play Support Reserved Reserved Plug and Play Configuration 7 6 ...
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SCC1 Base Address High Byte Register Reset Required Address Length CFG0 = 1 11 Bits Reserved Reserved A10 Reserved Reserved Reserved Reserved Reserved SCC2 Base Address Low Byte Register ...
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System IRQ Input 2 Configuration Register Reset Required SIRQI2 Mapping Invert SIRQI2 SIRQI2 Status Select MSEN1, DRATE1, CS0 or SIRQI2 System IRQ Input 3 Configuration Register ...
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In Legacy mode, SCC1 can be accessed at the address specified by bits 3,2 of the FAR. In Plug and Play mode, the address is speci- fied the by S1BAL and S1BAH registers. Bit 2 - SCC2 Enable ...
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Address 3F2h is used if the FDC is located at the primary address (bit 5 of FER = 0) and address 372h is used if the FDC is located at the secondary address (bit 5 of FER ...
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Reset Required Power Down Reserved Reserved Select IRQ5 or IRQ7 SCC1 Test Mode Reserved Lock Configuration Select Extended or Compatible Parallel Port FIGURE 5. ...
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Bit 1 - Select MSEN0 or DRATE0 This bit is initialized to 0 during reset, thus select- ing MSEN0 MSEN0 is selected on the pin. (Default DRATE0 is selected on the pin. Bit 2 - Reserved ...
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Bit 3 - ECP Clock Freeze Control When either this bit or the ECP enable bit is 0, there is no change in the Chip clock stopping mechanism The ECP does not affect the stopping of the clock ...
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Bit and IDLE or IRSL2/ ID2 Enable This is the PD and IDLE (FDC power management output signals) or IRSL2/ ID2 enable bit. When bit 2 of the SCF3 register is 1, IRSL2 controls pin 43 (PQFP) ...
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Bit 3 - MIDI/ Reserved In the PC87338 version this is the MIDI baud rate configuration bit which function as follow The SCC1 baud rate generator is fed by the master clock of the Chip, divided by 13. ...
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Pin 98 (PQFP) or pin 96 (TQFP) is ADRATE0 open drain output. ADRATE0 has the same value as DRATE0. Bit 1 - Reserved This bit is reserved. Bit 2 - Enhanced TDR Support 0 - TDR read is ...
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During reset, if CFG0 = 0, decode four ad- dress bits (A15-A12) and compare them to bits 7-4 of CS0HA. Bits 3-0 of CS0HA and bits 7-0 of CS0LA are ignored. During reset, if CFG0 = 1, it ...
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Chip Select 0 High Address Register (CS0HA), Index 10h This register holds the high address bits of the moni- tored I/O address. See CS0LA and CS0CF for com- plementary description. Bit 0 holds A8. If during reset CFG0 is1, ...
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SuperI/O Chip Configuration Register 1 (SCF1), Index 18h Upon reset, SCF1 is initialized to xx00000x Reset Required Reserved ECP DMA Number Parallel Port ...
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Plug and Play Configuration 0 Register (PNP0), Index 1Bh This register allows configurable mapping of the par- allel port’s interrupt onto the ISA interrupts. Upon re- set, PNP0 is initialized to 00000xxx. Plug and Play Configuration ...
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In Legacy mode, these bits are ignored and paral- lel port interrupt mapping is controlled by bits ...
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Bit 4 - SCC1 Bank Select Enable Enables bank switching. Upon reset, this bit is ini- tialized All attempts to access the extended registers of SCC1 are ignored. (Default SCC1 extended registers accessible. Bits ...
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Bit 3 Bit 2 Bit 1 Bit ...
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Parallel Port Base Address High Byte Register Reset Required Address Length CFG0 = 1 11 Bits Reserved Reserved A10 Reserved Reserved Reserved Reserved Reserved ...
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SCC2 Base Address High Byte Register (S2BAH), Index 47h This register holds the high address bits of SCC2’s base address. In Legacy mode, this register is ignored and the base address of SCC2 is determined by bits 4-7 of ...
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SIO Base Address Low Byte Register (SBAL), Index 4Ah This register holds the low address bits of the base address of the SuperI/O chip, i.e., the Chip. These bits are also the low address bits of the INDEX regis- ...
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Bits 3-0 - SIRQI1 Mapping When it controls its pin, SIRQI1 can be routed onto one of the following ISA interrupts: IRQ7-3, IRQ12-9. See Table 27. Unpredictable results when invalid values are writ- ten. IRQ5 and IRQ12 can not always ...
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TABLE 29. SIRQI2 Plug and Play Interrupt Map- ping Bit 3 Bit 2 Bit 1 Bit ...
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TABLE 31. SIRQI3 Plug and Play Interrupt Map- ping Bit 3 Bit 2 Bit 1 Bit ...
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Bits 2-0 - SCC2 Receiver Channel Selection Upon reset these bits are initialized to 000 the software’s responsibility to route all DMA sources onto the ISA DMA channels correctly. Table 33 shows the encoding options for these bits. ...
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Bit 0 - Select DRATE1, MSEN1, CS0, SIRQI2 or DACK3 When the pin is assigned for DACK3, MSEN1 is masked DRATE1, MSEN1, CS0 or SIRQI2 may use the pin, according to bits 7 and 6 of ...
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The Digital Floppy Disk Controller (FDC) The Floppy Disk Controller (FDC) is suitable for all PC-AT, EISA, PS/2, and general purpose applica- tions. DP8473 and N82077 software compatibility is provided. Key features include a 16-byte FIFO, PS/2 diagnostic register ...
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... Figure 42 shows the dynamic window margin in the performance of the FDC at different data rates, gen- erated using a FlexStar FS-540 floppy disk simulator and a proprietary dynamic window margin test pro- gram written by National Semiconductor. 250,300, 500 Kbps and 1 Mbps ...
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The dynamic window margin performance curve also indicates how much bit jitter (or window margin) can be tolerated by the data separator. This parameter is shown on the y-axis of the graph. Bit jitter is caused by the magnetic interaction ...
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Read/ 200 mm Write (38 bytes @ 1 Mbps) Head End of Intersector = 41 x 4Eh Gap 2 ID Field FIGURE 44. Perpendicular Recording Drive Read/Write Head and Pre-Erase Head Unlike conventional disk drives which have only a read/write ...
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FDC Low-Power Mode Logic The FDC of the Chip supports two low-power modes, manual and automatic. Other low-power modes (also referred to as power down) of the Chip are described in Section 7.1. In low-power mode, the microcode is ...
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THE REGISTERS OF THE FDC Legacy Mode In Legacy mode, the FDC registers are mapped to the offset address shown in Table 35, with the base ad- dress range provided by the on-chip address decod- er. For PC-AT or ...
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Reset Required Drive 0 Busy Drive 1 Busy Drive 2 Busy Drive 3 Busy Command in Progress Non-DMA Execution Data I/O Direction RQM 7 ...
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WP is active, i.e., the FDD in the selected drive is write protected not active, i.e., the FDD in the selected drive is not write protected. Bit 2 - Beginning of Track (INDEX) This ...
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WGATE is not active. The write circuitry of the selected FDD is disabled WGATE is active. The write circuitry of the se- lected FDD is enabled. (Default) Bit 3 - Read Data Status (RDATA) If read ...
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The motor enable and drive select signals for drives 2 and 3 are only available when four drives are support- ed, i.e., when bit 4 of FER when drives 2 and 0 are exchanged. These signals require ...
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Tape Drive Register (TDR), Offset 011 The TDR register is a read/write register that acts as the Floppy Disk Controller’s (FDC) media and drive type register. The bits of the TDR register function differently, de- pending on the drive ...
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Bits 3,2 - Logical Drive Control 1,0 (Enhanced Mode Only) These read/write bits control logical drive ex- change between drives 0 and 2. Drive 3 is never exchanged for drive 2. When four drives are configured, i.e., bit 4 of ...
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Reset Required Drive 0 Busy Drive 1 Busy Drive 2 Busy Drive 3 Busy Command in Progress Non-DMA Execution Data I/O Direction RQM FIGURE ...
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Data Rate Select Register (DSR), Offset 100 This write-only register is used to program the data transfer rate, amount of write precompensation, pow- er down mode, and software reset. The data transfer rate is programmed via the CCR, not ...
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Normal power Trigger power down. Bit 7 - Software Reset This bit controls the same kind of software reset of the FDC as bit 2 of the Digital Output Register (DOR). The difference is that this ...
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Section 3.1.2 on page 70 describes each mode and “Bit 7 - System Operation Mode” on page 53 de- scribes how each is enabled. In PC-AT mode, bits 6 through 0 are in TRI-STATE to prevent conflict with the status ...
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THE PHASES OF FDC COMMANDS FDC commands may be in the command phase, the execution phase or the result phase. The active phase determines how data is transferred between the Floppy Disk Controller (FDC) and the host micro- processor. ...
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PC-AT Mode In PC-AT interface mode when the FIFO is disabled, the controller is in single byte transfer mode. That is, the system has the time it takes to transfer one byte, to service a DMA request (DRQ) from the ...
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During a write operation, an underrun error terminates the execution phase after the controller has written the remaining bytes of the sector with the last correct- ly written byte to the FIFO. Whether there is an error or not, an ...
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... While in the idle phase, the controller periodically enters the drive polling phase. 3.4.5 Drive Polling Phase National Semiconductor’s FDC supports the polling mode of old 8-inch drives means of monitoring any change in status for each disk drive present in the system. This support provides backward compatibility with software that expects it ...
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Bit 4 - Equipment Check After a RECALIBRATE command, this bit indi- cates whether the head of the selected drive was at track 0, i.e., whether or not TRK0 was active. This information is used during the SENSE IN- TERRUPT ...
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Bit 5 of the result phase Status register 2 (ST2) indicates when and where the error oc- curred. See Section 3.5.3. Bit 6 - Not Used This bit is not used and is always 0. Bit 7 - End of ...
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Control mark detected. Bit 7 - Not Used This bit is not used and is always 0. 3.5.4 Result Phase Status Register 3 (ST3 Result Phase Status ...
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TABLE 43. FDC Command Set Summary Opcode Command 7 6 CONFIGURE 0 0 DUMPREG 0 0 FORMAT TRACK 0 MFM INVALID Invalid Opcode LOCK 0 MODE 0 0 NSC 0 0 PERPENDICULAR 0 0 MODE READ DATA MT MFM SK ...
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GDC Group Drive Configuration for all drives. Con- figures all logical drives as conventional or perpendicular. Used in the PERPENDICULAR MODE command. Formerly, GAP2 and WG. HD Head Select control bit used in most com- mands. Selects Head 0 or ...
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The CONFIGURE Command The CONFIGURE command controls some operation modes of the controller. It should be issued during the initialization of the FDC after power up. The bits in the CONFIGURE registers are set to their default values after ...
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The DUMPREG Command The DUMPREG command supports system run-time diagnostics, and application software development and debugging. DUMPREG has a one-byte command phase (the op- code) and a 10-byte result phase, which returns the values of parameters set in other ...
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The FORMAT TRACK Command This command formats one track on the disk in IBM, ISO, or Toshiba perpendicular format. After a pulse from the INDEX signal is detected, data patterns are written on the disk including all gaps, Ad- ...
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Table 44 shows the number of bytes in a data field for each code. TABLE 44. Bytes per Sector Codes Bytes-Per-Sector Code Bytes in Data Field (hex Fourth Command Phase Byte - ...
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Drive Type and Data Bytes in Data Bytes-Per-Sector Transfer Field (decimal) Code (hex) Rate 128 128 256 125 Kbps 512 FM 1024 2048 256 256 512 250 Kbps MFM 512 1024 2048 4096 128 256 512 250 Kbps FM 1024 ...
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INDEX Pulse Gap 0 SYNC IAM Gap 1 IBM Format (MFM) C2* FC IBM GAP0 SYNC IAM GAP1 Format FF 00 FC* (FM) Toshiba ...
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The INVALID Command If an invalid command (illegal opcode byte in the com- mand phase) is received by the Floppy Disk Control- ler (FDC), the controller responds with the result phase Status register 0 (ST0) in the result phase. ...
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The MODE Command This command selects the special features of the con- troller. The bits in the command bytes of the MODE command are set to their default values after a hard- ware reset. Command Phase ...
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If ETR (bit the controller issues a maxi- mum of 3925 recalibration step pulses. (De- fault ETR (bit the controller issues a maxi- mum of 255 recalibration step pulses. If ETR ...
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Bits 7,6 - Density Select Pin Configuration (DENSEL) This field can configure the polarity of the Density Select output signal (DENSEL) as always low or always high, as shown in Table 4-3. This allows the user more flexibility with new ...
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The PERPENDICULAR MODE Command The PERPENDICULAR MODE command configures each of the four logical disk drives for perpendicular or conventional mode via the logical drive configuration bits 1,0 or 5-2, depending on the value of bit 7. The default ...
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Second Command Phase Byte A hardware reset clears all the bits to zero (conven- tional mode for all drives). PERPENDICULAR MODE command bits may be written at any time. The settings of bits 1 and 0 in this byte override ...
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Bit 6 - Modified Frequency Modulation (MFM) This bit indicates the type of the disk drive and the data transfer rate, and determines the format of the address marks and the encoding scheme mode, i.e., single density. ...
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If the track address differs, either the Wrong Track bit (bit 4) or the Bad Track bit (bit 1) (if the track ad- dress is FF hex) is set in result phase Status reg- ister 2 (ST2). See Section 3.5.3 ...
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TABLE 52. End of Track Multi-Track Head # (EOT) Sector (MT) (HD) Number < EOT EOT < EOT EOT < EOT a 1 ...
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Result Phase Result Phase Status Register 0 (ST0) Result Phase Status Register 1 (ST1) Result Phase Status Register 2 (ST2) Track Number Head Number Sector Number Bytes-Per-Sector Code See Table 52 for the state of ...
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Command Phase MFM IPS Track Number Head Number Sector Number Bytes-Per-Sector Code End of Track (EOT) Sector Number Bytes Between Sectors - Gap 3 Data Length (Obsolete) ...
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The controller waits the Delay Before Processing time (see Table 59 on page 117) for the selected drive., and then becomes idle. See “Idle Phase” on page 88. Then, the controller issues pulses until the TRK0 disk interface input signal ...
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The SCAN EQUAL, the SCAN LOW OR EQUAL and the SCAN HIGH OR EQUAL Commands The scan commands compare data read from the disk with data sent from the microprocessor. This compar- ison produces a match for each scan ...
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Result Phase Result Phase Status Register 0 (ST0) Result Phase Status Register 1 (ST1) Result Phase Status Register 2 (ST2) Track Number Head Number Sector Number Bytes-Per-Sector Code Table 55 shows how all the scan ...
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Fourth Command Phase Byte, Bits 7-4 - MSN of Track Number If the track number is stored as a 12-bit value, these bits contain the Most Significant Nibble (MSN), i.e., the four most significant bits, of the number of the ...
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The result phase of any of the following com- mands started: — READ DATA, READ DELETED DATA, READ A TRACK, READ ID — WRITE DATA, WRITE DELETED — FORMAT TRACK — SCAN EQUAL, SCAN EQUAL OR LOW, SCAN EQUAL ...
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Drive 0 is selected Drive 1 is selected four drives are supported, or drives 2 and 0 are exchanged, drive 2 is selected four drives are supported, drive 3 is ...
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TABLE 58. Constant Multipliers for Delay After Processing Factor and Delay Ranges Bit 7 of MODE (TMR Data Transfer Rate (bps) Constant Multiplier Permitted Range (msec) Constant Multiplier Permitted Range (msec 500 K 16 300 ...
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The VERIFY Command The VERIFY command verifies the contents of data and/or address fields after they have been formatted or written. VERIFY reads logical sectors containing a normal data Address Mark (AM) from the selected drive, with- out transferring ...
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TABLE 61. VERIFY Command Termination Con- ditions Sector Count (SC End of Track (EOT) Value should be FF (hex) a EOT Sectors per Side SC should be FF (hex) EOT > Sectors per Side ...
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The WRITE DATA Command The WRITE DATA command receives data from the host and writes logical sectors containing a normal data Address Mark (AM) to the selected drive. This command is like the READ DATA command, ex- cept that ...
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Result Phase Upon terminating the execution phase of the WRITE DATA command, the controller asserts IRQ6, indicat- ing the beginning of the result phase. The micropro- cessor must then read the result bytes from the FIFO ...
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G1 DR0 A1 DR1 B1 PC87338/ PC97338 MTR0 FIGURE 59. PC87338/PC97338 Four Floppy Disk Drive Circuit 7407 (2) 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3 Hex Buffers Open Collector 122 ...
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Parallel Port 4.1 INTRODUCTION The Parallel Port is a communications device that en- ables transfer of parallel data bytes between the sys- tem and an external device. Originally designed to output data to an external printer, the use of ...
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TABLE 62. Parallel Port Reset States Signal Reset Control State After Reset SLIN MR INIT MR AFD MR STB MR IRQ5,7 MR 4.2.1 Standard Parallel Port (SPP) Modes Register Set All SPP mode port operation is controlled by three registers. ...
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The actual read or write to the data register is activat the system RD and WR strobes. Table 64 tabulates DTR register operation. TABLE 64. SPP Data Register Read and Write Modes Bit 7 of Bit 5 of ...
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Bit 2 - IRQ Status In all modes except Extended SPP, this bit is always 1. In Extended SPP mode (bit 7 of PTR is 1) this bit is the IRQ status bit. It remains high unless the interrupt request ...
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Bit 1 - Automatic Line Feed Control This bit directly controls the automatic line feed signal to the printer via the AFD pin. Setting this bit high causes the printer to automatically feed after each line is printed. This bit ...
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Enhanced Parallel Port (EPP) Modes Register Set Table 66 lists the EPP mode registers. All are single- byte registers. Bits 0, 1 and 3 of the CTR register must be 0 before the EPP registers can be accessed, since ...
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Reset Required EPP Device D3 Read or Write D4 Bits 7 ...
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SPP or EPP Control Reset Required Data Strobe Control Automatic Line Feed Control Printer Initialization Control (INIT) Parallel Port Input Control Interrupt Enable Direction ...
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EPP Data Port 3, Offset 7 This is the fourth EPP data port only accessed to transfer bits 32-bit read or write to data port ...
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D7-0 RD WAIT ASTRB WRITE PD7-0 IOCHRDY ZWS FIGURE 73. EPP 1.7 Address Read EPP 1.7 Data Write and Read This procedure writes to the selected peripheral de- vice or register. An EPP 1.7 data read or write operations are ...
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D7-0 WR WAIT ASTRB WRITE PD7-0 IOCHRDY ZWS FIGURE 75. EPP 1.9 Address Write EPP 1.9 Address Read The following procedure reads from the address reg- ister. 1. The system reads a byte from the EPP address register. When RD ...
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TABLE 68. Parallel Port Registers in ECP Modes Offset Symbol Description 000h DATAR Parallel Port Data Register 000h AFIFO ECP Address FIFO 001h DSR Status Register All Modes 002h DCR Control Register All Modes R/W 400h CFIFO Parallel Port Data ...
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Hardware Operation in ECP Modes The ZWS signal is asserted by the ECP when ECP modes are enabled, and an ECP register is accessed by system PIO instructions, thus using a system zero wait states cycle (except during read ...
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Bits 7-5 of ECR = 010 Parallel Port FIFO Register (CFIFO Reset Required Data Bits Bits 7-5 of ECR = 011 ...
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ECP Address FIFO (AFIFO) Register, Bits 7-5 of ECR = 011, Offset 000h The ECP Address FIFO Register (AFIFO) is write only. In the forward direction (bit 5 of DCR byte written into this register is ...
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Bit 0 - Data Strobe Control Bit 0 directly controls the data strobe signal to the printer via the STB signal. This bit is the inverse of the STB signal The STB signal is inactive in all modes ...
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In the backward direction (bit 5 of DCR is 1), the ECP automatically issues ECP read cycles to fill the FIFO. Reading from this register pops a byte from the FIFO. Writing to this register when it is set for ...
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Bits 7-5 of ECR = 111 Configuration Register Reset Required DMA Channel Select Reserved Interrupt Select IRQ Signal Value Reserved FIGURE 85. CNFGB ...
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The FIFO is empty or ECP clock is frozen. Bit 1 - FIFO Full This bit continuously reflects the FIFO state, and therefore can only be read. Data written to this bit is ignored. When the ECP clock ...
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ECP MODE DESCRIPTIONS 4.5.1 Software Controlled Data Transfer (Modes 000 and 001) Software controlled data transfer is supported in modes 000 and 001. The software generates periph- eral-device cycles by modifying the DATAR and DCR registers and reading the ...
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When ACK is asserted the ECP drives AFD high. When AFD is high the peripheral device deasserts ACK. The ECP reads the PD7-0 byte, then drives AFD low. When AFD is low the peripheral device may change BUSY and PD7-0 ...
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THE PARALLEL PORT MULTIPLEXER (PPM) A PPM is used for a PC, which may have an internal Floppy Disk Drive (FDD) connected via regular FDC pins, to interface with either a printer or an external FDD, via a 25-pin ...
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Connector Pin PQFP Pin TQFP Pin ...
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Serial Communications Controllers (SCC1 and SCC2) Two serial communications control modules are pro- vided: SCC1 and SCC2. Either module supports a UART mode of operation and is backward compatible with the 16550 and 16450. In addition to UART mode, ...
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The UART mode is the default mode of operation af- ter power up or reset. In fact, after reset, the module enters the 16450 compatibility mode. In addition to the 16450 and 16550 compatibility modes, an extend- ed mode of ...
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The FIR transmitter front-end section adds the Pre- amble as well as Start and Stop flags to each frame and encodes the transmit data into a 4PPM (Four Pulse Position Modulation) data stream. The FIR re- ceiver front-end section strips ...
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High Speed Infrared Receive Operation When the receiver front-end detects an incoming frame, it will start de-serializing the infrared bit stream and load the resulting data bytes into the RX_FIFO. When the EOF is detected, two or four CRC ...
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The RC_MMD bits select the transmitter modulation mode. If C_PLS mode is selected, modulation pulses are generated continuously for the entire time in which one or more logic 0 bits are being transmitted. If 6_PLS or 8_PLS modes are selected, ...
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High-Data-Level interrupt occurs, to decide whether a number of bytes, as indicated by the RX_FIFO threshold, can be read without checking bit 0 of the LSR register. An ST_FIFO time-out is en- abled only in MIR and FIR modes, ...
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In order to avoid spurious fallbacks, baud generator divisor ports are provided in bank 2. Accesses of the baud generator divisor through these ports will change the baud rate setting but will not cause a fall back. New programs, designed ...
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The ID/IR_SL[2–0] pins will power up as inputs and can be driven by an external source. When in input mode, they can be used to read the identification data of Plug-n-Play infrared adapters. The ID0/IRSL0/IRRX2 pin can also function as ...
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RXD is accessed during CPU read cycles. It provides the read data path from the receiver holding register when the FIFOs are disabled, or from the RX_FIFO bottom location when the FIFOs are enabled. DMA cycles always access the transmitter ...
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Non-Extended Mode The function of EIR is the same as in the 16550. It re- turns an encoded value representing the highest pri- ority pending interrupt. While a CPU access is occurring, the module records new interrupts, but it does ...
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TXLDL_EV LS_EV/TX_HLT_EV MS_EV DMA_EV TXXEMP_EV/PPLD_EV SFIF_EV TMR_EV FIGURE 88. Event Identification Register, Extended Mode B0 RXHDLEV – Receiver High-Data-Level Event. FIFOs Disabled: Set ...
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FCR – FIFO Control Register Write Only Used to enable the FIFOs, clear the FIFOs and set the interrupt threshold levels. Upon reset, all bits are set ...
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Bits are only effective in UART, Sharp-IR and SIR modes. They are ignored in MIR, FIR and CEIR modes WLS1 STB ...
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BSR – Bank Select Register When bit bits 0–6 of BSR are used to select the bank. The encodings are shown in Table 80. TABLE 80. Bank Selection Encoding BSR Bits ...
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B0 DTR – Data Terminal Ready. This bit controls the DTR signal output. When it is set to 1, DTR is driven low. In loopback mode this bit internally drives both DSR and RI. B1 RTS – Request to Send. ...
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Cleared when the CPU reads all the data in the Holding Register or in the RX_FIFO. B1 UART, Sharp-IR, SIR, CEIR Modes OE – Overrun Error. This bit is set soon as an overrun condition is detected ...
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MSR – Modem Status Register The function of this register depends on the selected operational mode. When UART Mode is selected, this register provides the current-state as well as state- change information of the status lines from the MO- ...
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In MIR or FIR modes this bit can be used in con- junction with bit 1 to determine whether a number of bytes, as determined by the RX_FIFO thresh- old, can be read without checking the RXDA bit in the ...
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LBGD – Legacy Baud Generator Divisor Port This port provides an alternate data path to the baud generator divisor register implemented for com- patibility with the 16550 and to support existing legacy software packages. New software should ...
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TABLE 84. Baud Generator Divisor Settings Prescaler 13 Value Baud Rate Divisor % Error 50 2304 0.16% 75 1536 0.16% 110 1047 0.19% 134.5 857 0.10% 150 768 0.16% 300 384 0.16% 600 192 0.16% 1200 96 0.16% 1800 64 ...
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EXCR1 – Extended Control Register 1 Used to control the extended mode of operation. Upon reset all bits are set ...
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DMA Swap Configuration Logic Module RX - RX_DMA Channel DMA Logic Routing Logic TX - TX_DMA Channel DMA Logic DMASWP FIGURE 88. DMA Control Signals Routing 5.16.3 LCR/BSR – Link Control/Bank Select Registers These registers are the same as in ...
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TXFLV – TX_FIFO Level, Read- Only This register returns the number of bytes in the TX_FIFO. It can be used for software debugging, or during recovery from a transmitter underrun condition in one of the high-speed infrared modes. 7 ...
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BANK 4 TABLE 86. Bank 4 Register Set Address Register Description Offset Name 00h TMR(L) Timer Register (Low Byte) 01h TMR(H) Timer Register (High Byte) 02h IRCR1 Infrared Control Register 1 03h LCR/ Link Control/ BSR Bank Select Registers ...
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TFRL/TFRCC – Transmitter Frame-Length/Current-Count These registers share the same addresses. TFRL is always accessed during write cycles and is used to program the frame length, in bytes, for the frames to be transmitted. The frame length value does not ...
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When a pipeline operation takes place, the following occurs the target mode is MIR or FIR, the transmitter is halted for 250 the target mode is SIR, the transmitter is halted for 250 or a ...
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TFRCC terminal count effective in DMA mode. B6 SFTSL – ST_FIFO Threshold Select. An interrupt request is generated when the ST_FIFO level reaches the threshold or when an ST_FIFO time-out occurs. Bit Value Threshold Level Reserved. ...
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LOST_FR = 0 Least significant 8 bits of the received frame length. LOST_FR = 1 Number of lost frames RFRL(H) – Received-Frame-Length at ST_FIFO Bottom, Read-Only This register should be read only when the VLD bit in FRMST is 1. ...
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B3-0 MPW [3–0] – MIR Signal Pulse Width TABLE 89. MIR Pulse Width Settings Pulse Width ENCODING MDRS = 0 00XX Reserved 0100 83.33 ns 0101 104.16 ns 0110 125 ns 0111 145.83 ns 1000 166.66 ns 1001 187.50 ns ...
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TABLE 91. MIR Beginning Flags ENCODING Beginning Flags 0000 Reserved 0001 1 0010 2 (Default) 0011 3 0100 4 0101 5 0110 6 0111 8 1000 10 1001 12 1010 16 1011 20 1100 24 1101 28 1110 32 1111 ...
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TABLE 93. CEIR, Low Speed Demodulator (RXHSC = 0) (Frequency Ranges in kHz)þ 001 010 DFR [4-0] min max min 00011 28.6 31.6 27.3 29.3 32.4 28.0 00100 00101 30.1 33.2 28.7 31.7 35.1 30.3 00110 00111 32.6 36.0 31.1 ...
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TABLE 94. Consumer IR High Speed Demodulator Frequency Ranges in kHz (RXHSC = 1) 001 010 DFR [4-0] min max min 381.0 421.1 363.6 444.4 00011 01000 436.4 480.0 417.4 505.3 457.7 505.3 436.4 533.3 01011 TABLE 95. 001 010 ...
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IRTXMC – Infrared Transmitter Modulator Control Register Used to select the modulation subcarrier parameters for CEIR and Sharp-IR modes. For Sharp-IR, only the subcarrier pulse width is controlled by this register, the subcarrier frequency is fixed at 500 kHz. ...
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B7–5 MCPW [2–0] – Modulation Subcarrier Pulse Width. High Frequency, Low Frequency, Encoding TXHSC = 0 (CEIR or Sharp- (CEIR only) 000 Reserved 001 Reserved 010 6 s 011 7 s 100 9 s 101 10.6 s 110 Reserved 111 ...
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IRCFG1 – Infrared Interface Configuration Register 1 This register holds the transceiver configuration data for Sharp-IR and SIR Modes. When automatic configuration is not enabled used to directly control the transceiver operational mode. The least significant four bits ...
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They are unused when AMCFG when the ID/IRSL [2–0] pins are programmed as in- puts. Upon read, these bits return the values previ- ously written. B3 Reserved. Write 0. B6–4 FIRC [2–0] – FIR Mode Transceiver Config- ...
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IRSL0_DS, IRRX_MD and AUX_IRRX. B7 AMCFG – Automatic Module Configuration Enable. When set to 1, automatic infrared transceiver configuration is enabled. TABLE 97. (HIS_IR = 1 When Selected Mode is MIR ...
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Extended Mode Reset Required RXHDL_IE TXLDL_IE LS_IE / TXHLT_IE MS_IE DMA_IE TXEMP_IE / PLD_IE SFIF_IE (MIR and FIR only) TMR_IE Non-Extended Modes, Read Cycle ...
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Extended Mode Reset Required DTR RTS DMA_EN TX_DFR IR_PLS MDSL0 MDSL1 MDSL2 Non-Extended Mode ...
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Low Byte Register Reset Required Least Significant Byte of Baud Rate Generator High Byte Register ...
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Link Control Register Reset Required WLS0 WLS1 STB PEN EPS STKP SBRK BKSE FIFO Control Register ...
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Reception Frame Maximum Length LSB or Current Count LSB (RFRML(L) or RFRCC(L Reset Required Least Significant Bits of Reception Frame Length or Current Count ...
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Reception Frame Length FIFO Bottom MSB Register (RFRL(H Reset Required Least Significant Bits of Received Frame Length FIFO Bottom or of ...
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Infrared Configuration Reset 0 Required IRIC(2-0) Reserved SIRC(2-0) STRV_MS Infrared Configuration ...
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DMA and Interrupt Mapping The Chip provides Plug and Play support. 6.1 DMA SUPPORT 6.1.1 Legacy Mode Table 98 shows the conditions under which DMA re- quest signals are put in TRI-STATE, in legacy mode. For each DMA signal ...
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INTERRUPT SUPPORT 6.2.1 Legacy Mode Tables 100 and 101 describe the possible interrupt source for each IRQ, in legacy mode. A plus sign ( ) means this is a possible interrupt source and a minus sign ( ) means ...
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TABLE 102. Interrupt SCC1 As described in As described in IRQ3,4 Section 5. NA IRQ5,7 NA IRQ6 b NA IRQx 10, 11 6.2.2 Plug and Play ...
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TABLE 103. Interrupt Support in Plug and Play Mode for IRQ3 Interrupt SCC1 b + IRQx ...
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Power Management The chip places special emphasis on power manage- ment. Power management is implemented in the two major states of the chip: Power-Down and Power-Up. 7.1 POWER-DOWN STATE Power-down can be divided into two major groups: Group 1: ...
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— 3.3V DD — FCR bit 0 of SCC1 and SCC2 are 1 (16550 mode - FIFO enabled) 3. When PCR bit and ...
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TABLE 107. Clock Multiplier Encoding Options CLK Register (Index 51h) External Valid Clock Clock Clock on Multiplier Multiplier Pin X1 Status Enable (MHz 14.31818 0 = Reset Stable Always 0 0 Reserved ...
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... Device Description 8.1 GENERAL ELECTRICAL CHARACTERISTICS 8.1.1 Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (V DD) Input Voltage ( Output Voltage ( Storage Temperature (T STG) Power Dissipation ( Lead Temperature (T ...
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DC CHARACTERISTICS OF PINS, BY GROUP The following tables list the DC characteristics of all device pins described in Section 1.2 on page 22. The pin list preceding each table lists the device pins to which the table applies. ...
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TABLE 112. Parameter Input high voltage Input low voltage Input leakage current 8.2.4 Group 4 PIN LIST: DRV2, DSCKCHG, INDEX, MSEN1,0, RDATA, TRK0, WP TABLE 113. Parameter Symbol Input high voltage V IH Input low voltage V IL Input leakage ...
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TABLE 115. Parameter Input high voltage Input low voltage TABLE 116. Parameter Output high voltage Output low voltage Input TRI-STATE leakage current 8.2.7 Group 7 PIN LIST: BOUT2,1, DTR2,1, RTS2,1, SOUT2,1 TABLE 117. Parameter Output high voltage Output low voltage ...