MPC972

Manufacturer Part NumberMPC972
ManufacturerFreescale Semiconductor, Inc
MPC972 datasheet
 
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MPC972 MPC973
control of the MPC972/973 allows designers, under software
control, to implement unique power management schemes
into their designs. Although useful, individual output control
at the expense of one pin per output is too high, therefore a
simple serial interface was derived to economize on the
control pins.
The freeze control logic provides a mechanism through
which the MPC972 clock outputs may be frozen (stopped in
the logic ‘0’ state):
The freeze mechanism allows serial loading of the 12–bit
Serial Input Register, this register contains one program–
mable freeze enable bit for 12 of the 14 output clocks. The
Qc0 and QFB outputs cannot be frozen with the serial port,
this avoids any potential lock up situation should an error
occur in the loading of the Serial Input Register. The user
may programmably freeze an output clock by writing logic ‘0’
to the respective freeze enable bit. Likewise, the user may
programmably unfreeze an output clock by writing logic ‘1’ to
the respective enable bit.
The freeze logic will never force a newly–frozen clock to a
logic ‘0’ state before the time at which it would normally
transition there. The logic simply keeps the frozen clock at
logic ‘0’ once it is there. Likewise, the freeze logic will never
MOTOROLA
force a newly–unfrozen clock to a logic ‘1’ state before the
time at which it would normally transition there. The logic
re–enables the unfrozen clock during the time when the
respective clock would normally be in a logic ‘0’ state,
eliminating the possibility of ‘runt’ clock pulses.
The user may write to the Serial Input register through the
Frz_Data input by supplying a logic ‘0’ start bit followed
serially by 12 NRZ freeze enable bits. The period of each
Frz_Data bit equals the period of the free–running Frz_Clk
signal. The Frz_Data serial transmission should be timed so
the MPC972 can sample each Frz_Data bit with the rising
edge of the free–running Frz_Clk signal.
Start
D0
D1
D2
D3
D4
D5
D6
Bit
D0–D3 are the control bits for Qa0–Qa3, respectively
D4–D7 are the control bits for Qb0–Qb3, respectively
D8–D10 are the control bits for Qc1–Qc3, respectively
D11 is the control bit for QSync
Figure 16. Freeze Data Input Protocol
12
D7
D8
D9 D10 D11
TIMING SOLUTIONS
BR1333 — Rev 6