TDA5240 Infineon Technologies AG, TDA5240 Datasheet
TDA5240
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TDA5240 Summary of contents
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... TDA5240 En hanced Sensitivity M ulti-Cha nnel Qua d-C onfi gu rati with Digita band Pro ce ssing Wi re less Co ntro l Dat V4 rua ...
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... Edition February 19, 2010 Published by Infineon Technologies AG, Am Campeon 85579 Neubiberg, Germany © Infineon Technologies AG February 19, 2010. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. ...
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... TDA5240 En hanced Sensitivity M ulti-Cha nnel Qua d-C onfi gu rati with Digita band Pro ce ssing Wi re less Co ntro l Dat V4 rua ...
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... BOM components C7, C8, L1, R2 and R3 updated We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: Wirelesscontrol@infineon.com 010 2010-02-19 TDA5240_V3.4 V4.0 ...
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... Wake-Up Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 2.4.8.6 Frame Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 2.4.8.7 Message ID Scanning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.4.8.8 RUNIN, Synchronization Search Time and Inter-Frame Time . . . . . . 66 2.4.9 Power Supply Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 2.4.9.1 Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 2.4.9.2 Chip Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 2.5 System Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 2.5.1 Interfacing to the TDA5240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 2.5.1.1 Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 2.5.1.2 Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 2.5.2 Receive FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 2.5.3 Digital Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 2.5.4 Interrupt Generation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Data Sheet 5 TDA5240 Page V4.0, 2010-02-19 ...
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... Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 4 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 4.1 Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 4.1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 4.1.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 4.1.3 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 4.2 Test Circuit - Evaluation Board v1 154 4.3 Test Board Layout, Evaluation Board v1 155 4.4 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 5 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Appendix - Registers Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Data Sheet 6 TDA5240 Page V4.0, 2010-02-19 ...
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... SPI interface bus pre-configured telegram formats can be stored into the device offering independent pre-processing of the received data to an extent not available till now. The down converter can be also configured in single-conversion mode at moderately reduced selectivity performance but at the advantage of omitting the IF ceramic filter. Data Sheet Product Description 7 TDA5240 V4.0, 2010-02-19 ...
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... ESD protection +/- all pins • Package PG-TSSOP-28 1.3 Applications • Remote keyless entry systems • Remote start applications • Tire pressure monitoring • Short range radio data transmission • Remote control units • Cordless alarm systems • Remote metering Data Sheet Product Description 8 TDA5240 V4.0, 2010-02-19 ...
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... IFMIX _INN VDD5V VDDD VDDD1V5 GNDD PP0 PP1 PP2 P_ON XTAL1 Figure 1 Pin-out Data Sheet TDA5240 TDA5240 Functional Description 28 IF _OUT 27 VDDA 26 RSSI 25 PP3 24 GNDRF 23 LNA_INP LNA_INN SDO 18 SDI 17 SCK 16 NCS XTAL2 15 V4 ...
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... VDDA VDDA 330Ω IFBUF IFBUF_IN 330Ω VDDA VDDA 330Ω GNDA GNDA VDDA 330Ω 10 TDA5240 Functional Description Function Analog input IF Buffer input Note: Input is biased at VDDA/2 VDDA MIX2BUF Analog output IF Buffer output IFBUF Analog ground Analog input + IF mixer input ...
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... VDDD GNDD VDDD + VReg - = VDD1V5 GNDD VDD5V VDD5V PPx SDO GNDD GNDD 11 TDA5240 Functional Description Function Analog input digital supply input Analog output 1.5 Volt voltage regulator Digital ground Digital output CLK_OUT, RX_RUN, NINT, LOW, HIGH, DATA, DATA_MATCHFIL, CH_DATA, CH_STR, RXD and RXSTR ...
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... Pin 10 12 PP2 see schematic of Pin 10 13 P_ON P_ON NCS SCK SDI Data Sheet VDD5V VDDD GNDD GNDD 12 TDA5240 Functional Description Function Digital output CLK_OUT, RX_RUN, NINT, LOW, HIGH, DATA, DATA_MATCHFIL, CH_DATA, CH_STR, RXD and RXSTR are programmable via a SFR, ...
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... SDO see schematic of Pin Data Sheet VDDD .... GNDD GNDD VDDD VDDD .... GNDD GNDD GNDD 13 TDA5240 Functional Description Function Analog input crystal oscillator VDDD input GNDD Analog output crystal oscillator output XTAL2 Digital input SPI enable Digital input SPI clock ...
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... PP3 see schematic of Pin 10 26 RSSI RSSI Data Sheet LNA GNDRF LNA GNDRF VDDA VDDA 500Ω GNDA GNDA 14 TDA5240 Functional Description Function Analog input - RF input Analog input + RF input RF analog ground Digital output RX_RUN, NINT, LOW, HIGH, DATA, DATA_MATCHFIL, CH_DATA, CH_STR, ...
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... Pin Pad name Equivalent I/O Schematic No. 27 VDDA 28 IF_OUT IF_OUT Data Sheet VDD5V + VReg - = VDDA GNDA VDDA VDDA 330Ω GNDA GNDA 15 TDA5240 Functional Description Function Analog input Analog supply Analog output IF output PPFBUF V4.0, 2010-02-19 ...
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... Functional Block Diagram IFMIX_INN (5) IFMIX_INP (4) IFBUF_OUT (2) IFBUF_IN (1) IF_OUT (28) GNDA (3) Figure 2 TDA5240 Block Diagram 1) The function on each PPx port pin can be programmed via SFR (see also in squared brackets in Figure Data Sheet (CERFSEL TDA5240 Functional Description Table 1). Default values are given V4.0, 2010-02-19 ...
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... The crystal oscillator serves as the reference frequency for the PLL phase detector, the clock signal of the Sigma-Delta modulator and divided by two as the 2 signal. To accelerate the start up time of the crystal oscillator two modes are selectable: a Low Power Mode (with lower precision) and a High Precision Mode. Data Sheet Functional Description 17 TDA5240 nd local oscillator V4.0, 2010-02-19 ...
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... Block Overview The TDA5240 is separated into the following main blocks: • Receiver • Crystal Oscillator and Clock Divider • Sigma-Delta Fractional-N PLL Synthesizer • ASK / FSK Demodulator incl. AFC, AGC and ADC • RSSI Peak Detector • Digital Baseband Receiver • ...
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... IF1 10.7 MHz 10 .7 MHz optional ΣΔ Modulator N Channel select Multi Modulos :1/:2/:3 IQ Divider : 4 PD Divider : N_FN Band select Loop Filter LF select 19 TDA5240 Functional Description I- LP digital Mix2 harm sup FSK Demod ASK / LP Q- RSSI alias sup RSSI Generator Mix2 ADC Divider ...
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... The order of such ceramic filters range the selectivity is further improved and a better channel separation is guaranteed. Data Sheet × center corner low corner high rd order bandpass polyphase filter might be 20 TDA5240 Functional Description , rd order intercept point of the I- LP digital Mix2 harm sup FSK Demod ASK / LP Q- RSSI ...
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... Double Down Conversion (DDC) with two external filters Data Sheet CER- Filter IF1 10.7 MHz CER- CER- Filter Filter IF1 IF1 10.7 MHz 10.7 MHz optional 21 TDA5240 Functional Description I- LP digital Mix2 harm sup FSK Demod ASK / LP Q- RSSI alias sup RSSI Generator Mix2 ...
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... The SFR control bit XTALHPMS can be used to activate the High Precision Mode also during SLEEP Mode. Oscillator -Core XTAL1 Figure 7 Crystal Oscillator Data Sheet f sys (DGND) XTAL2 22 TDA5240 Functional Description Setting XTALCAL0 9 automatically controlled XTALCAL1 ( ≤ 1pF steps ) XTALHPMS V4.0, 2010-02-19 ...
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... Register changes larger than 1 pF are automatically handled by the TDA5240 in 1pF steps • After the Oscillator is trimmed, the TDA5240 can be set to SLEEP mode and keeps these values during SLEEP mode • Add the settings of XTALCAL0/1 to the configuration. It must be set after every power ...
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... A clock output frequency higher than 1 MHz is not supported. For high sensitivity applications, the use of the external clock generation unit is not recommended. Data Sheet f sys f = -------------------------------------------- - ⋅ CLKOUT 2 divisionfactor Enable LK_OU T 24 TDA5240 Functional Description Enable f Divide C LK _OU V4.0, 2010-02-19 ...
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... To 1 mixer IQ Divider ÷ 4 Channel FN Figure 9 Synthesizer Block Diagram Data Sheet 3.6 GHz VCO Loop Filter Band Select ÷1/÷2/÷3 Multi- modulus Divider ΣΔ Modulator AFC filter AFC-data 25 TDA5240 Functional Description CP PFD QOSC 22MHz V4.0, 2010-02-19 ...
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... LSB is always high, and is clocked by the XTAL oscillator. This determines the achievable frequency resolution. The Automatic Frequency Control Unit filters the actual frequency offset from the FSK demodulator data and calculates the necessary correction of the divider factor to achieve the nominal IF center frequency. Data Sheet Functional Description Chapter 2.4.3 RF/IF 26 TDA5240 V4.0, 2010-02-19 ...
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... RSSI Slope Dig. Gain Peak Memory RSSI Offset Control Filter RSSI Peak Detector register Begin of config / Figure 15). 27 TDA5240 Functional Description AFC track/freeze AFC RF PLL ctrl loop filter FSK/ASK Rate adapter Bypass Rate doubler Decimation 8 … 16 samples /chip (data rate dependent ) ...
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... This limit can be used to avoid the AFC from drifting in the presence of interferers or when no RF input signal is available (AFC wander). A maximum AFC limit of 42 kHz is recommended. AFC wandering needs to be kept in mind especially when using Run Mode Slave. Data Sheet Functional Description rd order digital filter. The 28 TDA5240 V4.0, 2010-02-19 ...
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... AFCOFFSET, when AFC is activated. The value is in signed representation and has a frequency resolution of 2.68 kHz/digit. The output can be limited by the x_AFCLIMIT register. Data Sheet integrator 1 limit integrator 2 hold K2 limit x4 hold x_AFCK2CFG0 integrator 2 gain 29 TDA5240 Functional Description x_AFCLIMIT SDPLL FreqOffset scaling & HOLD limiting Freeze* / Track Delay x_AFCAGCD V4.0, 2010-02-19 ...
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... Analog RSSI output curve with AGC action ON (blue) vs. OFF (black) Data Sheet Figure 3) can be fine tuned "manually" by means path is either after the 2 nd mixer. & BPF bypassed AGC OFF margin hy s teres is 30 TDA5240 Functional Description nd poly-phase AGC ON Input power V4.0, 2010-02-19 ...
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... IF can be observed when using the 50kHz BPF or even about 16dB when using the 300kHz BPF. The input power level at which the AGC switches back to maximum gain is -66dBm - 21.3dB (default AGCHYS) = -87dBm. This provides enough margin against the minimum sensitivity. Data Sheet Functional Description 31 TDA5240 V4.0, 2010-02-19 ...
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... Table 3 can be applied. AGC AGC Threshold Threshold 1) Offset Low TDA5240 Functional Description Table 2 can be AGC RSSI Input Threshold Range Up Reduction 2 AGC Threshold V4.0, 2010-02-19 ...
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... ASK low duration the integrator is actually slightly discharged due to the decay set by PMFDN. The AGC start and freeze times are programmable. The same conditions can be used as in the corresponding AFC section above. They will however, be programmed in separate SFR registers. Data Sheet Functional Description 33 TDA5240 V4.0, 2010-02-19 ...
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... The input voltage of the ADC is in the range Therefore VDDD/2 (= 1.65 V typical) is used to monitor VDDD. Further details on the measurement and calibration procedure for temperature and VDDD can be taken from the corresponding application note. Data Sheet 10). 34 TDA5240 Functional Description V4.0, 2010-02-19 ...
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... Data Sheet Compare Peak Detector Payload Divide ADC Integrate Dump RSSI I&D Averaging Filter Compare Peak Detector to 35 TDA5240 Functional Description EOM Update Update Peak Peak Value RSSIPPL Value Register Load FSYNC Peak Detector Track Control Bit position ...
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... Computation Delay due to filtering and signal calculation. Figure 14 Peak Detector Behavior Data Sheet Figure 10) is used to measure the input signal Chapter 2.4.8.5 Wake-Up Generator Unit .... SPI FSync n = PKBITPOS 36 TDA5240 Functional Description .... EOM Noise TSI Run-In *1 EOM V4.0, 2010-02-19 and .... FSync ...
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... If IF Attenuation is trimmed, this has to be done before trimming of RSSI 4. If RSSI needs to be trimmed in a higher input power range the AGCGAIN must be set accordingly Data Sheet for required RSSI for required value 37 TDA5240 Functional Description -P ) IN2 IN1 slope SLOPER as RSSIR2 at ...
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... MUX SIGN Data Invert DATA_MATCHFIL (Matched Filtered Data for external processing ) Figure 10). The MF has to be adjusted accordingly to 38 TDA5240 Functional Description Blind Sync Initial Phase & Data rate CR PLL CDR PLL Slicer chip_data_clock Chip chip_data Data Chip Data Data ...
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... FAR (False Alarm Rate) performance, but then the MER/BER (Message Error Rate/Bit Error Rate) performance will decrease. On the other hand, the MER/BER performance can be increased by setting smaller SIGDET threshold levels but then the FAR performance will worsen. Data Sheet Functional Description 39 TDA5240 V4.0, 2010-02-19 ...
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... SPWR and NPWR can be read via the final application. A complete configuration file using right modulation, data rate and Run Mode Slave, must be prepared and downloaded to the TDA5240. Signal Detector Threshold for ASK Take 500 readings of SPWR (50 are also possible, but this leads to less accurate results) with no RF input signal applied (=noise only) ...
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... Threshold settings should be verified by testing receiver sensitivity over the input frequency range, with a step size of 100Hz, at minimum FSK deviation with all combinations of minimum and maximum data rate and duty cycle. Further detailed information can be taken from the corresponding Application Note. Data Sheet Functional Description 41 TDA5240 V4.0, 2010-02-19 ...
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... The Code Violations (CV) M (mark) and S (space), are coded as low/high signal levels. 1st Chip Figure 18 Manchester Symbols including Code Violations Data Sheet Data Clock 2nd 1st 2nd 1st 2nd Chip Chip Chip Chip Chip 42 TDA5240 Functional Description Figure M 1st 2nd Chip Chip V4.0, 2010-02-19 15). ...
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... When x_CDRRI.RUNLEN is set to small values, then the I-part is less accurate (residual error) and can lead to a longer needed PLL settling time and worse performance in the Data Sheet Timing Extrapolation Phase PI Detector Loop Filter / 2 43 TDA5240 Functional Description EOM Symbol Sync found Digital Recovered Controlled Clock Oscillator ...
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... Figure 20 RUNIN Generation Principle Data Sheet ). data first edge RUNIN bits detected first edge RUNIN bits detected 44 TDA5240 Functional Description Chapter 2.4.8.6 Frame V4.0, 2010-02-19 ...
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... TVWIN time is the time during which the Digital Baseband Receiver should stay locked without any incoming signal edges detected. The time resolution is T/16. Calculation of TVWIN can be seen at the end of subsection TSI Gap Mode in Chapter 2.4.8.6 Frame Synchronization. Data Sheet Functional Description Chapter 2.4.8.6 Frame 45 TDA5240 V4.0, 2010-02-19 ...
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... Data Sheet TOLCHIPH lim_bit_low = 16 - TOLBITL 46 TDA5240 Functional Description TOLBITH TOLBITL lim_bit_high = 16 + TOLBITH Figure 21, tighter ...
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... For each configuration there exists one bit (register x_CDRRI.DRLIMEN) to switch the data rate acceptance limitation functionality on or off. Data rate acceptance limitation is disabled by default. All configurations share the same threshold registers, the default Data Sheet CLOCK RECOVERY Data Rate Acceptance Limitation Clock Recovery PLL 47 TDA5240 Functional Description & cdr_lock cdr_clock V4.0, 2010-02-19 ...
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... Everything inside the zero thresholds (zero-tube) becomes a 0. After that, the decoding to the chip-level representation is done by mapping the - "0" chip and the "1" chip. A zero out of the data slicer is decoded to chip-level by referencing to the previous chip value. Data Sheet Functional Description 48 TDA5240 V4.0, 2010-02-19 ...
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... In bit mode the data slicer has only one threshold (zero) to distinguish between the two levels of the matched filter output. The data slicer internally maps a positive value and a negative value to a -1. After that, the selected line decoding is applied. Summary of data slicer modes in the TDA5240: Data Slicer Chip mode: • ...
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... Wake-up on Level can be set in the x_WULOT register. The Wake-up on Level criterion can be handled very quickly for FSK modulation, while in case of ASK the nature of this modulation type has to be kept in mind. Data Sheet Functional Description Chapter 2.6.2.3) for further decreasing the 50 TDA5240 V4.0, 2010-02-19 ...
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... Pattern Detector RSSI WU on Level Criteria Signal Recognition Sync Random Bits WU on Data Criteria Equal Bits Pattern 51 Functional Description WU Level Criterion WUW Chip Counter Wake-up Elapsed Generation FSM Code Violation Detected Bit Change Detected 15 Pattern Detected Selection x_WUC V4.0, 2010-02-19 TDA5240 ...
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... Several interferer measurements are recommended to suppress this, what makes sense anyway for a better distribution. Data Sheet wanted signal interferer wanted signal noise floor Figure 10, Chapter 2.4.7 RSSI Peak and Chapter 2.6.2.3 Fast Fall Back to 52 TDA5240 Functional Description x_WURSSIBHy x_WURSSIBLy x_WURSSITHy Detector, V4.0, 2010-02-19 ...
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... On using Data Slicer Bit Mode, the Wake-up criteria Equal Bits Detection and Pattern Detection cannot be applied. Further details can be seen at the end of The selection of 1 out of 4 wake-up data criteria is done via the x_WUC register. Data Sheet bit Chapter 2.4.8.8 RUNIN, Synchronization Search 53 TDA5240 Functional Description ) and the duration for the Chapter 2.4.8.4. V4.0, 2010-02-19 ...
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... Valid Data Rate Detection Wake-up condition is fulfilled if symbol synchronization is possible inside of Sync Search Time out (see Chapter 2.4.8.8 RUNIN, Synchronization Search Time and Inter- Frame Time). WUBCNT is not used. This is the weakest wake-up data criterion, and should be avoided. Data Sheet Functional Description 54 TDA5240 V4.0, 2010-02-19 ...
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... Counter<WUBCNT No WU=0 SSync=0 CV=1 WUW Chip Counter elapsed (WUW Chip Counter = WUBCNT) (WUW Chip Counter = WUBCNT) Wake-Up WU=1 No WU=0 No Wake-Up WU=0 No WU=1 55 Functional Description SSync=1 Wakeup Criteria=Valid Data Rate Equal Bits SSync= 0 Detection CV= 1 WU=0 Bit Change Detected=1 No WU=0 WUW Chip Counter elapsed V4.0, 2010-02-19 TDA5240 SSync =1 Detection ...
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... LRB Correlator A 16-bit TSI Data-Pattern TSI Data -Pattern MSB LSB MSB Delay-Line 16-bit LRB Correlator B 16-bit TSI Data-Pattern TSI Data -Pattern MSB LSB MSB 56 TDA5240 Functional Description EOMSYLO EOMDATLEN EOM-Detector x_EOMDLEN x_EOMDLENP x_TSILENA Correlator A Controller Frame Synchron - ization Controller x_TSIMODE x_TSIGAP ...
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... RunIn x_TSIPTB TDA5240 Functional Description Chapter 2.4.8. ...
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... RunIn x_TSIPTA TDA5240 Functional Description x_TSIPTB 1110 ...
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... TSI A pattern can be preset in the x_EOMDLEN register. The second criterion is the detection of a Code Violation. This EOM criterion is not applicable for Data Slicer Bit mode. Data Sheet Functional Description Chapter 2.4.8.3 Clock and Data Chapter 2.4.8.4 Data Slicer and 59 TDA5240 Recovery. V4.0, 2010-02-19 ...
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... Phase readjustment only, TSIGRSYN = 0. In this mode, the value in GAPVAL is used to correct the phase after the gap phase. Overall gap time can be defined in T/16 Data Sheet Functional Description clock recovery reset start point TSI GAP GAPSync PLL sync internal PLL sync 60 TDA5240 valid data TSI B < 1bit V4.0, 2010-02-19 ...
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... Data Sheet clock recovery phase readjustment start point all space or all mark TSI GAP PLL sync ] [ ] = TSIGAP chips + 6… TSIGAP chips + TSILENB chips 61 TDA5240 Functional Description valid data TSI B GAPSync [ ] + 11 nd chip. V4.0, 2010-02-19 ...
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... Functional Description GapSync TSIB Start of TSIB Stop of TSIB comparison TVWIN GAP RUNIN/ TSIGRSYN = 1 ) 1.25 ⋅ ⋅ ⋅ TSIA + + 8 CV V4.0, 2010-02-19 TDA5240 comparison Figure 34. ) 1.25 ⋅ ...
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... If the MID Unit finishes ID matching without success, the data receiving is stopped and the FSM waits again for a Frame Start criterion. The received bits are still stored in the FIFO. Data Sheet Functional Description 63 TDA5240 V4.0, 2010-02-19 ...
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... Data Sheet MID0:MID3 32 32 MID4:MID7 MID8:MID11 32 32 MID12:MID15 MID16:MID19 32 Scan Start Position Reached Scan End Position Bit Counter Reached Organization Digital-Receiver 64 TDA5240 Functional Description MID found Control- MID Scanning finished FSM Interface to Master FSM Init MID Scanner Enable MID Scanning from V4.0, 2010-02-19 ...
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... MID6:MID7 16 MID8:MID9 16 MID10:MID11 16 16 MID12:MID13 16 MID14:MID15 MID16:MID17 16 MID18:MID19 16 Scan Start Position Reached Scan End Position Bit Counter Reached Organization Digital-Receiver 65 TDA5240 Functional Description MID found Control- MID Scanning finished FSM Interface to Master FSM Init MID Scanner Enable MID Scanning from V4.0, 2010-02-19 ...
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... Further details on this topic can be gained from Chapter 2.6.1.5 Data Sheet Byte0 Byte0 Byte1 Byte0 Byte1 Byte0 Byte1 Figure 72). This wake-up sequence allows a very fast decision, and Chapter 2.4.8.5. 66 TDA5240 Functional Description Byte2 Byte2 Byte3 38. The protocol starts with a V4.0, 2010-02-19 ...
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... Code Violation (see register x_SLCCFG) Data Sheet TSI PAYLOAD Figure 39. TSI TSI TSI 12.5µ 1 0 TDA5240 Functional Description RUNIN RUNIN PLL re-synchronization RUNIN the delay between ADC 1 is the time between Symbol 2 V4.0, 2010-02-19 ...
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... T bit has to be added. 1 ⎛ 0.5T ⎜ = 1.5T + Inter Frame – bit ⎝ 68 Functional Description ⎞ 16 ⎞ 1.1 ⎞ ⋅ ⋅ RUNLEN ⎠ ⎠ ⎠ ⎞ ⎛ ⎞ T ⎟ ⎜ ⎟ bit 1 + ⎠ ⎝ ⎠ V4.0, 2010-02-19 TDA5240 and has a ...
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... In case a voltage drop of VDDD below approximately 2. detected a RESET will be initiated. Data Sheet IN IN Voltage Regulator RX_RUN 5 → 3.3 V OUT OUT IN RF Voltage Regulator 3.3 → 1.5 V Section OUT Power-Up Brownout Detector 69 TDA5240 Functional Description VDD5V VDDD Digital-I/O VDDD1V5 Reset- Internal Digital-Core Circuit Reset GNDD V4.0, 2010-02-19 ...
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... Supply-Application in 5V environment *) When operating environment, the voltage-drop across the voltage regulators 5 operating range. Resistive or capacitive loads (in excess to the scheme shown above) on pins VDDA and VDDD are not recommended. 70 TDA5240 Functional Description TDA5240 VDD5V VDDA VDDD 100n VDDD1V5 100n 100n ...
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... If the IF buffer amplifier or the clock generation feature (PPx pin active) are enabled, the respective currents must be added. Data Sheet , depending on the selected trimming RFstartdelay t COSCsettle t RXstartup 71 TDA5240 Functional Description ), the crystal oscillator 1 to settle at the trimmed COSCsettle when leaving SLEEP RXstartup is I RFstartdelay RF-FE-startup,BPFcal V4.0, 2010-02-19 ...
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... PP2 pin is undefined (NINT signal) Supply voltage falls below Functional - Threshold Supply voltage A ‚LOW’ is generated rises above at NINT signal Functional - Threshold 72 TDA5240 Functional Description µC reads A ‚HIGH’ is Interrupt- generated at Status-Register PP2 pin (NINT signal) A ‚LOW’ is generated at PP2 pin (NINT signal) V4 ...
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... NINT signal is forced to low. Now, the IC starts operation in the SLEEP Mode, ready to receive commands via the SPI interface. The NINT signal will go high, when one of the Interrupt Status registers is read for the first time. Data Sheet Functional Description 73 TDA5240 V4.0, 2010-02-19 ...
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... RF signal is demodulated and the corresponding data is made available to the Application Controller. Optionally, a chip clock is generated by the TDA5240. Since the data signal is always directly the baseband representation of the RF signal, we call this mode the Transparent Mode. The ...
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... Logical and electrical System Interfaces of the TDA5240 2.5.1.1 Control Interface The control interface is used in order to configure the TDA5240 after start- re- configure it during run-time, as well as to properly react on changes in the status of the receiver in the Application Controller’s firmware. The control interface offers a bi- directional communication link by which • ...
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... Data Interface The data interface between the Application Controller and the TDA5240 receiver IC is used for the transport of the received data, see as well as the features of the data interface depend on the selected mode of operation. There are 5 possible receive modes: • Packet Oriented FIFO Mode (POF) • ...
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... Figure 47 Data interface for the Packet Oriented Transparent Payload Mode In the TDA5240, there are specific digital output lines (PPx pin) for the Bi-phase decoded data and an appropriate Strobe signal. During inactivity of the receiver, the line is in default mode switched to low. ...
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... Figure 49 Data interface for the Transparent Mode - Chip Data and Strobe In the TDA5240, there is a specific digital output line for the chip clock estimate as well as for the data output line, which delivers the encoded chip data. During inactivity of the receiver, the line is in default mode switched to low. ...
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... One-Chip Matched Filter on the DATA signal (PPx pin). See more details in the block diagram in Data Sheet /2. The polarity of the CH_STR signal is CHIP CHIP Figure 15. scheduler 79 TDA5240 Functional Description /8 relative to CHIP data interface TDA5240 RX data Figure 15. V4.0, 2010-02-19 D n+1 ...
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... On time registers of the chip. The interrupt for Wake-Up Config B (WUB) is enabled and suitable RSSI thresholds are set. If the RSSI signal valid threshold area, the TDA5240 changes to Run Mode Self Polling and an interrupt can be signaled to the Application Controller. In case the RSSI signal is outside the valid threshold area, the chip stays in Self Polling Mode and the external controller gets no interrupt (as the desired RSSI level is not reached) ...
Page 81
... Wake-up on Signal Recognition is/is not disabled Data Sheet ConfigA ConfigB RSSI level too low Chip stays in Self Polling Mode and sends no interrupt 81 TDA5240 Functional Description OFF-time µC detects invalid data and sends „EXTTOTIM“ goto SPM µC finished data reception, sends „EXTEOM found“ ...
Page 82
... MUX Out Bit-Address Read-Port FIFO-Overflow FIFO- Controller SDO-Frame Generator # of Valid Bits 82 TDA5240 Functional Description Read Address Pointer (Up-Counter) SCLK RESET ENABLE to SPI-Bus SDO fifolk to FSM ) to address zero. Writing to the d V4.0, 2010-02-19 ...
Page 83
... FSM switches from Self Polling Mode to Run Mode Self Polling INITFIFO (Init Fifo@ Cycle Start Figure 54 FIFO Lock Behavior Data Sheet Accept Data EOM=0 Write Data into FIFO EOM=1 EOM=1 FIFOLK=0 FIFOLK=1 FIFO Lock FIFO Empty = 0 FIFOLK=1 Wait till FIFO is empty FIFOLK=0 FIFO Empty=1 83 TDA5240 Functional Description V4.0, 2010-02-19 ...
Page 84
... FIFO, while the next payload frame gets already received and payload data is further stored in the FIFO. Data Sheet FIFO Bits D0 D1 D30 D31 84 TDA5240 Functional Description Status Word V4.0, 2010-02-19 ...
Page 85
... Configuration separately. Every PPx can be configured with an individual RX_RUN setup. This can be set in RXRUNCFG0 and RXRUNCFG1 registers. Interfacing to 3.3V Logic: The TDA5240 is able to interface directly to a 3.3V logic, when chip is operated in 3.3V environment. Interfacing to 5V Logic: The TDA5240 is able to interface directly logic, when chip is operated in 5V environment ...
Page 86
... RC low pass circuit. 2.5.4 Interrupt Generation Unit The TDA5240 is able to signal interrupts (NINT signal) to the external Application Controller on one of the PPx port pins (for further details see Output Pins). The Interrupt Generation Unit receives all possible interrupts and sets the NINT signal based on the configuration of the Interrupt Mask registers (IM0 and IM1) ...
Page 87
... RESET PP2_select=NINT PP2INV SPI READ IS0 IS0 X FF PP2(NINT) WU(A,B) FSYNC(A,B) MID(A,B) EOM(A,B) Figure 57 Interrupt Generation Waveform (Example for Configuration A+B) Data Sheet Interrupt-Mask NINT Interrupt-Signalling NINT signal ConfigA 87 TDA5240 Functional Description IS1 + IS0 IM1 + IM0 Reset ConfigB V4.0, 2010-02-19 ...
Page 88
... Data Sheet 58) A 8-bit @2MHz = 4us irq2 (masked?) read /readb data = IS(t+0) addr read/capture IS* content IS(t+0) 88 TDA5240 Functional Description Figure 58) B SFR IS* read clear @end of data frame IS(t+1) 0x00 NOTE: SFR IS(j) status flag is cleared before it can be read if an IRQ occurs during SPI data frame ...
Page 89
... high impedance Z SDO Figure 59 Read Register Data Sheet Instruction Data Out TDA5240 Functional Description Frame Register Address Data Out V4.0, 2010-02-19 ...
Page 90
... Data Sheet Data Out (i) Data Out (i+ TDA5240 Functional Description Data Out (i+ V4.0, 2010-02-19 ...
Page 91
... Functional Description Frame Instruction Register Address Data Byte (i+1) Data Byte (i+ V4.0, 2010-02-19 TDA5240 8 Data Byte ...
Page 92
... Instruction I7 I6 Status Word D30 D31 Functional Description enable every 8 bit read/clear Frame FIFO Bits Status Word D0 D1 D30 D31 Instruction Format 0000 0010 0000 0011 0000 0100 0000 0001 V4.0, 2010-02-19 TDA5240 ...
Page 93
... Serial Input Timing NCS SCK t CLK_SDO Z SDO SDI ADDR LSB Figure 66 Serial Output Timing Data Sheet t Setup t t SDI_setup SDI_hold high impedance Z t CLK_H t t CLK_SDO CLK_L 93 TDA5240 Functional Description t Deselect CLK_H hold not_setup t CLK_L t t SDO_disable SDO_r t SDO_f V4.0, 2010-02-19 Z ...
Page 94
... Chip Serial Number Every device contains a unique, preprogrammed 32-bit wide serial number. This number can be read out from SN3, SN2, SN1 and SN0 registers via the SPI interface. The TDA5240 always has SN0.6 set to 1 and SN0.5 set to 1. Fuses Figure 67 ...
Page 95
... The following operation modes and the behavior of the Master Control Unit are fully automatic and only influenced by SFR settings and by incoming RF data streams. The TDA5240 has two major operation modes, which are switched by SFR bit MSEL. In Slave Mode the device is controlled via SPI by the external microcontroller. This mode supports: • ...
Page 96
... Mode Chip is periodically active and searching for WU criteria Bit:SLRXEN == X Bit:MSEL == 1 ToTim Timeout == 1 Run Mode Self Polling Chip is permanently active Chapter 2.5.1.2 Data Interface). 96 TDA5240 Functional Description Run Mode Bit:SLRXEN == 1 Slave Bit:MSEL == 0 Chip is permanently active Bit:SLRXEN == X Bit:MSEL == 1 WUC found == 0 Bit:SLRXEN == X Bit:MSEL == 1 WUC found == 1 ...
Page 97
... Otherwise the state machine may hang up. Reconfigurations in HOLD Mode are faster, because there is no Start-Up sequence. The following flowchart and explanation show and help to understand the internal behavior of the Finite State Machine (FSM) in Run Mode Slave. Data Sheet Functional Description 97 TDA5240 V4.0, 2010-02-19 ...
Page 98
... Analyze The Scanning Result MID Found=1 11 EOM Check EOM Found == 1 Store RX Data Into FIFO Check For EOM EOM Found == 0 98 TDA5240 Functional Description Startup Finished == 0 INITDRXES ==1 INITDRXES ==0 Generating A Frame Start Interrupt If Not Masked Generating A MID Found Interrupt If Not Masked Generating A EOM Interrupt If Not Masked V4 ...
Page 99
... The limits are +/- 1 MHz for the 315 MHz band, +/- 1.5 MHz for the 434 MHz band and +/- 3 MHz for the 868/915 MHz band. When this additional VAC routine is enabled, the TDA5240 starts initialization of the Digital Receiver block after release from HOLD and an additional Channel Hop time. ...
Page 100
... TDA5240 mode is changed to Run Mode Self Polling for automatic verification of TSI, optional MIDs and for transfer of payload data into the FIFO. A general overview on a typically transmitted protocol and the behaviour of the TDA5240 is given in Figure 72 ...
Page 101
... three different channels. Then, there is an optional search for a wake-up criterion according to Configuration B, C and D, again including channels. In applications using only Single-Configuration, settings are always taken from Configuration A. Data Sheet Functional Description Chapter 2.6.2 Polling Timer Switching, Chapter 2.4.8.5 Wake- (in Subsection TMRDS). 101 TDA5240 V4.0, 2010-02-19 ...
Page 102
... Permanent WU Search Mode Enable == 0 Permanent WU Search Mode Enable == 1 Loop Counter == 11 Load Load 11 Channel 2 Channel 3 Initialize RX-Part Initialize RX-Part Multi Channel A Multi Channel A 10 Increment Loop Counter Incrementation Of The Loop Counter Generating WU CFG A Interrupt If Not Masked From Compare of V4.0, 2010-02-19 TDA5240 Config ...
Page 103
... CfgLoopCounter == CfgNr 8 Store Channel Store The Current Channel Configuration Into Actual Channel Register 12 Run Mode Self Polling Chip is permanently active of Config C,D 103 TDA5240 Functional Description Loop Counter == 10 Loop Counter == Load Load Channel 2 Channel 3 Initialize RX-Part Initialize RX-Part Multi Channel B,C,D Multi Channel B,C,D ...
Page 104
... SFR control bit MT. 2.6.1.7 Multi-Channel in Self Polling Mode As previously mentioned, in Self Polling Mode the TDA5240 allows RF scans three RF channels per configuration, this can be defined in the x_CHCFG register. Channel frequencies are defined in registers x_PLLINTCy, x_PLLFRAC0Cy, x_PLLFRAC1Cy, x_PLLFRAC2Cy, where and ...
Page 105
... TX signal Wake-up RX_RUN WU-data Interrupt RunMode SelfPolling SelfPolling / Sleep Init TOTIMs TOTIM_SYNC counter activity TOTIM_TSI 9.5ms counter activity TOTIM_EOM counter activity Figure 75 TOTIM Behavior without Presence of Interferer Data Sheet 76. RI TSI Payload1 5ms 105 TDA5240 Functional Description RI TSI Payload2 5ms V4.0, 2010-02-19 ...
Page 106
... Cycle Start, that means whenever Run Mode Self Polling is entered or • Frame Start, when a TSI has been successfully identified (and Receive FIFO is not locked). Further information about the Receive FIFO can be found in the FIFO. Data Sheet RI TSI Payload1 *) 106 TDA5240 Functional Description RI TSI Payload2 Chapter 2.5.2 Receive V4.0, 2010-02-19 ...
Page 107
... After an EOM was found, the information about the RF channel and the configuration of the actual payload data is saved in the RFPLLACC register. After detection of EOM the TDA5240 can either proceed with a search for a wake-up criterion in the next configuration or a search for wake-up in Configuration A can follow or the TOTIMs of the current configuration are reloaded for being prepared to receive another (redundant) payload data frame within the same configuration ...
Page 108
... Result MID Found == 1 11 EOM Check Store RX Data Into FIFO Check For EOM PWUF = PWUEN bit ToTim Timeout EOM == 0 EOM Found == 0 108 TDA5240 Functional Description To Self Polling Mode (WU Search With Next Programmed Channel) To Self Polling Mode (WU Search With TOTIM2nCh == 1 Configuration A ) TOTIM2nCh == 0 ...
Page 109
... While the TDA5240 is in Run Mode Self Polling, further Wake-ups would normally not be detected by the receiver. If the functionality of a parallel Wake-up search during the search for a TSI is desired, this can be activated by the PWUEN bit. In this case the Wake-up search is not active during a recognized payload and is only active after the first received payload frame, as can be seen from used, when modulation type is the same for SPM and RMSP ...
Page 110
... Generate external EOM Write EXTPCMD 0x01 4. Disable external processing Write x_CHCFG.EXTPROC = 0x0 5. Unforce Symbol Sync Write 0xED 0x00 Symbol Sync = 0 110 TDA5240 Functional Description TIMEOUT -> SLEEP -> SPM or (dependent on application ) EXT_TOTIM: (Write x_CHCFG.EXTROC = 0x2) (Write EXTPCMD 0x02) (Write x_CHCFG.EXTROC = 0x0) Deactivate Symbol Sync on PPx (example for RX_RUN) Write PPCFG0 ...
Page 111
... TSI = 000001, all bits Manchester encoded). This function can be activated by the INITFRCS bit, so then there is no reset of the framer compare shift register after a Wake-up event, which can shorten the required processing time. Data Sheet Functional Description 111 TDA5240 V4.0, 2010-02-19 ...
Page 112
... The On-Off Timer and the Active Idle Period Timer are used to generate the polling signal. The entire unit is controlled by the SPM FSM. The TDA5240 is able to handle up to four different sets of configurations automatically. However, the examples and figures in this subsection only show up to two configuration sets for the sake of clarity ...
Page 113
... A detected wake-up data sequence or an actual value for RSSI or Signal Recognition (a combination of Signal Detector and Noise Detector, see certain adjustable threshold forces the TDA5240 into Run Mode Self Polling. In all modes the timing resolution is defined by the Reference Timer, which scales the ...
Page 114
... The longer the Off time, the lower the average power consumption in Self Polling Mode. On the other hand, the Off time has to be short enough that no transmitted wake-up Data Sheet OFF T OFF BON OFF 114 TDA5240 Functional Description Channels = MasterPeriod AON OFF Channels = m ...
Page 115
... Instead of the single RSSI criterion also the Signal Recognition criterion can be activated. Data Sheet has to be reduced by the related additional OFF t t WULOT WULOT and Chapter 2.4.8.5 Wake-Up 115 TDA5240 Functional Description Figure 81 last observation time WULOT WULOT_part window is forced to end by n-1 n end ...
Page 116
... Wake-up search is completed positively. When a Data Criterion is found to be not OK, the Wake-up search is terminated independent of the state of the Wake-Up on Level FSM. Therefore both FSMs are initialized. Data Sheet can be applied additionally 116 TDA5240 Functional Description by setting the bit V4.0, 2010-02-19 ...
Page 117
... If there is no synchronization to a bit stream within the so-called Sync Search Time Out (SYSRCTO), the wake-up search for this channel is stopped. If synchronization to a bit stream is possible (and not lost again), the TDA5240 waits if the wake-up criterion is fulfilled. If the wake-up criterion is not fulfilled (in worst case, if the ...
Page 118
... The On and Off time setting is different from the Constant On-Off Time Mode. The entire On time is defined in the SPMONTA0 and SPMONTA1 registers. Regardless of the Data Sheet Figure 10, Chapter 2.4.7 RSSI Peak Detector Generator): WULCUFFB WUCRT & & 118 TDA5240 Functional Description and UFFB criterion & WU criterion Wake-up Generation FSM V4.0, 2010-02-19 ...
Page 119
... Data Sheet Chapter 2.5.1.2 Data T OFF T MasterPeriod T OFF T MasterPeriod OFF T MasterPeriod Chapter 2.4.8.8 RUNIN, Synchronization Search Time and 119 TDA5240 Functional Description Interface) can be used: Channels = MasterPeriod AON OFF Channels = MasterPeriod AON OFF Channels Config Channels Config ...
Page 120
... Data Sheet Chapter 2.5.1.2 Data T OFF T MasterPeriod T T BON OFF T MasterPeriod BON OFF T MasterPeriod 120 TDA5240 Functional Description Interface) can be used: Channels = MasterPeriod AON BON OFF Channels = m MasterPeriod AON BON OFF Channels Config Channels Config ...
Page 121
... OFF T MasterPeriod OFF T MasterPeriod OFF T MasterPeriod 121 TDA5240 Functional Description Interface) can be used: Channels = MasterPeriod AON OFF Channels = AON OFF MasterPeriod Channels Config Channels Config AON OFF MasterPeriod ...
Page 122
... SPMAP and the SPMIP registers. The values of these registers determine the factor M and N. run mode RX polling sleep mode T On Figure 87 Active Idle Period Data Sheet . With this Active Idle Period selection MasterPeriod T Off T MasterPeriod M*T N*T MasterPeriod MasterPeriod Active Idle 122 TDA5240 Functional Description V4.0, 2010-02-19 ...
Page 123
... Data Sheet symbols bitrate = --------------------- - s × chiprate = n bitrate Level-based Definition MDC = Duration of H-level / Symbol period MDC < 50 MDC > 50 123 TDA5240 Functional Description V4.0, 2010-02-19 ...
Page 124
... Data Sheet chip MDC = -------- - = -------------------------- - A T bit Chip-based Definition MDC = Duration of the first chip / Symbol period MDC < MDC > 50 124 Functional Description Δ bit 1. bit T 1 .chip T bit V4.0, 2010-02-19 TDA5240 ...
Page 125
... bit -T the Manchester duty cycle is calculated to rise Δ chip = ------------------------- - T T bit bit 125 TDA5240 Functional Description Δ bit – T chip fall rise = ----------------------------------------------- - ...
Page 126
... Symbolizes SFR registers or SFR control bit (s) with Multi-Configuration capability (protocol specific). In case of SFR register, the name starts with D_, depending on the selected configuration. This is generally noted by the prefix „x _“. 126 TDA5240 Functional Description Power level specification value 6dB ...
Page 127
... Reserved 640 3) d Common Registers 4) Reserved 767 d 768 Page 3 2) Reserved 896 3) d Common Registers 4) Reserved 1023 d 127 TDA5240 Functional Description physical address space 1) Configuration A - Page 0 2) Reserved 3) Common Registers 4) Reserved 1) Configuration B - Page 1 2) Reserved 1) Configuration C - Page 2 2) Reserved 1) Configuration D ...
Page 128
... Data Sheet Functional Description 128 TDA5240 V4.0, 2010-02-19 ...
Page 129
... Data Sheet RF in SAW filter SPI Bus TDA5240 to/from µC , e.g. the crystal frequency or a SRC ) of it, which can act as interferer (EMI SRC 129 TDA5240 Applications V4.0, 2010-02-19 ...
Page 130
... Assuming a harmonic ( impact on the sensitivity there. In this case another XTAL frequency shall be selected, e.g. 10 kHz away | SRC LocalOscillator Example (e.g. EMI source TDA5240 XOSC 21.948717 MHz ==> XOSC For further details please refer to the corresponding application note or to the latest configuration software. 3.1 Configuration Example Please see configuration files supplied with the Explorer tool ...
Page 131
... R 140 th(ja) P 100 tot HBMRF V -500 500 SDM V -750 750 SDM I 100 LU V -0.3 V inmax DD5V or 6 IOmax 131 TDA5240 Reference Unit Remarks °C °C K According to ESD Standard JEDEC EIA / JESD22-A114 AEC-Q100 (transient current) +0.5 V whichever is lower mA V4.0, 2010-02-19 ...
Page 132
... Supply Operating Range and Ambient Temperature Parameter # B1 Supply voltage at pin VDD5V B2 Supply voltage at pin VDD5V=VDDD=VDDA B3 Ambient temperature Data Sheet Symbol Limit Values min. max. V 4.5 5.5 DD5V V 3.0 3.6 DD3V3 T -40 105 amb 132 TDA5240 Reference Unit Remarks V Supply voltage range 1 V Supply voltage range 2 °C V4.0, 2010-02-19 ...
Page 133
... I 115 350 sleep_high I PDN 0.8 1.5 3 clock I 0.5 0.7 Buffer 133 TDA5240 Reference o C and VDD5V = 5.0V or VDD5V = Unit Test Conditions Remarks mA ASK or FSK mode P < -50dBm in mA ASK or FSK mode P < -50dBm in crystal oscillator in Low Power Mode; clock generator off; µA valid for SLEEP Mode and during SPM Off time µ ...
Page 134
... NINT_Pulse T +/- 23 Error, uncal T +/- 4.5 Error, cal V +/- 200 DDD, Error, uncal V +/- 25 DDD, Error, cal 134 TDA5240 Reference Unit Test Conditions Remarks Note: No SPI communication is allowed before XOSC start-up is finished and chip reset is already finished µs Time to startup RF frontend (comprises time ...
Page 135
... FSK Manchester, differential Manchester, Bi-phase Mark / Bi-phase Space chip T data chip T data 135 TDA5240 Reference Unit Test Conditions Remarks st MHz 1 Local Oscillator Low Side LO-injection MHz and High Side LO- injection allowed; MHz See also Chapter 3 MHz ...
Page 136
... BER SFSK5 -110 -107 BER SFSK6 -106 -103 BER SFSK7 -110 -107 BER 136 TDA5240 Reference Unit Test Conditions Remarks -3 BER = 2*10 RF input matched to 50 Ω °C; amb Single-Ended Matching without SAW; Insertion loss of input matching network = 1dB; Receive Mode = TMMF (sampled with ideal data clock) ...
Page 137
... BER SASK8 -104 -101 BER ΔS 0 0.5 1 SDC Δ DDC, IFATT7 137 TDA5240 Reference Unit Test Conditions Remarks -3 BER = 2*10 RF input matched to 50 Ω °C, amb peak power level (see Chapter 2.7.3); Single-Ended Matching without SAW; Insertion loss of input matching network = 1dB; ...
Page 138
... P -16 -14 IIP3 P -27 -25 CP1dB 30 40 image1 image2 138 TDA5240 Reference Unit Test Conditions Remarks dB dB relative °C; amb temperature drift of crystal not considered dB AFC inactive; For Sensitivity Bandwidth see Table 11 dB AFC active, slow AFC; For Sensitivity Bandwidth ...
Page 139
... SE C 1.56 in_p 290 330 380 out_IF FE, max FE_7 139 TDA5240 Reference Unit Test Conditions Remarks Ω differential parallel equivalent input between pF LNA_INP and LNA_INN Ω pF Ω pF Ω pF Ω single-ended parallel equivalent input between pF LNA_INP and GNDRF / Ω ...
Page 140
... SSB_LO -79 -74 -77 -72 -116 -111 -130 -125 -57 -47 140 TDA5240 Reference Unit Test Conditions Remarks dB max. IF attenuation (IFATT = 15); input matched to 50 Ω; Insertion loss of input matching network = 1dB = 330 Ω; R load_IF tested at 434 MHz dB 12dB / 15 = 0.8dB/step Double Down ...
Page 141
... TEMP V 0.8 2.0 RSSI+ DRSSI -4 +2 ana RSSI dV mix_in DRSSI -4 +2 dig_u 141 TDA5240 Reference Unit Test Conditions Remarks dBc kHz LNA input to Limiter output, excluding external CER filter Ω 10...12 MHz IF Ω 10...12 MHz 10...12 MHz IF = 330 Ω Z source = 330 Ω ...
Page 142
... BW 50 -3dB 80 125 200 300 tol_BW -5 +5 -3dB tol_BW -6 +6 -3dB 142 TDA5240 Reference Unit Test Conditions Remarks dB RSSI register readout LSB RSSI register readout; /dB typical 600 mV/ mV/dB, 1mV = 1 LSB (10-bit ADC) 8-bit readout: 4mV=1LSB LSB RSSI register readout; /dB typical 600 mV/ ...
Page 143
... XTAL Δ X_step f 11 5.5M clock_out t 292 292 292 COSCsettle t 0.45 1 start_up 143 TDA5240 Reference Unit Test Conditions Remarks MHz fF Ω nominal value ppm oscillator untrimmed (trim capacitor default settings, usage of recommended crystal); not including crystal tolerances ppm larger trimming range ...
Page 144
... VDD5V VDD5V V Out_High1 -0 0.4 Out_Low1 V VDD5V VDD5V V Out_High2 -0 0.8 Out_Low2 144 TDA5240 Reference Unit Test Conditions Remarks V µ µA IOH=-500 µA, static driver capability; Normal Pad Mode (see register PPCFG2 and CMC0) V IOL=500 µA, static driver capability; Normal Pad Mode ...
Page 145
... CLK_SDO t 40 CLK_SDO t 90 SDO_r t 90 SDO_f t 15 SDO_r t 15 SDO_f t 25 SDO_disable 145 TDA5240 Reference Unit Test Conditions Remarks MHz Note: A high SPI clock rate during data reception can reduce sensitivity load High Power Pad not ...
Page 146
... Unless explicitly otherwise noted, the following test conditions apply to the given specification values in Table 10 * Hardware: TDA5240 Platform Testboard V1.0 * Single-Ended Matching for 315.0 MHz / 433.92 MHz / 868.3 MHz / 915.0 MHz * RF input matched to 50 Ω; Insertion loss of input matching network = 1dB * Receive Frequency 315.0 MHz / 433.92 MHz / 868.3 MHz / 915.0 MHz; Lo-Side LO-Injection * Reference Clock: XTAL=21 ...
Page 147
... Symbol Limit Values min. typ. max tolManch_DefB 35 55 tolManch_DefC 45 55 tolManch_DefB 35 55 tolManch_DefC 147 TDA5240 Reference Unit Test Conditions Remarks % 50% % According to Definition B in Chapter 2.7.2; including DRE of -10% to +10%; Data Rate < 50 kBit/s % According to Definition C in Chapter 2.7.2 including DRE of -10% to +10%; ...
Page 148
... SASK3 -111 -108 SASK4 -109 -106 SASK5 -115 -112 SASK6 -112 -109 SASK7 -106 -103 148 TDA5240 Reference Unit Test Conditions Remarks 50% and DRE = 0 °C, amb peak power level (see Chapter 2.7.3) dBm m = 100% nd peak kHz; ...
Page 149
... SFSK3 -112 -109 SFSK4 -106 -103 SFSK5 -108 -105 SFSK6 -107 -104 SFSK7 -109 -106 149 TDA5240 Reference Unit Test Conditions Remarks dBm m = 100% nd peak 300 kHz; IFATT = 7, CDR = fast; Data Slicer Bit Mode; Note: 3dB sensitivity loss @ f = +/-100 kHz ...
Page 150
... DR2,OOK -10 -105 DR10,OOK -45 -103 DR2,ASK50 DR10,ASK50 -60 -99 DR10,AM0 -10 -106 DR10,AM90 -10 -90 150 TDA5240 Reference Unit Test Conditions Remarks 50% and DRE = 0 °C, amb peak power level (see Chapter 2.7.3) dBm m = 100% nd peak kHz; IFATT = 0, CDR = normal; Data Slicer Bit Mode ...
Page 151
... TDA5240 Reference Data Rate [bit/s], Manchester 230 230 230 230 280 280 280 280 150 - - - 220 - - - 160 - ...
Page 152
... TDA5240 Reference Data Rate [bit/s], Manchester 180 180 180 180 220 220 220 220 140 - - - 190 - - - 130 - - - ...
Page 153
... TDA5240 Reference Data Rate [bit/s], Manchester 120 120 120 120 150 150 150 150 100 - - - 120 - - - 100 - - - 120 ...
Page 154
... Test Circuit - Evaluation Board v1.0 Figure 94 Test Circuit Schematic Data Sheet 154 TDA5240 Reference V4.0, 2010-02-19 ...
Page 155
... Test Board Layout, Evaluation Board v1.0 Figure 95 Test Board Layout, Top View Figure 96 Test Board Layout, Bottom View Data Sheet 155 TDA5240 Reference V4.0, 2010-02-19 ...
Page 156
... Figure 97 Test Board Layout, Component View Data Sheet 156 TDA5240 Reference V4.0, 2010-02-19 ...
Page 157
... X7R +/- 10% X7R +/- 10% +/- 2% +/- 2% +/- 2% +/- 2% +/- 5% +/- 5% +/- 5% C0=1.7 pF C1=7 fF CL=12 pF 157 TDA5240 Reference Manufacturer Remark/Options (RF+supply variant) Infineon crystal oscillator load crystal oscillator load 3. environment) matching for 315MHz matching for 434MHz matching for 868MHz matching for 915MHz matching for 315MHz matching for 434MHz ...
Page 158
... Device / Tolerance Type X7R +/- 10% X7R +/- 10% Tantal +/- 10% X7R +/- 10% X7R +/- 10% LS M676- P251-1 158 TDA5240 Reference Manufacturer Remark/Options (RF+supply variant) EEPROM for board detection RSSI measurement low pass polarized capacitor filter network on supply line filter network on supply line no filter network on supply line RSSI measurement ...
Page 159
... Ordering Code TDA5240 SP000550860 You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”:http://www.infineon.com/products SMD = Surface Mounted Device Data Sheet C 0.1 28x 159 TDA5240 Package Outlines 1) 4.4 ±0.1 B +0.15 0.6 -0.1 6.4 0.2 B 28x Package PG-TSSOP-28 Dimensions in mm ...
Page 160
... Power Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Table 7 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Table 8 Supply Operating Range and Ambient Temperature . . . . . . . . . . . . . 132 Table 9 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Table 10 MER Characteristics (Receive Mode = POF 147 Table 11 Typical Achievable Sensitivity Bandwidth [kHz 151 Table 12 Order Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Data Sheet 160 TDA5240 Page V4.0, 2010-02-19 ...
Page 161
... List of Figures Figure 1 Pin-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 2 TDA5240 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 3 Block Diagram RF Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 4 Single Down Conversion (SDC, no external filters required Figure 5 Double Down Conversion (DDC) with one external filter . . . . . . . . . . . 21 Figure 6 Double Down Conversion (DDC) with two external filters . . . . . . . . . . 21 Figure 7 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 8 External Clock Generation Unit ...
Page 162
... Figure 43 Reset Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Figure 44 Logical and electrical System Interfaces of the TDA5240 . . . . . . . . . . 75 Figure 45 Receive Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Figure 46 Data interface for the Packet Oriented FIFO Mode . . . . . . . . . . . . . . . 77 Figure 47 Data interface for the Packet Oriented Transparent Payload Mode . . 77 Figure 48 Timing of the Packet Oriented Transparent Payload Mode . . . . . . . . . 78 Figure 49 Data interface for the Transparent Mode - Chip Data and Strobe ...
Page 163
... Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Figure 94 Test Circuit Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Figure 95 Test Board Layout, Top View 155 Figure 96 Test Board Layout, Bottom View . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Figure 97 Test Board Layout, Component View . . . . . . . . . . . . . . . . . . . . . . . . 156 Figure 98 PG-TSSOP-28 Package Outline (green package 159 Data Sheet 163 TDA5240 V4.0, 2010-02-19 ...
Page 164
... Data Sheet 164 TDA5240 V4.0, 2010-02-19 ...
Page 165
... Appendix - Registers Chapter Data Sheet 165 TDA5240 V4.0, 2010-02-19 ...
Page 166
... A_WURSSIBL1 RSSI Wake-Up Blocking Level Low Channel 1 Register A_WURSSIBH1 RSSI Wake-Up Blocking Level High Channel 1 Register A_WURSSITH2 RSSI Wake-Up Threshold for Channel 2 Register 01E Data Sheet Register Description 166 TDA5240 Appendix Register Overview Offset Address Page Number 000 193 H 001 193 H ...
Page 167
... H 036 H 037 H 038 H 039 H 03A H 03B H 03C H 03D H 03E H 03F H 040 H 167 TDA5240 Appendix Register Overview Page Number 207 207 208 208 208 209 209 210 210 211 211 212 212 213 214 214 215 215 215 216 217 218 ...
Page 168
... H 057 H 058 H 059 05D 061 080 H 168 TDA5240 Appendix Register Overview Page Number 225 225 226 227 227 228 229 230 231 232 232 233 233 234 235 235 236 236 237 237 237 ...
Page 169
... H 09B H 09C H 09D H 09E H 09F H 0A0 H 0A1 H 0A2 H 0A3 H 0A4 H 0A5 H 169 TDA5240 Appendix Register Overview Page Number 246 247 249 250 251 252 252 252 253 254 254 255 255 256 257 257 257 258 258 259 260 261 ...
Page 170
... H 103 H 104 H 105 H 106 H 107 H 108 H 109 H 10A H 10B H 10C H 10D H 170 TDA5240 Appendix Register Overview Page Number 270 271 271 272 274 275 275 275 276 276 277 277 278 278 279 279 280 280 280 281 281 281 ...
Page 171
... H 110 H 111 H 112 H 113 H 114 H 115 H 116 H 117 H 118 H 119 H 11A H H 11C H 11D H H 11F H 120 H H 122 H 123 H 124 H 125 H 126 H 127 H 128 H 129 H 12A H 12B H 12C H 12D H 12E H 12F H 171 TDA5240 Appendix Register Overview Page Number V4.0, 2010-02-19 ...
Page 172
... H 133 H 134 H 135 H 136 H 137 H 138 H 139 H 13A H 13B H 13C H 13D H 13E H 13F H 140 H 141 H 142 H 143 H 144 H 145 H 146 H 147 H 148 H 149 H 14A H 14B H 14C H 14D H 14E H 14F H 150 H 151 H 152 H 172 TDA5240 Appendix Register Overview Page Number V4.0, 2010-02-19 ...
Page 173
... H 156 H 157 H 158 H 159 15D 161 200 H 201 H 202 H 203 H 204 H 205 H 206 H 207 H 208 H 209 H 20A H 20B H 20C H 20D H 20E H 20F H 210 H 211 H 212 H 213 H 173 TDA5240 Appendix Register Overview Page Number V4.0, 2010-02-19 ...
Page 174
... H 216 H 217 H 218 H 219 H 21A H H 21C H 21D H H 21F H 220 H H 222 H 223 H 224 H 225 H 226 H 227 H 228 H 229 H 22A H 22B H 22C H 22D H 22E H 22F H 230 H 231 H 232 H 233 H 234 H 235 H 174 TDA5240 Appendix Register Overview Page Number V4.0, 2010-02-19 ...
Page 175
... H 239 H 23A H 23B H 23C H 23D H 23E H 23F H 240 H 241 H 242 H 243 H 244 H 245 H 246 H 247 H 248 H 249 H 24A H 24B H 24C H 24D H 24E H 24F H 250 H 251 H 252 H 253 H 254 H 255 H 256 H 257 H 258 H 175 TDA5240 Appendix Register Overview Page Number V4.0, 2010-02-19 ...
Page 176
... H H 25D 261 300 H 301 H 302 H 303 H 304 H 305 H 306 H 307 H 308 H 309 H 30A H 30B H 30C H 30D H 30E H 30F H 310 H 311 H 312 H 313 H 314 H 315 H 316 H 317 H 318 H 319 H 176 TDA5240 Appendix Register Overview Page Number V4.0, 2010-02-19 ...
Page 177
... H H 31C H 31D H H 31F H 320 H H 322 H 323 H 324 H 325 H 326 H 327 H 328 H 329 H 32A H 32B H 32C H 32D H 32E H 32F H 330 H 331 H 332 H 333 H 334 H 335 H 336 H 337 H 338 H 339 H 33A H 33B H 177 TDA5240 Appendix Register Overview Page Number V4.0, 2010-02-19 ...
Page 178
... H 33E H 33F H 340 H 341 H 342 H 343 H 344 H 345 H 346 H 347 H 348 H 349 H 34A H 34B H 34C H 34D H 34E H 34F H 350 H 351 H 352 H 353 H 354 H 355 H 356 H 357 H 358 H 359 35D H H 178 TDA5240 Appendix Register Overview Page Number V4.0, 2010-02-19 ...
Page 179
... Wake-Up Control Register A_WUPAT0 Wake-Up Pattern Register 0 A_WUPAT1 Wake-Up Pattern Register 1 A_WUBCNT Wake-Up Bit or Chip Count Register A_WURSSITH1 RSSI Wake-Up Threshold for Channel 1 Register 01B Data Sheet Register Description 179 TDA5240 Appendix Register Overview Offset Address Page Number H H 361 ...
Page 180
... H 02D H 02E H 02F H 030 H 031 H 032 H 033 H 034 H 035 H 036 H 037 H 038 H 039 H 03A H 03B H 03C H 03D H 180 TDA5240 Appendix Register Overview Reset Value ...
Page 181
... H 04D H 04E H 04F H 050 H 051 H 052 H 053 H 054 H 055 H 056 H 057 H 058 H 059 05D 181 TDA5240 Appendix Register Overview Reset Value ...
Page 182
... H 090 H 091 H 092 H 093 H 094 H 095 H 096 H 097 H 098 H 099 H 09A H 09B H 09C H 09D H 09E H 09F H 0A0 H 182 TDA5240 Appendix Register Overview Reset Value ...
Page 183
... H 0B6 H 0B7 H 0B8 H 0B9 H 0BA H 0BB H 0BC H 0BD H 100 H 101 H 102 H 103 H 104 H 105 H 106 H 107 H 108 H 183 TDA5240 Appendix Register Overview Reset Value ...
Page 184
... H 119 H 11A H H 11C H 11D H H 11F H 120 H H 122 H 123 H 124 H 125 H 126 H 127 H 128 H 129 H 12A H 184 TDA5240 Appendix Register Overview Reset Value ...
Page 185
... H 13D H 13E H 13F H 140 H 141 H 142 H 143 H 144 H 145 H 146 H 147 H 148 H 149 H 14A H 14B H 14C H 14D H 185 TDA5240 Appendix Register Overview Reset Value ...
Page 186
... 200 H 201 H 202 H 203 H 204 H 205 H 206 H 207 H 208 H 209 H 20A H 20B H 20C H 20D H 20E H 186 TDA5240 Appendix Register Overview Reset Value ...
Page 187
... H 220 H H 222 H 223 H 224 H 225 H 226 H 227 H 228 H 229 H 22A H 22B H 22C H 22D H 22E H 22F H 230 H 187 TDA5240 Appendix Register Overview Reset Value ...
Page 188
... H 243 H 244 H 245 H 246 H 247 H 248 H 249 H 24A H 24B H 24C H 24D H 24E H 24F H 250 H 251 H 252 H 253 H 188 TDA5240 Appendix Register Overview Reset Value ...
Page 189
... H 304 H 305 H 306 H 307 H 308 H 309 H 30A H 30B H 30C H 30D H 30E H 30F H 310 H 311 H 312 H 313 H 314 H 189 TDA5240 Appendix Register Overview Reset Value ...
Page 190
... H 326 H 327 H 328 H 329 H 32A H 32B H 32C H 32D H 32E H 32F H 330 H 331 H 332 H 333 H 334 H 335 H 336 H 190 TDA5240 Appendix Register Overview Reset Value ...
Page 191
... H 349 H 34A H 34B H 34C H 34D H 34E H 34F H 350 H 351 H 352 H 353 H 354 H 355 H 356 H 357 H 358 H 359 H 191 TDA5240 Appendix Register Overview Reset Value ...
Page 192
... D_PLLFRAC1C3 PLL Fractional Division Ratio Register 1 Channel 3 363 D_PLLFRAC2C3 PLL Fractional Division Ratio Register 2 Channel 3 364 Data Sheet Offset Address 35D 361 192 TDA5240 Appendix Register Overview Reset Value ...
Page 193
... Bits Type MID1 7:0 w Message ID Register 2 A_MID2 Message ID Register 2 Data Sheet Offset 000 H Description Message ID Register 0 Reset Offset 001 H Description Message ID Register 1 Reset Offset 002 H 193 TDA5240 Appendix Register Description Reset Value 00 H Reset Value 00 H Reset Value 00 H V4.0, 2010-02-19 ...
Page 194
... Message ID Register 4 Field Bits Type MID4 7:0 w Message ID Register 5 Data Sheet Description Message ID Register 2 Reset Offset 003 H Description Message ID Register 3 Reset Offset 004 H Description Message ID Register 4 Reset 194 TDA5240 Appendix Register Description Reset Value 00 H Reset Value 00 H V4.0, 2010-02-19 ...
Page 195
... Bits Type MID7 7:0 w Data Sheet Offset 005 H Description Message ID Register 5 Reset Offset 006 H Description Message ID Register 6 Reset Offset 007 H Description Message ID Register 7 Reset 195 TDA5240 Appendix Register Description Reset Value 00 H Reset Value 00 H Reset Value 00 H V4.0, 2010-02-19 ...
Page 196
... Bits Type MID9 7:0 w Message ID Register 10 A_MID10 Message ID Register 10 Data Sheet Offset 008 H Description Message ID Register 8 Reset Offset 009 H Description Message ID Register 9 Reset Offset 00A H 196 TDA5240 Appendix Register Description Reset Value 00 H Reset Value 00 H Reset Value 00 H V4.0, 2010-02-19 ...
Page 197
... A_MID13 Message ID Register 13 Data Sheet Description Message ID Register 10 Reset Offset 00B H Description Message ID Register 11 Reset Offset 00C H Description Message ID Register 12 Reset Offset 00D H 197 TDA5240 Appendix Register Description Reset Value 00 H Reset Value 00 H Reset Value 00 H V4.0, 2010-02-19 ...
Page 198
... Message ID Register 15 Field Bits Type MID15 7:0 w Message ID Register 16 Data Sheet Description Message ID Register 13 Reset Offset 00E H Description Message ID Register 14 Reset Offset 00F H Description Message ID Register 15 Reset 198 TDA5240 Appendix Register Description Reset Value 00 H Reset Value 00 H V4.0, 2010-02-19 ...
Page 199
... Bits Type MID18 7:0 w Data Sheet Offset 010 H Description Message ID Register 16 Reset Offset 011 H Description Message ID Register 17 Reset Offset 012 H Description Message ID Register 18 Reset 199 TDA5240 Appendix Register Description Reset Value 00 H Reset Value 00 H Reset Value 00 H V4.0, 2010-02-19 ...
Page 200
... UNUSED Reset Message ID Scan Start Position Min: 00h = Comparision starts one Bit after FSYNC Max Comparision starts 128 Bits after FSYNC Reset Offset 015 H 200 TDA5240 Appendix Register Description Reset Value 00 H Reset Value 00 H Reset Value 00 H V4.0, 2010-02-19 ...