MT9125AP Mitel, MT9125AP Datasheet
MT9125AP
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MT9125AP Summary of contents
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... ADPCMo ENA Transcoder 2 VDD VSS PWRDN MT9125AE MT9125AP Description The Dual-channel ADPCM transcoder is a low power, CMOS device capable of two encoder functions and two decoder functions. Two 64 kbit/s PCM channels are compressed into two 32 kbit/s ADPCM channels, and two 32 kbit/s ADPCM channels are expanded into two 64 kbit/s PCM channels ...
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MT9125 24 PIN PDIP 28 PIN PLCC Pin Description Pin # Name DIP PLCC 1 2 MCLK Master Clock input. This 4.096 MHz clock is used as an internal master clock and must be provided during both ST-BUS and SSI ...
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Preliminary Information Pin Description (continued) Pin # Name DIP PLCC 6 7 BCLK Bit Clock input for both PCM and ADPCM ports; used in SSI mode only. The falling edge of this clock is used to clock data in on ...
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MT9125 Pin Description (continued) Pin # Name DIP PLCC 22 26 EN1 Channel 1 Output Enable strobe. This output is decoded from the ST-BUS C4i and F0i signals and its position, within the ST-BUS stream, may be controlled via the ...
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Preliminary Information For ST-BUS operation (i.e., when a valid ST-BUS frame pulse is applied to the F0i input) the bit rate, at 2.048 MHz, is generated internally from the master clock input at the MCLK pin. The BCLK and ENA ...
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MT9125 F0i Channel 0 B1 DSTi/o EN1 EN2 ADPCMi/o EN1 EN2 ADPCMi/o In ST-BUS mode the ENA, ENB1 and ENB2 input strobes are ignored. All timing is dervied internally from the F0i, MCLK and ENS inputs. the device and must, ...
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Preliminary Information Mode Selection (MS1, MS2, MS3, MS4) Separate mode select pins are available for per- channel B1 and B2 operation. MS1 and MS2 are used to configure the B1 channel while MS3 and MS4 configure the B2 channel. Normally ...
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MT9125 frame n-1 DSTi PCM Byte "X" latched into device during frame n-1 ADPCMo ENA ENB1 or EN1 MS1/3 1,1=32 kb/s MS2/4 This diagram shows the conversion sequence from PCM to ADPCM. The same pipelining occurs in the reverse ADPCM ...
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Preliminary Information MT8910 F0b C4b L + out out DSTo DSTi FPi C4i DSTi DSTo Gate Array Ring Generator Hookswitch to SLICs from SLICs Figure 7 - Pair Gain Application ...
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MT9125 configuration the ENB1 and ENB2 inputs are ignored. If F0i is tied continuously to V operation will be assumed and the transcoder will use the strobes connected to ENB1 and ENB2 as its internal reference. Power-Down Operation (PWRDN) To ...
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Preliminary Information MT8910 C4ib F0b C4b L + out L - out DSTo DSTi FPob FPb System Frame pulse or delayed frame pulse from previous selection MT8980 C & D Channel Switch 1/2 bandwidth ...
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MT9125 Absolute Maximum Ratings* Parameter 1 Supply Voltage 2 Voltage on any I/O pin 3 Continuous Current on any I/O pin 4 Storage Temperature 5 Power Dissipation 6 Latch-up Immunity * Exceeding these values may cause permanent damage. Functional operation ...
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Preliminary Information AC Electrical Characteristics Voltages are with respect to ground (V ) unless otherwise stated. SS Characteristics 1 Data Clock High 2 Data Clock Low 3 BCLK Period 4 Data Output Delay (excluding first bit) 5 Output Active to ...
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MT9125 t BCL BCLK t S SSS S ENB1 I or ENB2 b7 DSTi DSTo S MCLK F0iH U S F0i t F0iS t BCL BCLK t S SSS S I ENA b1-1 ...
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Preliminary Information AC Electrical Characteristics Voltages are with respect to ground (V ) unless otherwise stated. SS Characteristics 1 Delay MCLK falling to C2o rising 2 Delay MCLK falling to Enable † Timing is over recommended temperature & power supply ...
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MT9125 NOTES: 8-32 Preliminary Information ...