PM6388-RI PMC-Sierra Inc, PM6388-RI Datasheet
PM6388-RI
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PM6388-RI Summary of contents
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... DATA SHEET PMC-1971019 OCTAL E1 FRAMER PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC. AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM6388 EOCTL DATA SHEET ISSUE 6: JANUARY, 2000 PM6388 EOCTL OCTAL E1 FRAMER ...
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... E1 TRANSMITTER (E1-TRAN)................................................... 34 9.10 TRANSMIT PER-CHANNEL SERIAL CONTROLLER (TPSC).... 34 9.11 TRANSMIT DATA LINK INSERTER (TXCI)................................. 35 9.12 FACILITY DATA LINK TRANSMITTER (TDPR) .......................... 35 9.13 RECEIVE AND TRANSMIT DIGITAL JITTER ATTENUATOR (RJAT, TJAT)........................................................................................... 36 PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER i ...
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... PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 NON-MULTIPLEXED BUS INGRESS MODES............. 40 MULTIPLEXED BUS INGRESS MODE ........................ 42 NON-MULTIPLEXED BUS EGRESS MODES.............. 43 MULTIPLEXED EGRESS INTERFACE ........................ 45 INGRESS MULTIPLEXED BUS CONFIGURATION ... 263 EGRESS MULTIPLEXED BUS CONFIGURATION .... 264 LINE LOOPBACK ....................................................... 280 DIAGNOSTIC DIGITAL LOOPBACK .......................... 280 PM6388 EOCTL OCTAL E1 FRAMER ii ...
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... EOCTL I/O TIMING CHARACTERISTICS ........................................... 310 17 ORDERING AND THERMAL INFORMATION...................................... 322 18 MECHANICAL INFORMATION............................................................ 323 PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PER-TS LOOPBACK .................................................. 281 INITIALIZATION.......................................................... 283 DIRECT ACCESS MODE ........................................... 283 INDIRECT ACCESS MODE ........................................ 283 PM6388 EOCTL OCTAL E1 FRAMER iii ...
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... REGISTERS 00DH, 08DH, 10DH, 18DH, 20DH, 28DH, 30DH, 38DH: CLOCK MONITOR 81 REGISTERS 00EH, 08EH, 10EH, 18EH, 20EH, 28EH, 30EH, 38EH: INGRESS FRAME PULSE CONFIGURATION.................................................................. 83 PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER iv ...
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... REGISTERS 023H, 0A3H, 123H, 1A3H, 223H, 2A3H, 323H, 3A3H: RJAT CONFIGURATION .......................................................................................... 109 REGISTERS 024H, 0A4H, 124H, 1A4H, 224H, 2A4H, 324H, 3A4H: TJAT INTERRUPT STATUS...................................................................................... 111 PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER v ...
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... REGISTER 02CH, 0ACH, 12CH, 1ACH, 22CH, 2ACH, 32CH, 3ACH (TXCISEL = 1): TXCI TRANSMIT DATA LINK 3 CONTROL ............................................... 131 REGISTERS 02DH, 0ADH, 12DH, 1ADH, 22DH, 2ADH, 32DH, 3ADH (TXCISEL = 1): TXCI DATA LINK 3 BIT SELECT REGISTER......................................... 133 PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER vi ...
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... REGISTERS 03DH, 0BDH, 13DH, 1BDH, 23DH, 2BDH, 33DH, 3BDH: E1 FRMR NATIONAL BIT CODEWORD......................................................................... 154 REGISTERS 03EH, 0BEH, 13EH, 1BEH, 23EH, 2BEH, 33EH, 3BEH: E1 FRMR FRAME PULSE/ALARM/V5.2 LINK ID INTERRUPT ENABLES .................... 155 PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER vii ...
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... REGISTERS 04CH, 0CCH, 14CH, 1CCH, 24CH, 2CCH, 34CH, 3CCH: RDLC #1, #2, #3 PRIMARY ADDRESS MATCH ....................................................... 179 REGISTERS 04DH, 0CDH, 14DH, 1CDH, 24DH, 2CDH, 34DH, 3CDH: RDLC #1, #2, #3 SECONDARY ADDRESS MATCH................................................. 180 PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER viii ...
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... REGISTER 060H, 0E0H, 160H, 1E0H, 260H, 2E0H ,360H, 3E0H: TPSC CONFIGURATION .......................................................................................... 203 REGISTER 061H, 0E1H, 161H, 1E1H, 261H, 2E1H ,361H, 3E1H: TPSC µP ACCESS STATUS .......................................................................................... 204 PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER ix ...
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... REGISTER 068H, 0E8H, 168H, 1E8H, 268H, 2E8H ,368H, 3E8H: FRAMING BIT ERROR COUNT ............................................................................................. 228 REGISTER 06AH, 0EAH, 16AH, 1EAH, 26AH, 2EAH ,36AH, 3EAH: FAR END BLOCK ERROR COUNT LSB ........................................................................ 229 PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER x ...
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... REGISTER 07DH, 0FDH, 17DH, 1FDH, 27DH, 2FDH ,37DH, 3FDH: PRGD PATTERN DETECTOR #2.............................................................................. 241 REGISTER 07EH, 0FEH, 17EH, 1FEH, 27EH, 2FEH ,37EH, 3FEH: PRGD PATTERN DETECTOR #3.............................................................................. 242 PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER xi ...
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... DATA SHEET PMC-1971019 REGISTER 07FH, 0FFH, 17FH, 1FFH, 27FH, 2FFH ,37FH, 3F0H: PRGD PATTERN DETECTOR #4.............................................................................. 242 REGISTER 008H: EOCTL MASTER TEST .................................................... 245 PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER xii ...
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... FIGURE 19 - BIDIRECTIONAL CELL (IO_CELL) ......................................... 253 FIGURE 20 - LAYOUT OF OUTPUT ENABLE AND BIDIRECTIONAL CELLS 254 FIGURE 21 - TYPICAL DATA FRAME .......................................................... 273 FIGURE 22 - EXAMPLE MULTI-PACKET OPERATIONAL SEQUENCE...... 274 PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER xiii ...
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... FIGURE 40 - TRANSMIT CONCENTRATION HIGHWAY INTERFACE........ 298 FIGURE 41 - SERIAL TELECOM BUS (ST-BUS), EXAMPLE 1 ................... 299 FIGURE 42 - SERIAL TELECOM BUS (ST-BUS), EXAMPLE 2 ................... 299 FIGURE 43 - NON-MULTIPLEXED RECEIVE BACKPLANE AT 2.048/4.096 MHZ 300 PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER xiv ...
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... FIGURE 57 - MULTIPLEXED INGRESS INTERFACE TIMING ................... 318 FIGURE 58 - MULTIPLEXED EGRESS INTERFACE TIMING .................... 319 FIGURE 59 - JTAG PORT INTERFACE TIMING .......................................... 320 FIGURE 60 - 128 PIN COPPER LEADFRAME PLASTIC QUAD FLAT PACK (R SUFFIX) 323 PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER xv ...
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... E1 SIGNALING INSERTION MODE........................................ 159 TABLE TIMESLOT 0 INSERTION CONTROL SUMMARY (INDIS = FDIS = 0) 161 TABLE 21 - NATIONAL BIT CODEWARD SELECTION ............................. 170 TABLE 22 - RECEIVE PACKET BYTE STATUS......................................... 176 PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER xvi ...
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... TEST MODE 0 OUTPUT SIGNAL READ ADDRESSES ......... 248 TABLE 41 - INSTRUCTION REGISTER..................................................... 250 TABLE 42 - IDENTIFICATION REGISTER ................................................. 250 TABLE 43 - BOUNDARY SCAN REGISTER .............................................. 251 TABLE 44 - PSEUDO-RANDOM PATTERN GENERATION (PS BIT = 0) .. 277 PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER xvii ...
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... PMC-1971019 TABLE 45 - REPETITIVE PATTERN GENERATION (PS BIT = 1) ............. 278 TABLE 46 - PMON COUNTER SATURATION LIMITS ............................... 286 TABLE 47 - EOCTL ABSOLUTE MAXIMUM RATINGS .............................. 302 TABLE 48 - EOCTL D.C. CHARACTERISTICS.......................................... 303 PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER xviii ...
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... Seamless interface to the PM4314 QDSX Quad Line Interface. Provides a IEEE P1149.1 (JTAG) compliant test access port (TAP) and controller for boundary scan test. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER ® ...
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... Frames to the E1 signaling multiframe alignment when enabled and extracts channel associated signaling. Alternatively, a common channel signaling data link may be extracted from timeslot 16. Can be programmed to generate an interrupt on change of signaling state. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER 2 ...
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... Provides a digital phase locked loop for generation of a low jitter transmit clock. Provides programmable idle code substitution, data inversion, signaling insertion, and A-Law or -Law digital milliwatt code insertion on a per-channel basis. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER 3 ...
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... Digital Private Branch Exchanges (PBX) E1 Channel Service Units (CSU) and Data Service Units (DSU) E1 Channel Banks and Multiplexers Digital Access and Cross-Connect Systems (DACS) PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER 4 ...
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... Digital Networks Which are Based on the 2048 kbit/s Hierarchy, 1993. 12. ITU-T Recommendation G.964, - V-Interfaces at the Digital Local Exchange (LE) - V5.1 Interface (Based on 2048kbit/s) for the Support of Access Network (AN), June 1994. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER 5 ...
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... ITU-T Recommendation O.153 - Basic Parameters for the Measurement of Error Performance at Bit Rates below the Primary Rate, October 1992 18. GO-MVIP - Multi-Vendor Integration Protocol, MVIP-90 Release 1.1, 1994. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER 6 ...
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... PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6388-RI EO CTL PM 6388 CTL PM 6388 CTL PM 4388-RI EO CTL # 6388- 6388- PM6388 EOCTL OCTAL E1 FRAMER PM7364 FREEDM(s) Channelized /Unchannelized Packet Router Core HDLC or Processor(s) Packet Sw itch Core 7 ...
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... Store SIGX ELST Signaling Alignment, RPSC Elastic Extractor Per- Store Extraction Channel Controller Performance * These signals are shared between all eight framers. PM6388 EOCTL OCTAL E1 FRAMER TOPS Timing Options TJAT TLCLK[1:8] Digital Jitter TLD[1:8] Attenuator XCLK* FRMR Framer: Frame Alarm RLCLK[1:8] ...
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... DATA SHEET PMC-1971019 6 DESCRIPTION The PM6388 Octal E1 Framer (EOCTL feature-rich device for use in systems carrying data (frame relay, Point to Point Protocol, or other protocols) or voice over E1 facilities. Each of the framers and transmitters is independently software configurable, allowing feature selection without changes to external wiring. ...
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... It should be noted that the EOCTL device operates on unipolar data only: HDB3 encoding and line code violation monitoring, if required, must be processed by the E1 LIU. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 ® , AT&T CHI and MVIP PCM standards. PM6388 EOCTL OCTAL E1 FRAMER 10 ...
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... RLD[7] RLCLK[7] RLD[8] RLCLK[8] PIN 38 PIN 39 PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Index Pin PM6388 EOCTL Top View PM6388 EOCTL OCTAL E1 FRAMER PIN 103 PIN 102 ESIG/ECLK/EFP[6] ED[7] ESIG/ECLK/EFP[7] ED[8] ESIG/ECLK/EFP[8] ID/MID[1] ICLK/ISIG/MISIG[1] IFP/MIFP[1] ID/MID[2] PLA[4] ...
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... Receive Line Clocks (RLCLK[1:8]). Each input externally recovered 2.048 MHz line clock that 6 samples the RLD[x] inputs on its active edge. 8 RLCLK[x] may be a gapped clock subject to the 32 timing constraints in the AC Timing section of this 34 datasheet PM6388 EOCTL OCTAL E1 FRAMER 12 ...
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... ID[x] data stream. ISIG[x] is updated on the active edge of the common ingress clock, CICLK Multiplexed Ingress Signaling (MISIG[1:2): When 96 the Multiplexed bus structure is enabled, MISIG[1:2] 91 carry the signaling data for the selected links. MISIG[1:2] are updated on the active edge of MCICLK. PM6388 EOCTL OCTAL E1 FRAMER 13 ...
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... MID[1:2] multiplexed data stream. The frame alignment signal for each link can behave the same as IFP[x], or either MIFP can be configured as a reference frame pulse indicating bit 1 of the Multiplexed frame. MIFP[1:2] are updated on the active edge of MCICLK. PM6388 EOCTL OCTAL E1 FRAMER 14 ...
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... ID[x], ISIG[x], and IFP[x] are updated on the active edge of CICLK. Multiplexed Common Ingress Clock (MCICLK). When configured for the Multiplexed bus structure, MCICLK drives the ingress multiplexed bus. MCICLK is a 8.192 Mhz or 16.384 MHz clock. PM6388 EOCTL OCTAL E1 FRAMER 15 ...
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... Multiplexed bus structure, MED[1:2] are the egress data streams. Data for each link must configured to originate from an 8-bit-wide slot within one of the two MED data streams. MED[1:2] are sampled on the active edge of MCECLK. PM6388 EOCTL OCTAL E1 FRAMER 16 ...
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... ED[x] stream. ED[x] is sampled on the active edge of the associated ECLK[x]. Multiplexed Bus Egress Signaling (MESIG[1:2]). 114 When the Multiplexed bus structure is enabled, 112 MESIG[1:2] carries the signaling data for the links configured the two buses. MESIG[1:2] is sampled on the active edge of MCECLK. PM6388 EOCTL OCTAL E1 FRAMER 17 ...
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... Multiplexed Common Egress Clock (MCECLK). When the Multiplexed bus structure is enabled, MCECLK is a 8.192 MHz or 16.384 Mhz clock which drives the two Multiplexed buses and samples the data on MESIG[1:2], MED[1:2], and the alignment signal on MCEFP. PM6388 EOCTL OCTAL E1 FRAMER 256) so long as CTCLK 18 ...
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... Crystal Clock Input (XCLK). This signal provides timing for many portions of the EOCTL. XCLK is nominally a 49.152 MHz ± 50ppm, 50% duty cycle clock. Vector Clock (VCLK). The VCLK signal is used during EOCTL production test to verify internal functionality. PM6388 EOCTL OCTAL E1 FRAMER 19 ...
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... Active low reset (RSTB). This signal is set low to asynchronously reset the EOCTL. RSTB is a Schmitt-trigger input with integral pull-up. When resetting the device, RSTB must be asserted for a minimum of 100 ns to ensure that the EOCTL is completely reset. PM6388 EOCTL OCTAL E1 FRAMER CSB must 20 ...
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... IEEE P1149.1 test access port. TRSTB is a Schmitt triggered input with an integral pull up resistor. The JTAG TAP controller must be initialized when the EOCTL is powered up. If the JTAG port is not used TRSTB must be connected to the RSTB input or grounded. PM6388 EOCTL OCTAL E1 FRAMER 21 ...
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... Pad ring ground pins (PLA[5:0]). These pins must 30 be connected to a common ground together with the 50 core ground pins PLD[3:0 108 21 Core ground pins (PLD[3:0]). These pins must be 52 connected to a common ground together with the pad 86 ring ground pins PLA[5:0]. 118 PM6388 EOCTL OCTAL E1 FRAMER 22 ...
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... Certain inputs are described as being sampled by the “active edge” particular clock. These inputs may be enabled to be sampled on either the rising edge or the falling edge of that clock, depending on the software configuration of the device. . PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER 23 ...
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... OOSMF, OOCMF, AIS, or RED), and to signal when any event output (RRA, RRMA, AISD, T16AISD, COFA, FER, SMFER, CMFER, CRCE, or FEBE) has occurred. As well, interrupts may be generated every frame, CRC sub-multiframe, CRC multiframe or signaling multiframe. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER 24 ...
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... CRC Frame Find Block accumulates excessive CRC evaluation errors ( 915 CRC errors in 1 second) and is enabled to force a re-frame. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 -3 bit error rate. The block declares loss of frame PM6388 EOCTL OCTAL E1 FRAMER 25 ...
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... CRC-4 multiframe alignment within the subsequent 400ms, the distant end is assumed is assumed non CRC-4 interface. The details of this algorthm are outlined in the state diagram below: PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER 26 ...
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... FAS_Find_2_Par 8m s expire FAS found next fram e BFA_Par 8m s expire and NOT(400m s expire) CRCMFA_P ar CRC to non-CRC Interworking CRCMFA_Par (Optional setting) PM6388 EOCTL OCTAL E1 FRAMER NFAS not found next fram not found next fram e Start 8m s tim er 400m s expire 27 ...
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... The basic frame alignment is set to correspond to the frame alignment found by the parallel offline search, which PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER OOF OOOF ...
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... Remote Signaling Multiframe Alarm bit (bit frame 0 of the multiframe). Using debounce, the Remote Signaling Multiframe Alarm bit has < 0.00001% probability of being falsely indicated in the presence rate. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER -3 bit error 29 ...
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... Performance Monitor Counters (PMON) The Performance Monitor Counters function is provided by the PMON block. The block accumulates CRC error events, Frame Synchronization bit error events, and PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER -3 30 ...
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... Received data is placed into a 128-byte FIFO buffer. An interrupt is generated when a programmable number of bytes are stored in the FIFO buffer. Other sources of interrupt are detection of the terminating flag sequence, abort sequence, or FIFO buffer overrun. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER 31 ...
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... Signaling Extractor (SIGX) The Signaling Extraction (SIGX) block provides signaling bit extraction from timeslot 16 of the ingress. When the external signaling interface is enabled, the SIGX PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER 32 ...
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... The counters are reset in such a way that no events are missed. The data is then available in the PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER 33 ...
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... E1 stream on a per-channel basis. It also allows per-channel control of datainversion, per-channel loopback (from the ingress stream), channel insertion, and the detection or generation of pseudo-random or repetitive patterns. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER 34 ...
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... Transmission commences regardless of whether or not a packet has been completely written into the FIFO. The user must be careful to avoid overfilling the FIFO. Underruns can only occur if the PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER 35 ...
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... If the FIFO read pointer comes within one bit of the write pointer, DJAT will track the jitter of the input clock. This permits the phase jitter to pass through unattenuated, inhibiting the loss of data. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER 36 ...
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... Hz UIpp with no frequency offset. The frequency offset is the difference between the frequency of XCLK divided by 24 and that of the input data clock. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER 37 ...
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... PLL reference clock and XCLK ÷ 24 are shown in Figure 4. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 ITU-T G.823 unacceptable Region 20 100 10 Jitter Frequency, Hz PM6388 EOCTL OCTAL E1 FRAMER DJAT m inimum tolerance acceptable 2.4k 18k 1k 10k 100k 35 0 ...
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... PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 200 0 49 G.737, G738, G.739, G.742 max response 100 10 40 Jitter Frequency, Hz PM6388 EOCTL OCTAL E1 FRAMER 42.4 39 34.9 300 308 Hz 100 ± ppm Unacceptable Region 1k 10k 39 -19.5 ...
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... When the EOCTL is the clock master in the PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 FRMR Framer: Frame Alignment, Alarm Extraction PM6388 EOCTL OCTAL E1 FRAMER RLCLK[1:8] RJAT Digital Jitter RLD[1:8] Attenuator RECEIVER 40 ...
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... PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 FRMR Framer: Frame Alignment, Alarm Extraction ELST Elastic Store FRMR Framer: Frame Alignment, Alarm Extraction PM6388 EOCTL OCTAL E1 FRAMER RLCLK[1:8] RJAT Digital Jitter RLD[1:8] Attenuator RECEIVER RLCLK[1:8] RJAT Digital Jitter RLD[1:8] Attenuator RECEIVER 41 ...
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... FRMR Framer: Frame FRMR Alignment, Framer: Alarm Frame ELST Extraction Alignment, Elastic Alarm Store Extraction Alignment, Extraction PM6388 EOCTL OCTAL E1 FRAMER RJAT Digital Jitter Attenuator RECEIVER RJAT Digital Jitter Attenuator RJAT Digital Jitter FRMR Attenuator Framer: RJAT RJAT Frame Digital Jitter ...
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... The CEFP input is unused in this mode, and has no effect. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 TRAN BasicTransmitter: Frame Generation, Alarm Insertion, Signaling Insertion, Trunk Conditioning PM6388 EOCTL OCTAL E1 FRAMER TRANSMITTER RLCLK[1:8] TJAT TLCLK[1:8] Digital PLL TLD[1:8] 43 ...
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... PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 TRAN BasicTransmitter: Frame Generation, Alarm Insertion, Signaling Insertion, Trunk Conditioning TRAN BasicTransmitter: Frame Generation, Alarm Insertion, Signaling Insertion, Trunk Conditioning PM6388 EOCTL OCTAL E1 FRAMER TRANSMITTER RLCLK[1:8] TJAT TLCLK[1:8] Digital PLL TLD[1:8] TRANSMITTER RLCLK[1:8] TJAT Digital PLL TLCLK[1:8] TJAT ...
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... BasicTransmitter: Signaling Insertion, Frame Generation, Trunk Conditioning Alarm Insertion, TRAN Signaling Insertion, BasicTransmitter: Trunk Conditioning Frame Generation, Alarm Insertion, Signaling Insertion, Trunk Conditioning PM6388 EOCTL OCTAL E1 FRAMER TRANSMITTER RLCLK[1:8] TJAT Digital PLL TLCLK[1:8] TJAT FIFO TLD[1:8] TJAT Digital PLL TJAT Digital PLL ...
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... Clock Monitor 20E 28E 30E 38E Ingress Frame Pulse 20F 28F 30F 38F Reserved 210 290 310 390 Receive Backplane PM6388 EOCTL OCTAL E1 FRAMER Register Master Test EOCTL Revision/Chip ID/Global PMON Update Reset Interrupt ID Positioning/Control Configuration Configuration 46 ...
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... RXCE Receive Data Link 1 229 2A9 329 3A9 RXCE Data Link 1 Bit Select 22A 2AA 32A 3AA RXCE Receive Data Link 2 PM6388 EOCTL OCTAL E1 FRAMER Configuration Configuration Offset Reserved Configuration Pulse Configuration Configuration and Status Offset Reserved (N1) Control ...
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... E1 FRMR National Bit Codeword 23D 2BD 33D 3BD E1 FRMR National Bit Codeword 23E 2BE 33E 3BE E1 FRMR Frame PM6388 EOCTL OCTAL E1 FRAMER Register (TXCISEL = 0) / TXCI Data Link 2 Bit Select Register (TXCISEL = 1) Control (TXCISEL = 0) / TXCI Transmit Data Link 3 Control (TXCISEL = 1) Register (TXCISEL = 0) / TXCI ...
Page 68
... RPSC Configuration 25D 2DD 35D 3DD RPSC µP Access Status 25E 2DE 35E 3DE RPSC Channel Indirect 25F 2DF 35F 3DF RPSC Channel Indirect Data PM6388 EOCTL OCTAL E1 FRAMER Interrupts Alarm/Diagnostic Control Select Match* Address Match* Threshold* Threshold * UDR Clear* Address/Control Buffer 49 ...
Page 69
... PRGD Pattern Detector #1 2FD 37D 3FD PRGD Pattern Detector #2 27E 2FE 37E 3FE PRGD Pattern Detector #3 27F 2FF 37F 3FF PRGD Pattern Detector #4 PM6388 EOCTL OCTAL E1 FRAMER Address/Control Buffer State Change Channels 25-32 Status/Signaling State Channels 17-24 Address/Control/Signaling State Change Channels 9-16 Buffer/ Signaling State Change ...
Page 70
... RDLC or TDPR block must be selected using the RDLCSEL[1:0] and TDPRSEL[1:0] register bits in the Framer Reset Register. These bits do NOT have default values and must be set to defined values before proper operation can be achieved. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER 51 ...
Page 71
... To ensure that the EOCTL operates as intended, reserved register bits must only be written with logic zero. Similarly, writing to reserved registers should be avoided. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER 52 ...
Page 72
... FAS word results in a single framing error count. When WORDERR is logic 0, each error in a FAS word results in a single framing error count. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default FIFOBYP 0 UNF 0 WORDERR 0 CNTNFAS 0 AUTOYELLOW 0 AUTORED 0 AUTOOOF 0 AUTOUPDATE 0 PM6388 EOCTL OCTAL E1 FRAMER 53 ...
Page 73
... If the INTE bit is set in the PMON Interrupt/Enable register, then the PMON will interrupt the PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER 54 ...
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... PRGD may be initiated by the microprocessor via the Revision/Chip ID/Global PMON Update register, and care must be taken to avoid initiating an update while another update is in progress. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER 55 ...
Page 75
... RLCLK[x]. When ICLKSEL is a logic 0, ICLK[ kHz timing PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default RLCLKFALL 0 ISIG_EN 1 ICLKSEL 0 MIBUS2 0 MIBUS_OUTEN 0 OOSMFAIS 0 TRKEN 0 RXMTKC 0 Mode Clock Slave: ICLK Reference Clock Slave: External Signaling/Multiplexed backplane PM6388 EOCTL OCTAL E1 FRAMER 56 ...
Page 76
... RPSC Data Trunk Conditioning and Signaling Trunk Conditioning registers. This bit affects the corresponding timeslot of the MID[x] data stream in the same manner if the multiplexed backplane is enabled. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER 57 ...
Page 77
... RPSC. This bit affects the corresponding timeslot of the MID[x] data stream in the same manner if the multiplexed backplane is enabled. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER 58 ...
Page 78
... When PATHCRC is set to logic 0, a new CRC-4 value overwrites the incoming CRC-4 word. For the PATHCRC bit to be effective, the CRC PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default FIFOBYP 0 TAISEN 0 Unused X PATHCRC 0 Unused X EFPRISE 0 Unused X TLCLKRISE 0 PM6388 EOCTL OCTAL E1 FRAMER 59 ...
Page 79
... The TLCLKRISE bit enables the transmit line interface to be updated on the rising TLCLK[x] edge. When TLCLKRISE is set to logic 1, TLD[x] is updated on the rising TLCLK[x] edge. When TLCLKRISE is set to logic 0, TLD[x] is updated on the falling TLCLK[x] edge. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER 60 ...
Page 80
... CRC PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default Unused X ESIG_EN 1 Unused X MEBUS2 0 Unused X Unused X Unused X ESFP 0 Mode Clock Slave: EFP Enabled Clock Slave: External Signaling PM6388 EOCTL OCTAL E1 FRAMER 61 ...
Page 81
... DATA SHEET PMC-1971019 multiframe. When ESFP is set to logic 0, the EFP[x] output pulses high during each framing bit (i.e. every 256 bits). PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER 62 ...
Page 82
... The PLLREF[1:0] bits select the source of the Transmit Digital Jitter Attenuator phase locked loop reference signal as follows: PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default HSBPSEL 0 Unused X Unused X OCLKSEL 0 PLLREF1 0 PLLREF0 1 CTCLKSEL 0 SMCLKO 0 PM6388 EOCTL OCTAL E1 FRAMER 63 ...
Page 83
... Transmit Line Clock Options ECLKSLV =1 When PLLREF[1:0]=0X, TLCLK[ ESIG_EN =1 jitter-attenuated clock referenced to HSBPSEL =0 CECLK. This is the default. OCLKSEL =0 CTCLKSEL =0 When PLLREF[1:0]=10, TLCLK[ SMCLKO =0 jitter-attenuated clock referenced to RLCLK[x] When PLLREF[1:0]=11, TLCLK[ jitter-attenuated clock referenced to CTCLK[x] PM6388 EOCTL OCTAL E1 FRAMER 64 ...
Page 84
... When PLLREF[1:0]=11, TLCLK[ jitter-attenuated clock referenced to CTCLK ECLKSLV =1 When PLLREF[1:0]=0X, TLCLK[ HSBPSEL =1 jitter-attenuated clock referenced to OCLKSEL =0 CECLK. See note 2. CTCLKSEL =0 SMCLKO =0 When PLLREF[1:0]=10, TLCLK[ jitter-attenuated clock referenced to RLCLK[x] When PLLREF[1:0]=11, TLCLK[ jitter-attenuated clock referenced to CTCLK PM6388 EOCTL OCTAL E1 FRAMER 65 ...
Page 85
... RLCLK[x] (See Note 3) When PLLREF[1:0]=11, TLCLK[ jitter-attenuated clock referenced to CTCLK ECLKSLV =0 When OCLKSEL = 1, TLCLK[x] = CTCLK. HSBPSEL =0 FIFOBYP =0 When OCLKSEL = 0, SMCLKO = 1, and CECLK2M =0 CTCLKSEL =0, then TLCLK[x] = PLLREF[1:0] =XX CTCLK÷8. When OCLKSEL = 0, SMCLKO = 1, and CTCLKSEL =1, then TLCLK[x] = XCLK÷24. PM6388 EOCTL OCTAL E1 FRAMER 66 ...
Page 86
... Clock Slave mode, while the Clock Master Mode PLL is referenced to RLCLK[x], CEFP should be removed after the framers in Clock Slave Mode are aligned. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER 67 ...
Page 87
... Smooth 2.048MHz 00 TJAT 01 PLL 10 24X reference clock for jitter attenuation CTCLKSEL 0 1 HSBPSEL PM6388 EOCTL OCTAL E1 FRAMER 1 TLCLK[x] 0 FIFOBY P OCLKSEL "Jitter-free" 1 SMCLKO 2.048MHz "High-speed" clock f or FRMR (=16.384MHz) "High-speed" clock for ELST, SIGX, TPSC & RPSC ( 6x ...
Page 88
... Reading this register does not remove the interrupt indication; the corresponding block’s interrupt status register must be read to remove the interrupt indication. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default PMON X TRAN X FRMR X PRGD X ELST X RDLC#1 X RDLC#2 X RDLC#3 X PM6388 EOCTL OCTAL E1 FRAMER 69 ...
Page 89
... Reading these registers does not remove the interrupt indication; the corresponding block’s interrupt status register must be read to remove the interrupt indication. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default BTIF X Unused X TJAT X RJAT X TDPR#1 X TDPR#2 X TDPR#3 X SIGX X PM6388 EOCTL OCTAL E1 FRAMER 70 ...
Page 90
... When a logic 1, the RAIS bit forces all ones into the ID[x] data stream. The ISIG[x] data stream will freeze at the current valid signaling. This capability is PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default Unused X Unused X Unused X LINELB 0 V52DIS 0 DDLB 0 RAIS 0 TXDIS 0 PM6388 EOCTL OCTAL E1 FRAMER 71 ...
Page 91
... The TXDIS bit provides a method of suppressing the output of the basic transmitter. When TXDIS is set to logic 1, the TRAN output is disabled by forcing it to logic 0. When TXDIS is set to logic 0, the TRAN output is not suppressed. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER 72 ...
Page 92
... The PMCTST bit is logically “ORed” with the IOTST bit, and is cleared by setting CSB to logic 1. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default A_TM[9] X A_TM[8] X A_TM[7] X PMCTST X DBCTRL 0 IOTST 0 HIZDATA 0 HIZIO 0 PM6388 EOCTL OCTAL E1 FRAMER 73 ...
Page 93
... The microprocessor interface is still active. While the HIZDATA bit is a logic 1, the data bus is also held in a high- impedance state which inhibits microprocessor read cycles. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER 74 ...
Page 94
... The chip identification bits, TYPE[2:0], are set to binary 011 representing the EOCTL. Writing to this register causes all performance monitor and pattern generator/detector counters to be updated simultaneously. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default TYPE[2] 0 TYPE[1] 1 TYPE[0] 1 ID[4] 0 ID[3] 0 ID[2] 0 ID[1] 1 ID[0] 1 PM6388 EOCTL OCTAL E1 FRAMER 75 ...
Page 95
... Receive Datalink Controller Selection RDLCSEL[1: PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default RDLCSEL[1] X RDLCSEL[0] X TDPRSEL[1] X TDPRSEL[0] X TXCISEL X Unused X Unused X RESET 0 Rx HDLC Controller selected RDLC #1 RDLC #2 RDLC #3 Reserved PM6388 EOCTL OCTAL E1 FRAMER 76 ...
Page 96
... A hardware reset clears the RESET bit, thus deasserting the software reset. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Tx HDLC Controller selected TDPR #1 TDPR #2 TDPR #3 Reserved PM6388 EOCTL OCTAL E1 FRAMER 77 ...
Page 97
... The INTx bit will be high if the xth E1 framer (the E1 framer corresponding to the input pin RLCLK[x]) causes the INTB pin to transition low. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default INT8 X INT7 X INT6 X INT5 X INT4 X INT3 0 INT2 0 INT1 0 PM6388 EOCTL OCTAL E1 FRAMER 78 ...
Page 98
... The UNF_GEN bit overrides any per-timeslot pattern generation specified in the TPSC or RPSC. When RXPATGEN = 0, then PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default Unused X Unused X Unused X Unused X Unused X RXPATGEN 0 UNF_GEN 0 UNF_DET 0 PM6388 EOCTL OCTAL E1 FRAMER 79 ...
Page 99
... PRGD will search for the pattern in all 256 bits of the egress or receive stream, depending on the setting of RXPATGEN. The UNF_DET bit overrides any per-timeslot pattern detection specified in the TPSC or RPSC. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER 80 ...
Page 100
... CICLKA is set high on a rising edge of CICLK, and is set low when this register is read. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default Unused X Unused X Unused X XCLKA X CECLKA X CTCLKA X CICLKA X RLCLKA X PM6388 EOCTL OCTAL E1 FRAMER 81 ...
Page 101
... The CECLK active bit monitors for low to high transitions on the CECLK input. CECLKA is set high on a rising edge of CECLK, and is set low when this register is read. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER 82 ...
Page 102
... PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default Unused X Unused X Unused X Unused X PERTS_IFP 0 REF_MIFP 0 OOCMFE0 0 G706RAI 0 REF_MIFP Description 0 IFP[x] is forced logic 0. When the multiplexed backplane is enabled, the octant will not make a contribution to MIFP[1:2]. 0 IFP[x] is output as configured by the ROHM, BRXSMFP and BRXCMFP PM6388 EOCTL OCTAL E1 FRAMER 83 ...
Page 103
... ISSUE 6 bits. When configured for multiplexed backplane, the frame pulse/overhead indication is contributed to MIFP along with the octant’s MID and MISIG contribution. 1 IFP[x]/MIFP contains a reference frame pulse aligned with the Ingress backplane frame pulse as indicated on CIFP. PM6388 EOCTL OCTAL E1 FRAMER 84 ...
Page 104
... PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default NxTS[1] 0 NxTS[0] 0 ICLKSLV CMS 0 RATE[1] 0 RATE[0] 0 NxTS[0] Operation 0 Full E1 1 Reserved 0 64 kbit/s NxTS 1 64 kbit/s NxTS with F-bit PM6388 EOCTL OCTAL E1 FRAMER 85 ...
Page 105
... The rate select (RATE[1:0]) bits determine the backplane rate according to the following table: Table 7 - Rate[1:0] Backplane Receive Operation RATE[1] RATE[ PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Backplane Rate 1.544 Mbit/s G.802 DS1 from E1 mapping 2.048 Mbit/s PM6388 EOCTL OCTAL E1 FRAMER 86 ...
Page 106
... The multiplexed ingress backplane bus is enabled when any of the 8 octants has its RATE[1:0] bits set to binary ‘b11. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Backplane Rate Reserved 8.192 Mbit/s PM6388 EOCTL OCTAL E1 FRAMER 87 ...
Page 107
... NFAS frames. If the BRXCMFP or BRXSMFP bit is logic 1 when ALTIFP is logic 1, the output signal on IFP[x] pulses every 32 frames. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default Reserved 0 FPINV 0 FPMODE 1 Reserved 0 ROHM 0 BRXSMFP 0 BRXCMFP 0 ALTIFP 0 PM6388 EOCTL OCTAL E1 FRAMER 88 ...
Page 108
... CRC multiframing is disabled, the IFP[x] output continues to indicate the position of bit 1 of the FAS frame every 16 The CRC Multiframe pulse is not valid when timeslot and bit offsets are configured to indicate the last bit of the frame. PM6388 EOCTL OCTAL E1 FRAMER th frame). 89 ...
Page 109
... IFP[x] signal. Note that if the signaling and CRC multiframe alignments are coincident, IFP[x] will pulse high for 1 CICLK or ICLK[x] cycle every 16 frames. The Composite Multiframe pulse is not valid when timeslot and bit offsets are configured to indicate the last bit of the frame. PM6388 EOCTL OCTAL E1 FRAMER frame.) 90 ...
Page 110
... PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 BRXCMFP IFP[x] Configuration X Backplane receive overhead output: IFP[x] is high for timeslot 0 and timeslot 16 of each 256-bit frame, indicating the overhead of the ID[x] data stream. ROHM is not valid when timeslot or bit offsets are used. PM6388 EOCTL OCTAL E1 FRAMER 91 ...
Page 111
... If RPRTYE is a logic 1, FIXF has no effect. If RPRTYE and FIXF are both logic 0, the first bit of the frame passes from the line transparently. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default RPTYP 0 RPTYE 0 FIXF 0 FIXPOL 0 PTY_EXTD 0 Unused X TRI[1] 0 TRI[0] 0 PM6388 EOCTL OCTAL E1 FRAMER 92 ...
Page 112
... Totem-pole operation. ID[x] and ISIG[x] drive during the bit periods that contain valid data, i.e. every second or fourth byte for multiplexed operation Reserved 1 1 Reserved PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER 93 ...
Page 113
... Mbit/s, every byte on ID[x] and ISIG[x] is driven. With a data rate of 8.192 Mbit/s, each octant contributes every fourth byte on MID[1:2] and MISIG[1:2]. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default Unused X TSOFF[6] 0 TSOFF[5] 0 TSOFF[4] 0 TSOFF[3] 0 TSOFF[2] 0 TSOFF[1] 0 TSOFF[0] 0 PM6388 EOCTL OCTAL E1 FRAMER 94 ...
Page 114
... ISIG[x] is sampled on the fourth clock edge after CIFP is sampled (see Figure 45). The following tables show the relationship between BOFF[2:0], FE, DE and CER. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default Unused X Unused X Unused X Unused X BOFF_EN 0 BOFF[2] 0 BOFF[1] 0 BOFF[0] 0 PM6388 EOCTL OCTAL E1 FRAMER 95 ...
Page 115
... BOFF[2:0] 010 011 100 101 PM6388 EOCTL OCTAL E1 FRAMER 101 110 111 CET 110 111 000 TSOFF+ ...
Page 116
... PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default NxTS[1] 0 NxTS[0] 0 ECLKSLV CMS 0 RATE[1] 0 RATE[0] 0 NxTS[0] Operation 0 Full E1 1 Reserved 0 64 kbit/s NxTS 1 64 kbit/s NxTS with F-bit PM6388 EOCTL OCTAL E1 FRAMER 97 ...
Page 117
... If CMS is a logic 0, CECLK is at the backplane rate. If CMS is a logic 1, CECLK is at twice the backplane rate. RATE[1:0]: The rate select (RATE[1:0]) bits determine the backplane rate according to the following table: PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER 98 ...
Page 118
... RATE[1:0] bits set to binary ‘b11. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Backplane Rate 1.544 Mbit/s G.802 DS1 to E1 mapping 2.048 Mbit/s Reserved 8.192 Mbit/s PM6388 EOCTL OCTAL E1 FRAMER 99 ...
Page 119
... CRC multiframe. Reserved: This register bit must be set to logic 1 for proper operation. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default Reserved 0 Unused X Unused X Unused X FPINV 0 Reserved 0 FPTYP 0 Reserved 1 PM6388 EOCTL OCTAL E1 FRAMER 100 ...
Page 120
... The transmit data interrupt (TDI) bit indicates if a parity error has been detected on the ED[x] input. This bit is cleared when this register is read. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default TPTYP 0 TPTYE 0 TDI X Reserved X PTY_EXTD 0 Unused X Unused X Unused X PM6388 EOCTL OCTAL E1 FRAMER 101 ...
Page 121
... The parity extend (PRY_EXTD) bit causes the parity to be calculated over the previous frame plus the previous parity bit, instead of only the previous frame. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER 102 ...
Page 122
... When in the Clock Slave EFP Enabled mode, the TSOFF[6:0] bits must all be set to logic 0 for proper operation. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default Unused X TSOFF[6] 0 TSOFF[5] 0 TSOFF[4] 0 TSOFF[3] 0 TSOFF[2] 0 TSOFF[1] 0 TSOFF[0] 0 PM6388 EOCTL OCTAL E1 FRAMER 103 ...
Page 123
... ESIG[x] is sampled on the fourth clock edge after CEFP is sampled (see Figure 40). The following tables show the relationship between BOFF[2:0], FE, DE and CER. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default Unused X Unused X Unused X Unused X BOFF_EN 0 BOFF[2] 0 BOFF[1] 0 BOFF[0] 0 PM6388 EOCTL OCTAL E1 FRAMER 104 ...
Page 124
... BOFF[2:0] 001 010 011 100 PM6388 EOCTL OCTAL E1 FRAMER 101 110 111 CER 101 110 111 CER ...
Page 125
... FIFO when the FIFO is already empty. When UNDI is a logic 1, an underrun event has occurred. The UNDI bit is cleared after this register is read. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default Unused X Unused X Unused X Unused X Unused X Unused X OVRI X UNDI X PM6388 EOCTL OCTAL E1 FRAMER 106 ...
Page 126
... Upon reset of the EOCTL, the default value set to decimal 47 (2FH). Consult the Operations section for clarification of divisor selection criteria. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default N1[7] 0 N1[6] 0 N1[5] 1 N1[4] 0 N1[3] 1 N1[2] 1 N1[1] 1 N1[0] 1 PM6388 EOCTL OCTAL E1 FRAMER 107 ...
Page 127
... Upon reset of the EOCTL, the default value set to decimal 47 (2FH). Consult the Operations section for clarification of divisor selection criteria. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default N2[7] 0 N2[6] 0 N2[5] 1 N2[4] 0 N2[3] 1 N2[2] 1 N2[1] 1 N2[0] 1 PM6388 EOCTL OCTAL E1 FRAMER 108 ...
Page 128
... INTB pin. When OVRE or UNDE is set to logic 0, the FIFO error events are disabled from generating an interrupt. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default Unused X Unused X Reserved 1 CENT 0 UNDE 0 OVRE 0 SYNC 1 LIMIT 1 PM6388 EOCTL OCTAL E1 FRAMER 109 ...
Page 129
... This limiting of jitter ensures that no data is lost during high phase shift conditions. When LIMIT is set to logic 1, the PLL jitter attenuation is limited. When LIMIT is set to logic 0, the PLL is allowed to operate normally. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER 110 ...
Page 130
... FIFO when the FIFO is already empty. When UNDI is a logic 1, an underrun event has occurred. The UNDI bit is cleared after this register is read. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default Unused X Unused X Unused X Unused X Unused X Unused X OVRI X UNDI X PM6388 EOCTL OCTAL E1 FRAMER 111 ...
Page 131
... Upon reset of the EOCTL, the default value set to decimal 47 (2FH). Consult the Operations section for clarification of divisor selection criteria. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default N1[7] 0 N1[6] 0 N1[5] 1 N1[4] 0 N1[3] 1 N1[2] 1 N1[1] 1 N1[0] 1 PM6388 EOCTL OCTAL E1 FRAMER 112 ...
Page 132
... Upon reset of the EOCTL, the default value set to decimal 47 (2FH). Consult the Operations section for clarification of divisor selection criteria. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default N2[7] 0 N2[6] 0 N2[5] 1 N2[4] 0 N2[3] 1 N2[2] 1 N2[1] 1 N2[0] 1 PM6388 EOCTL OCTAL E1 FRAMER 113 ...
Page 133
... INTB pin. When OVRE or UNDE is set to logic 0, the FIFO error events are disabled from generating an interrupt. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default Unused X Unused X Reserved 1 CENT 0 UNDE 0 OVRE 0 SYNC 1 LIMIT 1 PM6388 EOCTL OCTAL E1 FRAMER 114 ...
Page 134
... This limiting of jitter ensures that no data is lost during high phase shift conditions. When LIMIT is set to logic 1, the PLL jitter attenuation is limited. When LIMIT is set to logic 0, the PLL is allowed to operate normally. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER 115 ...
Page 135
... When these conditions are met and TS16_EN is logic 1, timeslot 16 data will be automatically extracted on RDLC#1. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default DL1_EVEN 0 DL1_ODD 0 TS16_EN 1 DL1_TS[4] 0 DL1_TS[3] 0 DL1_TS[2] 0 DL1_TS[1] 0 DL1_TS[0] 0 PM6388 EOCTL OCTAL E1 FRAMER 116 ...
Page 136
... The data link 1 timeslot (DL1_TS[4:0]) bits give a binary representation of the timeslot from which the datalink extracted for RDLC#1. These bits have no effect when DL1_EVEN and DL1_ODD are both logic 0. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER 117 ...
Page 137
... MSB and DL1_BIT[0] corresponds to the LSB of the timeslot. These bits have no effect when DL1_EVEN and DL1_ODD are both logic 0. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default DL1_BIT[7] 0 DL1_BIT[6] 0 DL1_BIT[5] 0 DL1_BIT[4] 0 DL1_BIT[3] 0 DL1_BIT[2] 0 DL1_BIT[1] 0 DL1_BIT[0] 0 PM6388 EOCTL OCTAL E1 FRAMER 118 ...
Page 138
... RDLC#2. These bits have no effect when DL2_EVEN and DL2_ODD are both logic 0. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default DL2_EVEN 0 DL2_ODD 0 Unused X DL2_TS[4] 0 DL2_TS[3] 0 DL2_TS[2] 0 DL2_TS[1] 0 DL2_TS[0] 0 PM6388 EOCTL OCTAL E1 FRAMER 119 ...
Page 139
... MSB and DL2_BIT[0] corresponds to the LSB of the timeslot. These bits have no effect when DL2_EVEN and DL2_ODD are both logic 0. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default DL2_BIT[7] 0 DL2_BIT[6] 0 DL2_BIT[5] 0 DL2_BIT[4] 0 DL2_BIT[3] 0 DL2_BIT[2] 0 DL2_BIT[1] 0 DL2_BIT[0] 0 PM6388 EOCTL OCTAL E1 FRAMER 120 ...
Page 140
... RDLC#3. These bits have no effect when DL3_EVEN and DL3_ODD are both logic 0. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default DL3_EVEN 0 DL3_ODD 0 Unused X DL3_TS[4] 0 DL3_TS[3] 0 DL3_TS[2] 0 DL3_TS[1] 0 DL3_TS[0] 0 PM6388 EOCTL OCTAL E1 FRAMER 121 ...
Page 141
... MSB and DL3_BIT[0] corresponds to the LSB of the timeslot. These bits have no effect when DL3_EVEN and DL3_ODD are both logic 0. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default DL3_BIT[7] 0 DL3_BIT[6] 0 DL3_BIT[5] 0 DL3_BIT[4] 0 DL3_BIT[3] 0 DL3_BIT[2] 0 DL3_BIT[1] 0 DL3_BIT[0] 0 PM6388 EOCTL OCTAL E1 FRAMER 122 ...
Page 142
... The TS16_EN bit allows timeslot 16 data stream to be routed from TDPR#1. DL1_EVEN and DL1_ODD must each be set to logic 0 for this bit to have PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default DL1_EVEN 0 DL1_ODD 0 TS16_EN 0 DL1_TS[4] 0 DL1_TS[3] 0 DL1_TS[2] 0 DL1_TS[1] 0 DL1_TS[0] 0 PM6388 EOCTL OCTAL E1 FRAMER 123 ...
Page 143
... The data link 1 timeslot (DL1_TS[4:0]) bits give a binary representation of the timeslot into which the TDPR#1 inserts the data link. These bits have no effect when DL1_EVEN and DL1_ODD are both a logic 0. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER 124 ...
Page 144
... MSB and DL1_BIT[0] corresponds to the LSB of the timeslot. These bits have no effect when DL1_EVEN and DL1_ODD are both logic 0. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default DL1_BIT[7] 0 DL1_BIT[6] 0 DL1_BIT[5] 0 DL1_BIT[4] 0 DL1_BIT[3] 0 DL1_BIT[2] 0 DL1_BIT[1] 0 DL1_BIT[0] 0 PM6388 EOCTL OCTAL E1 FRAMER 125 ...
Page 145
... Even/odd frames are set by the CRC multiframe alignment. The National Bits are contained in the odd frames. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default DL2_EVEN 0 DL2_ODD 0 Unused X DL2_TS[4] 0 DL2_TS[3] 0 DL2_TS[2] 0 DL2_TS[1] 0 DL2_TS[0] 0 PM6388 EOCTL OCTAL E1 FRAMER 126 ...
Page 146
... The data link 2 timeslot (DL2_TS[4:0]) bits give a binary representation of the timeslot into which the TDPR#2 inserts the data link. These bits have no effect when DL2_EVEN and DL2_ODD are both a logic 0. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER 127 ...
Page 147
... To insert the data link into the entire timeslot, all eight bits must be set to a logic 1. DL2_BIT[7] corresponds to PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default DL2_BIT[7] 0 DL2_BIT[6] 0 DL2_BIT[5] 0 DL2_BIT[4] 0 DL2_BIT[3] 0 DL2_BIT[2] 0 DL2_BIT[1] 0 DL2_BIT[0] 0 PM6388 EOCTL OCTAL E1 FRAMER 128 ...
Page 148
... DATA SHEET PMC-1971019 the MSB and DL2_BIT[0] corresponds to the LSB of the timeslot. These bits PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER 129 ...
Page 149
... DATA SHEET PMC-1971019 PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER 130 ...
Page 150
... Even/odd frames are set by the CRC multiframe alignment. The National Bits are contained in the odd frames. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default DL3_EVEN 0 DL3_ODD 0 Unused X DL3_TS[4] 0 DL3_TS[3] 0 DL3_TS[2] 0 DL3_TS[1] 0 DL3_TS[0] 0 PM6388 EOCTL OCTAL E1 FRAMER 131 ...
Page 151
... The data link 3 timeslot (DL3_TS[4:0]) bits give a binary representation of the timeslot into which the TDPR#3 inserts the data link. These bits have no effect when DL3_EVEN and DL3_ODD are both a logic 0. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER 132 ...
Page 152
... MSB and DL3_BIT[0] corresponds to the LSB of the timeslot. These bits have no effect when DL3_EVEN and DL3_ODD are both logic 0. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default DL3_BIT[7] 0 DL3_BIT[6] 0 DL3_BIT[5] 0 DL3_BIT[4] 0 DL3_BIT[3] 0 DL3_BIT[2] 0 DL3_BIT[1] 0 DL3_BIT[0] 0 PM6388 EOCTL OCTAL E1 FRAMER 133 ...
Page 153
... E1-FRMR will cease searching for CRC multiframe alignment in CRC to non-CRC interworking mode. If this bit is a logic one, the E1-FRMR PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default CRCEN 1 CASDIS 0 C2NCIWCK 0 Unused X Unused X REFR 0 REFCRCE 1 REFRDIS 0 PM6388 EOCTL OCTAL E1 FRAMER 134 ...
Page 154
... CRC errors, etc.). Note that while the FRMR remains locked in frame due to REFRDIS=1, a received AIS will not be detected since the FRMR must be out-of-frame to detect AIS. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER 135 ...
Page 155
... TS16C bit position enables declaration of loss of PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default Unused X BIT2C 1 SMFASC 0 TS16C 0 RAIC 0 Unused X AISC X EXCRCERR X PM6388 EOCTL OCTAL E1 FRAMER 136 ...
Page 156
... REFCRCE bit of the Frame Alignment Options register. The EXCRCERR bit is reset to logic 0 after the register is read. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER 137 ...
Page 157
... A logic one in the CMFERE bit enables the generation of an interrupt when an error has been detected in the CRC multiframe alignment signal. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default C2NCIWE 0 OOFE 0 OOSMFE 0 OOCMFE 0 COFAE 0 FERE 0 SMFERE 1 CMFERE 0 PM6388 EOCTL OCTAL E1 FRAMER 138 ...
Page 158
... When the CRCEE bit is a logic one, an interrupt is generated when calculated CRC differs from the received CRC remainder. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default RAIE 0 RMAIE 0 AISDE 0 Reserved 0 REDE 0 AISE 0 FEBEE 0 CRCEE 0 PM6388 EOCTL OCTAL E1 FRAMER 139 ...
Page 159
... Framing Status outputs. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default C2NCIWI X OOFI X OOSMFI X OOCMFI X COFAI X FERI X SMFERI X CMFERI X PM6388 EOCTL OCTAL E1 FRAMER 140 ...
Page 160
... Maintenance/Alarm Status events. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default RAII X RMAII X AISDI X Reserved X REDI X AISI X FEBEI X CRCEI X PM6388 EOCTL OCTAL E1 FRAMER 141 ...
Page 161
... OOOFV is asserted when the offline framer in the CRC multiframe find procedure is searching for frame alignment. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default C2NCIWV X OOFV X OOSMFV X OOCMFV X OOOFV X RAICCRCV X CFEBEV X V52LINKV X PM6388 EOCTL OCTAL E1 FRAMER 142 ...
Page 162
... This bit indicates the current state of the V5.2 link (V52LINK) identification signal indicator. V52LINKV will be asserted if 2 out of 3 Sa7 bits are received as a logic 0. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER 143 ...
Page 163
... In the second mode, AISD is asserted when two consecutive 512 bit periods have been received with 2 or less zeros. The indication is cleared when 2 PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default RAIV X RMAIV X AISD X Reserved X RED X AIS X Unused X Unused X PM6388 EOCTL OCTAL E1 FRAMER 144 ...
Page 164
... The AIS bit is a logic one when an out of frame all-ones condition has persisted for 100 ms. The AIS bit returns to a logic zero when the AIS condition has been absent for 100 ms. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER 145 ...
Page 165
... This bit is updated upon generation of the IFPI interrupt on NFAS frames. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default Si[1] X Si[ Sa[4] X Sa[5] X Sa[6] X Sa[7] X Sa[ Sa[4] Sa[5] PM6388 EOCTL OCTAL E1 FRAMER Sa[6] Sa[7] Sa[8] 146 ...
Page 166
... Reading these bits returns the National bit values in the last received NFAS frame. This bit is updated upon generation of the IFPI interrupt on NFAS frames. Table 16 - TS0 NFAS Bits 1 2 Si0 1 PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE Sa[4] Sa[5] PM6388 EOCTL OCTAL E1 FRAMER Sa[6] Sa[7] Sa[8] 147 ...
Page 167
... The CRCERR register bits contain the least significant byte of the 10-bit CRC error counter value, which is updated every second. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default CRCERR[7] X CRCERR[6] X CRCERR[5] X CRCERR[4] X CRCERR[3] X CRCERR[2] X CRCERR[1] X CRCERR[0] X PM6388 EOCTL OCTAL E1 FRAMER 148 ...
Page 168
... Note that the contents of this register are not updated while the E1- FRMR is out of frame. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default OVR 0 NEWDATA 0 X[ X[1] X X[2] X CRCERR[9] X CRCERR[8] X PM6388 EOCTL OCTAL E1 FRAMER 149 ...
Page 169
... The CRCERR register bits contain the two most significant bits of the 10-bit CRC error counter value, which is updated every second. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE X[0] PM6388 EOCTL OCTAL E1 FRAMER X[1] X[2] 150 ...
Page 170
... PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default SaSEL[2] 0 SaSEL[1] 0 SaSEL[0] 0 Sa4E 0 Sa5E 0 Sa6E 0 Sa7E 0 Sa8E 0 National Bit Codeword 001 Undefined 010 Undefined 011 Undefined 100 Sa4 101 Sa5 110 Sa6 111 Sa7 000 Sa8 PM6388 EOCTL OCTAL E1 FRAMER 151 ...
Page 171
... International Bits/National Interrupt Status register will result in the assertion low of the INTB output. The interrupt enable should be logic 0 for any bit receiving a HDLC datalink. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER 152 ...
Page 172
... Interrupt Enable register is a logic 1, a logic 1 in the SaXI results in the assertion of the INTB output. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default Unused X Unused X Unused X Sa4I X Sa5I X Sa6I X Sa7I X Sa8I X PM6388 EOCTL OCTAL E1 FRAMER 153 ...
Page 173
... A change in these bit values sets the SaI[X] bit of the International Bits/National Interrupt Status register.. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default Unused X Unused X Unused X Unused X SaX[1] X SaX[2] X SaX[3] X SaX[4] X PM6388 EOCTL OCTAL E1 FRAMER 154 ...
Page 174
... If IFPE is a logic 1, a logic 1 in the IFPI bit of the Frame Pulse Interrupts register will result in the assertion low of the INTB output. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default OOOFE 0 RAICCRCE 0 CFEBEE 0 V52LINKE 0 IFPE 0 ICSMFPE 0 ICMFPE 0 ISMFPE 0 PM6388 EOCTL OCTAL E1 FRAMER 155 ...
Page 175
... If ISMFPE is a logic 1, a logic 1 in the ISMFPI bit of the Frame Pulse Interrupts register will result in the assertion low of the INTB output. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER 156 ...
Page 176
... The input frame pulse interrupt status bit is asserted at bit position 1 of the frame in the incoming data stream. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default OOOFI X RAICCRCI X CFEBEI X V52LINKI X IFPI X ICSMFPI X ICMFPI X ISMFPI X PM6388 EOCTL OCTAL E1 FRAMER 157 ...
Page 177
... The input signaling multiframe alignment frame pulse interrupt status bit is asserted at bit position 1 of frame 0 of the signaling multiframe in the incoming data stream. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER 158 ...
Page 178
... CAS enabled. TS16 data is taken from either ESIG[x] stream or from the TPSC Signaling/PCM Control byte as selected on a per-timeslot basis via the SIGSRC bit. The format of the ESIG[x] input data stream is shown in the “Functional Timing” section. PM6388 EOCTL OCTAL E1 FRAMER 159 ...
Page 179
... The INDIS bit controls the insertion of the International and National Bits into TS0 only valid if FDIS is a logic 0. When INDIS is a logic 1, the contents of the E1-TRAN International Bit PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER 160 ...
Page 180
... International bit in the NFAS frames, with the Si[1:0] bits in the International Bits Control Register used for the spare bits. The contents of the National Bit Codeword Registers are used for the National bits in NFAS frames. PM6388 EOCTL OCTAL E1 FRAMER 161 ...
Page 181
... DATA SHEET PMC-1971019 When XDIS is a logic 1, the contents of the register are ignored and the X[0], X[1], and X[2] bits are taken directly from the ED[x] stream. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER 162 ...
Page 182
... The SPATINV bit is a diagnostic control bit. When set to logic 1, SPATINV forces the signaling multiframe alignment signal written into bits 1-4 of TS16 PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default MTRK 0 FPATINV 0 SPLRINV 0 SPATINV 0 REMAIS 0 MFAIS 0 TS16AIS 0 AIS 0 PM6388 EOCTL OCTAL E1 FRAMER 163 ...
Page 183
... The AIS bit controls the transmission of the Alarm Indication Signal (unframed all-ones). A logic 1 in the AIS bit position forces the output streams to logic 1. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER 164 ...
Page 184
... The Si[1] and Si[0] bits should be programmed to a logic 1 when not being used to carry information. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default Si[1] 1 Si[0] 1 Unused X Unused X Unused X Unused X Unused X Unused X PM6388 EOCTL OCTAL E1 FRAMER 165 ...
Page 185
... XDIS. The X[0], X[1], and X[2] bits should be programmed to a logic 1 when not being used to carry information. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default Unused X Unused X Unused X Unused X X[0] 1 Unused X X[1] 1 X[2] 1 PM6388 EOCTL OCTAL E1 FRAMER 166 ...
Page 186
... INTB. When SIGMFE is set to logic 0, the SIGMFI interrupt bit will not cause INTB to be asserted. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default Unused X Unused X Unused X SIGMFE 0 FASE 0 MFE 0 SMFE 0 FRME 0 PM6388 EOCTL OCTAL E1 FRAMER 167 ...
Page 187
... The contents of this register are cleared to logic 0 after the register is read. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default Unused X Unused X Unused X SIGMFI X FASI X MFI X SMFI X FRMI X PM6388 EOCTL OCTAL E1 FRAMER 168 ...
Page 188
... SaX[1:4] bits of the National Bit Codeword register. These bits map to the codeword selection as follows: PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default SaSEL[2] 0 SaSEL[1] 0 SaSEL[0] 0 Unused X Unused X Unused X Unused X Unused X PM6388 EOCTL OCTAL E1 FRAMER 169 ...
Page 189
... National Bit Codeward Selection SaSEL[2:0] PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 National Bit Codeword 000 Undefined 001 Undefined 010 Undefined 011 Sa4 100 Sa5 101 Sa6 110 Sa7 111 Sa8 PM6388 EOCTL OCTAL E1 FRAMER 170 ...
Page 190
... If the code word is written during SMF multiframe, its contents will be latched internally and will appear in SMF I of the next multiframe. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default SaX_EN[1] 0 SaX_EN[2] 0 SaX_EN[3] 0 SaX_EN[4] 0 SaX[1] 1 SaX[2] 1 SaX[3] 1 SaX[4] 1 PM6388 EOCTL OCTAL E1 FRAMER 171 ...
Page 191
... Setting the Match Enable (MEN) bit to logic 1 enables the detection and storage in the FIFO of only those packets whose first data byte matches PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default Unused X Unused X Unused X Reserved 0 MEN PM6388 EOCTL OCTAL E1 FRAMER 172 ...
Page 192
... Match Register, and the two least significant bits of the universal all ones address when performing the address comparison. Reserved: This bit must be set to logic 0 for correct operation. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER 173 ...
Page 193
... The Interrupt Enable bit (INTE) must set to logic 1 to allow the internal interrupt status to be propagated to the INTB output. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default INTE 0 INTC[6] 0 INTC[5] 0 INTC[4] 0 INTC[3] 0 INTC[2] 0 INTC[1] 0 INTC[0] 0 PM6388 EOCTL OCTAL E1 FRAMER 174 ...
Page 194
... The packet byte status (PBS[2:0]) bits indicate the status of the data last read from the FIFO. The bits are encoded as follows: PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default FE X OVR X COLS X PKIN X PBS[2] X PBS[1] X PBS[0] X INTR X PM6388 EOCTL OCTAL E1 FRAMER 175 ...
Page 195
... FIFO must be read until empty. The status of the data link is determined by the PBS bits associated with the data read from the FIFO. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER 176 ...
Page 196
... The FIFO buffer empty (FE) bit is set to logic 1 when the last FIFO buffer entry is read. The FE bit goes to logic 0 when the FIFO is loaded with new data. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 PM6388 EOCTL OCTAL E1 FRAMER 177 ...
Page 197
... FIFO Input Status Register is read. The RDLC Status and Data registers should not be accessed at a rate greater than 1/15 of the XCLK rate. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default RD[7] X RD[6] X RD[5] X RD[4] X RD[3] X RD[2] X RD[1] X RD[0] X PM6388 EOCTL OCTAL E1 FRAMER 178 ...
Page 198
... FIFO. PA[0] corresponds to the first bit of the serial byte received on the DATA input. The MM bit in the Configuration Register is used mask off PA[1:0] during the address comparison. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default PA[7] 1 PA[6] 1 PA[5] 1 PA[4] 1 PA[3] 1 PA[2] 1 PA[1] 1 PA[0] 1 PM6388 EOCTL OCTAL E1 FRAMER 179 ...
Page 199
... FIFO. SA[0] corresponds to the first bit of the serial byte received on the DATA input. The MM bit in the Configuration Register is used mask off SA[1:0] during the address comparison. PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default SA[7] 1 SA[6] 1 SA[5] 1 SA[4] 1 SA[3] 1 SA[2] 1 SA[1] 1 SA[0] 1 PM6388 EOCTL OCTAL E1 FRAMER 180 ...
Page 200
... The Abort (ABT) bit controls the sending of the 7 consecutive ones HDLC PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use ISSUE 6 Function Default FLGSHARE 1 FIFOCLR 0 Reserved 0 Unused X EOM 0 ABT 0 CRC PM6388 EOCTL OCTAL E1 FRAMER th that of XCLK. 181 ...