PM73123-PI PMC-Sierra Inc, PM73123-PI Datasheet
PM73123-PI
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PM73123-PI Summary of contents
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... PM73124 / PM73123 ATM Adaptation Layer 1 Segmentation and Reassembly Processor-4/8 Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2000098 Issue 1 AAL1GATOR-4/8 Telecom Standard Product Data Sheet AAL1GATOR-4/8 Data Sheet Proprietary and Confidential Released Issue No. 1: June 2002 ...
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Legal Information Copyright Copyright 2002 PMC-Sierra, Inc. All rights reserved. The information in this document is proprietary and confidential to PMC-Sierra, Inc., and for its customers’ internal use. In any event, no part of this document may be reproduced or ...
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Contacting PMC-Sierra PMC-Sierra 8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: +1 (604) 415-6000 Fax: +1 (604) 415-6200 Document Information: Corporate Information: Technical Support: apps@pmc-sierra.com Web Site: http://www.pmc-sierra.com Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal ...
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Revision History Issue No. Issue Date 1 June 2002 Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2000098 Issue 1 AAL1GATOR-4/8 Telecom Standard Product Data Sheet Details of Change Created data sheet from issue ...
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Table of Contents Legal Information........................................................................................................................... 2 Copyright................................................................................................................................. 2 Disclaimer ............................................................................................................................... 2 Trademarks ............................................................................................................................. 2 Patents 2 Contacting PMC-Sierra.................................................................................................................. 3 Revision History............................................................................................................................. 4 Table of Contents........................................................................................................................... 5 List of Registers............................................................................................................................. 8 List of Figures ................................................................................................................................ 9 List of Tables................................................................................................................................ 13 1 ...
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Processor Interface Block (PROCI) ........................................................................ 118 9.5 RAM Interface Block (RAMI) ................................................................................... 128 14.2 Line Interface Block (AAL1_LI) ............................................................................... 128 9.6 JTAG Test Access Port............................................................................................ 136 10 Memory Mapped Register Description ............................................................................... 137 10.1 Initialization.............................................................................................................. 137 10.2 A1SP and ...
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Reset Timing ........................................................................................................... 279 17.2 SYS_CLK Timing..................................................................................................... 279 17.3 NCLK Timing ........................................................................................................... 280 17.4 Microprocessor Interface Timing Characteristics .................................................... 281 17.5 External Clock Generation Control Interface .......................................................... 285 17.6 RAM Interface ......................................................................................................... 285 17.7 Utopia Interface ....................................................................................................... 286 17.8 ...
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List of Registers Register 0x80000 Reset and Device ID Register (DEV_ID_REG) ......................................... 181 Register 0x80010 A1SP Command Register (A_CMD_REG) ................................................ 182 Register 0x80020 A1SP Add Queue FIFO Register (A_ADDQ_FIFO) .................................. 183 Register 0x80030 A1SP Clock Configuration Register (A_CLK_CFG) .................................. 184 ...
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List of Figures Figure 1 AAL1gator-4 Integrated Access Device (IAD) Application. ............................. 21 Figure 2 AAL1gator-4 APON ONU Application ............................................................. 22 Figure 3 AAL1gator-4/8 Internal Block Diagram ....................................................................... 23 Figure 4 Data Flow and Buffering in ...
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Figure 34 T1 SDF-FR Format of the R_DATA_BUFFER.......................................................... 90 Figure 35 E1 SDF-MF Format of the R_DATA_BUFFER ......................................................... 90 Figure 36 E1 SDF-MF with T1 Signaling Format of the R_DATA_BUFFER ............................ 91 Figure 37 E1 SDF-FR Format of the R_DATA_BUFFER ...
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Figure 69 R_CRC_SYNDROME Mask Bit Table Legend ....................................................... 158 Figure 70 Boundary Scan Architecture ................................................................................... 243 Figure 71 TAP Controller Finite State Machine....................................................................... 245 Figure 72 Input Observation Cell (IN_CELL) .......................................................................... 248 Figure 73 Output Cell (OUT_CELL) ........................................................................................ 248 Figure ...
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Figure 104 MVIP-90 Receive Functional Timing..................................................................... 268 Figure 105 Transmit Line Side T1 Timing(TL_CLK = 1.544 MHz).......................................... 269 Figure 106 Transmit Line Side E1 Timing(TL_CLK = 2.048 MHz).......................................... 269 Figure 107 MVIP-90 Transmit Functional Timing.................................................................... 270 Figure 108 Receive H-MVIP ...
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List of Tables Table 1 Line Interface Signal Table Selection........................................................................... 37 Table 2 CFG_ADDR and PHY_ADDR Bit Usage in SRC direction .......................................... 52 Table 3 CFG_ADDR and PHY_ADDR Bit Usage in SNK direction .......................................... 54 Table 4 Minimum Partial Cell ...
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... Table 47 Receive High Speed Interface Timing...................................................................... 292 Table 48 JTAG Port Interface.................................................................................................. 293 Table 49 AAL1GATOR-4/8 (PM73123/4) Ordering Information.............................................. 295 Table 50 AAL1GATOR-4/8 (PM73123/4) Thermal Information .............................................. 295 Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2000098 Issue 1 AAL1GATOR-4/8 Telecom Standard Product Data Sheet ...
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Features The AAL1 Segmentation And Reassembly (SAR) Processor (AAL1gator-4/ monolithic single chip device that provides DS1, E1, E3, or DS3 line interface access to an ATM Adaptation Layer One (AAL1) Constant Bit Rate (CBR) ATM network. It ...
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In Cell Receive direction, provides per-VC configuration of time slots allocated, CAS signaling support, partial cell size, sequence number processing options, cell delay variation tolerance buffer depth, maximum buffer depth. Processes AAL1 headers in accordance with ITU-T I.363.1. · ...
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Supports AAL0 mode, selectable on a per VC basis. · Provides system side loopback support. When enabled and the incoming VCI matches the programmable loopback VCI, the cell received on the Receive UTOPIA interface is looped back to the ...
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Provides a transmit buffer which can be used for Operations, Administration and Maintenance (OAM) cells as well as any other user-generated cells such as AAL5 cells for ATM signaling. A corresponding receive buffer exists for the reception of OAM ...
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Applications · Multi-service ATM Switch · ATM Access Concentrator · Digital Cross Connect · Computer Telephony Chassis with ATM infrastructure · Wireless Local Loop Back Haul · ATM Passive Optical Network Equipment Proprietary and Confidential to PMC-Sierra, Inc., and ...
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References Applicable Recommendations and Standards. 1. ANSI T1 Recommendation T1.403, Network-to-Customer Installation – DS1 Metallic Interface, NY, NY, 1995. 2. ANSI T1 Recommendation T1.630, Broadband ISDN-ATM Adaptation Layer for Constant Bit Rate Services, Functionality and Specification, NY, NY, 1993. ...
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... ONUs on street locations, in buildings or even in homes. Figure 2 shows the use of the AAL1gator-4 ONU application supporting CES functions. Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2000098 Issue 1 AAL1GATOR-4/8 Telecom Standard Product Data Sheet UTOPIA L2/ UTOPIA L2 Any-PHY PM73123(4) PM7329 AAL1gator- S/UNI-APEX- 8(4) 1K800 PM7328 ATM ...
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... COMET- QUAD Ethernet Video Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2000098 Issue 1 AAL1GATOR-4/8 Telecom Standard Product Data Sheet UTOPIA L2/ UTOPIA L2 Any-PHY PM7329 PM73123 S/UNI-APEX- AAL1gator-8 1K800 PM7328 ATM S/UNI-ATLAS- Interworking 1K800 Function, AAL5 SAR ...
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Block Diagram The AAL1gator-4/8 contains an AAL1 SAR Processor block (A1SP) which work in parallel. The A1SP block interfaces to a common UTOPIA interface on one side and a Line Interface block on the other side which can be ...
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Description The AAL1 Segmentation And Reassembly (SAR) Processor (AAL1gator-4/ monolithic single chip device that provides DS1, E1, E3, or DS3 line interface access to an ATM Adaptation Layer One (AAL1) Constant Bit Rate (CBR) ATM network. It ...
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Pin Diagram The AAL1gator-4/8 is manufactured in a 324 pin, fine pitch, plastic ball grid array (PBGA) package. (23mm x 23 mm). Note that all center pins are thermal ground pins and should be connected to Ground. Bottom View ...
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Bottom View of AAL1gator RL_C LK TL_C LK TL_SYNC PQ H PPH A [7] [7] [7] TL_SYNC RL_SYNC RL_SIG TL_DATA LINE_MO B [6] [7] [7] [7] RL_SIG TL_CLK RL_SYNC C PPL TL_SIG [7] [6] [6] ...
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Pin Description 8.1 UTOPIA Interface Signals (52) Pin Name Note signals have different meanings depending on whether the UTOPIA bus is in ATM master mode, PHY mode or Any-PHY mode. The mode is controlled by the UTOP_MODE and ANY-PHY_EN ...
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Pin Name TATM_D[15]/RPHY_D[15] TATM_D[14]/RPHY_D[14] TATM_D[13]/RPHY_D[13] TATM_D[12]/RPHY_D[12] TATM_D[11]/RPHY_D[11] TATM_D[10]/RPHY_D[10] TATM_D[9]/RPHY_D[9] TATM_D[8]/RPHY_D[8] TATM_D[7]/RPHY_D[7] TATM_D[6]/RPHY_D[6] TATM_D[5]/RPHY_D[5] TATM_D[4]/RPHY_D[4] TATM_D[3]/RPHY_D[3] TATM_D[2]/RPHY_D[2] TATM_D[1]/RPHY_D[1] TATM_D[0]/RPHY_D[0] TATM_PAR/ RPHY_PAR TATM_ENB/RPHY_ENB /RENB Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2000098 Issue 1 AAL1GATOR-4/8 ...
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Pin Name TATM_CLAV/RPHY_CLAV /RPA Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2000098 Issue 1 AAL1GATOR-4/8 Telecom Standard Product Data Sheet Type Pin No. Function ATM: Transmit UTOPIA ATM Layer Bidi J4 Cell Available ...
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Pin Name RPHY_ADD[4]/RSX RPHY_ADD[3]/RCSB RPHY_ADD[2] RPHY_ADD[1] RPHY_ADD[0] RATM_CLK/ TPHY_CLK Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2000098 Issue 1 AAL1GATOR-4/8 Telecom Standard Product Data Sheet Type Pin No. Function ATM: These signals are ...
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Pin Name RATM_SOC/ TPHY_SOC /TSOP RATM_D[15]/TPHY_D[15] RATM_D[14]/TPHY_D[14] RATM_D[13]/TPHY_D[13] RATM_D[12]/TPHY_D[12] RATM_D[11]/TPHY_D[11] RATM_D[10]/TPHY_D[10] RATM_D[9]/TPHY_D[9] RATM_D[8]/TPHY_D[8] RATM_D[7]/TPHY_D[7] RATM_D[6]/TPHY_D[6] RATM_D[5]/TPHY_D[5] RATM_D[4]/TPHY_D[4] RATM_D[3]/TPHY_D[3] RATM_D[2]/TPHY_D[2] RATM_D[1]/TPHY_D[1] RATM_D[0]/TPHY_D[0] RATM_PAR/ TPHY_PAR Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2000098 Issue 1 ...
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Pin Name RATM_ENB/TPHY_ENB RATM_CLAV/TPHY_CLAV Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2000098 Issue 1 AAL1GATOR-4/8 Telecom Standard Product Data Sheet Type Pin No. Function ATM: Receive UTOPIA ATM Layer Bidi M2 Enable is ...
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Pin Name TPHY_ADD[4]/TSX TPHY_ADD[3]/TCSB TPHY_ADD[2] TPHY_ADD[1] TPHY_ADD[0] Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2000098 Issue 1 AAL1GATOR-4/8 Telecom Standard Product Data Sheet Type Pin No. Function ATM: These signals are not used ...
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Microprocessor Interface Signals (42) Pin Name Type D[15] I/O D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] A[19] Input A[18] A[17] A[16] A[15] A[14] A[13] A[12] A[11] A[10] A[9] A[8] A[7] A[6] ...
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Pin Name Type RDB Input CSB Input ACKB Open- Drain Output INTB Open- Drain Output Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2000098 Issue 1 AAL1GATOR-4/8 Telecom Standard Product Data Sheet Pin No. ...
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Ram Interface Signals(40) Pin Name Type RAM_D[15] I/O RAM_D[14] RAM_D[13] RAM_D[12] RAM_D[11] RAM_D[10] RAM_D[9] RAM_D[8] RAM_D[7] RAM_D[6] RAM_D[5] RAM_D[4] RAM_D[3] RAM_D[2] RAM_D[1] RAM_D[0] RAM_A[16] Output RAM_A[15] RAM_A[14] RAM_A[13] RAM_A[12] RAM_A[11] RAM_A[10] RAM_A[9] RAM_A[8] RAM_A[7] RAM_A[6] RAM_A[5] RAM_A[4] RAM_A[3] RAM_A[2] ...
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Pin Name Type RAM_ADSCB/RAM_ Output R/WB RAM_PAR[1] I/O RAM_PAR[0] NOTE: For different modes of the line interface the I/O is redefined. For Direct mode there are 4/8 separate bi-directional lines which can support lines Mbps each with ...
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Pin Name TL_SYNC[7] TL_SYNC[6] TL_SYNC[5] TL_SYNC[4] TL_SYNC[3] TL_SYNC[2] TL_SYNC[1] TL_SYNC[0] TL_DATA[7] TL_DATA[6] TL_DATA[5] TL_DATA[4] TL_DATA[3] TL_DATA[2] TL_DATA[1] TL_DATA[0] TL_SIG[7] TL_SIG[6] TL_SIG[5] TL_SIG[4] TL_SIG[3] TL_SIG[2] TL_SIG[1] TL_SIG[0] Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: ...
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Pin Name TL_CLK[7]/TSM[7] TL_CLK[6]/TSM[6] TL_CLK[5]/TSM[5] TL_CLK[4]/TSM[4] TL_CLK[3]/TSM[3] TL_CLK[2]/TSM[2] TL_CLK[1]/TSM[1] TL_CLK[0]/TSM[0] CTL_CLK RL_SYNC[7] RL_SYNC[6] RL_SYNC[5] RL_SYNC[4] RL_SYNC[3] RL_SYNC[2] RL_SYNC[1] RL_SYNC[0] Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2000098 Issue 1 AAL1GATOR-4/8 Telecom Standard Product ...
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Pin Name RL_DATA[7] RL_DATA[6] RL_DATA[5] RL_DATA[4] RL_DATA[3] RL_DATA[2] RL_DATA[1] RL_DATA[0] RL_SIG[7] RL_SIG[6] RL_SIG[5] RL_SIG[4] RL_SIG[3] RL_SIG[2] RL_SIG[1] RL_SIG[0] RL_CLK[7] RL_CLK[6] RL_CLK[5] RL_CLK[4] RL_CLK[3] RL_CLK[2] RL_CLK[1] RL_CLK[0] CRL_CLK 8.5 Line Interface Signals(H-MVIP)(12) Pin Name LINE_MODE F0B TL_DATA[1] TL_DATA[0] Proprietary and Confidential ...
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Pin Name TL_SIG[1] TL_SIG[0] C16B RL_DATA[1] RL_DATA[0] RL_SIG[1] RL_SIG[0] C4B 8.5.1 Summary of Line Interface Signals The following table shows all modes at the same time and shows how pins are redefined for the different modes. Line Interface Summary Direct ...
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Direct H-MVIP TL_DATA[2] TL_DATA[1] TL_DATA[1] (AAL1gator-8 Only) TL_DATA[0] TL_DATA[0] TL_SIG[7] TL_SIG[6] TL_SIG[5] TL_SIG[4] TL_SIG[3] TL_SIG[2] TL_SIG[1] TL_SIG[1] (AAL1gator-8 Only) TL_SIG[0] TL_SIG[0] TL_CLK[7] TL_CLK[6] TL_CLK[5] TL_CLK[4] TL_CLK[3] TL_CLK[2] TL_CLK[1] TL_CLK[0] CTL_CLK C16B RL_SYNC[7] RL_SYNC[6] RL_SYNC[5] RL_SYNC[4] RL_SYNC[3] RL_SYNC[2] RL_SYNC[1] RL_SYNC[0] RL_DATA[7] ...
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Direct H-MVIP RL_SIG[6] RL_SIG[5] RL_SIG[4] RL_SIG[3] RL_SIG[2] RL_SIG[1] RL_SIG[1] (AAL1gator-8 Only) RL_SIG[0] RL_SIG[0] RL_CLK[7] RL_CLK[6] RL_CLK[5] RL_CLK[4] RL_CLK[3] RL_CLK[2] RL_CLK[1] RL_CLK[0] CRL_CLK C4B 8.6 Clock Generation Control Interface(14) Pin Name CGC_DOUT[3] CGC_DOUT[2] CGC_DOUT[1] CGC_DOUT[0] CGC_LINE[3] CGC_LINE[2] CGC_LINE[1] CGC_LINE[0] SRTS_STBH ADAP_STBH ...
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Pin Name TL_CLK_OE CGC_SER_D CGC_VALID 8.7 JTAG/TEST Signals(7) Pin Name TCLK TMS TDI TDO SCAN_ENB SCAN_MODEB TRSTB RESERVED_OUT RESERVED_IN Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2000098 Issue 1 AAL1GATOR-4/8 Telecom Standard Product ...
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General Signals(3+power/gnd) Pin Name Type RSTB Schmitt Trigger Input Internal Pull-up SYS_CLK Input VDD3.3 Power (PPH, PQH) VDD2.5 Power (PCH) Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2000098 Issue 1 AAL1GATOR-4/8 Telecom ...
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Pin Name Type VSS Ground (PPL, PQL, PCL) Thermal Grounds Ground No Connects Unconnect ed Notes on Pin Description: 1. All AAL1gator-4/8 inputs and bi-directionals present minimum capacitive loading and are 5V tolerant. 2. The AAL1gator-4/8 UTOPIA/Any-PHY outputs and bi-directional ...
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Functional Description The AAL1gator-4/8 is divided into the following major blocks, all of which are explained in this section: · UTOPIA Interface Block (UTOPIAI) · AAL1 SAR Processing Block (A1SP) · Processor Interface Block (PROCI) · RAM Interface Block ...
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Figure 4 Data Flow and Buffering in the UI and the A1SP Block UI TUFIFO (4 cells) RUFIFO (8 cells) In UTOPIA Level Two mode, the AAL1gator-4/8 responds on the UTOPIA bus as a single port device. For UTOPIA to ...
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Figure 5 UI Block Diagram TXUTOPIA SIGNALS RXUTOPIA SIGNALS 9.1.1 UTOPIA Source Interface (SRC_INTF) The SRC_INTF block (shown in Figure 5) conveys the cells received from the UMUX block to the UTOPIA interface. Depending on the value of UTOP_MODE field ...
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In master mode, the SRC_INTF block sources TATM_D, TATM_PAR, TATM_SOC, and TATM_ENB while receiving TATM_CLAV. The Start-Of-Cell (SOC) indication is generated coincident with the first word (only 8-bit mode is supported) of each cell that is transmitted on TATM_D. TATM_D, ...
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The SRC_INTF circuit controls when a cell is transmitted from the internal 4 cell FIFO. Since the UTOPIA can transmit cells at higher speeds than the TALP, and since it is expected to see applications in a shared UTOPIA environment, ...
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Table 2 CFG_ADDR and PHY_ADDR Bit Usage in SRC direction Polling MODE PHY_ADDR Pins UTOPIA-2 [4:0]=device Single-Addr Any-PHY [2:0]=device with CSB Any-PHY [3:0]=device without CSB Notes Any-PHY mode, in the SRC direction the AAL1gator-4/8 will prepend the cell ...
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In UTOPIA Level Two mode, SNK_INTF responds as a single address device. TPHY_CLAV is driven the cycle following ones in which TPHY_ADDR(4:0) matches CFG_ADDR(4:0) in UI_SNK_ADD_CFG register. Otherwise TPHY_CLAV is tri-stated. If, in addition to an address match, during the ...
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Table 3 CFG_ADDR and PHY_ADDR Bit Usage in SNK direction Polling MODE PHY_ADDR Pins UTOPIA-2 [4:0]=device Single-Addr Any-PHY [2]=device [1:0]=”00” with CSB Any-PHY [3:2]=device [1:0]=”00” without CSB Notes Any-PHY mode, if CS_MODE_EN=’1’ then you must program CFG_ADDR[4:3] = ...
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AAL1 SAR Processing Block (A1SP) The A1SP block is the main AAL1 SAR processing block. The block processes 4/8 E1/T1 lines. The remainder of this section refers to the AAL1gator-8 A1SP block with 8 links, but for all cases ...
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Figure 6 A1SP Block Diagram 2 Transmit Frame Input from LI Transfer Controller Block (TFTC External Memory Receive Frame Output to LI Transfer Controller Block (RFTC) 1. TFTC stores line data into the memory 16 bits at a ...
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The RALP performs pointer searches, checks for overrun and underrun conditions, detects SN mismatches, checks for OAM cells, and extracts the line data from the cells, and places the data into the receive buffer. 10. The RFTC plays the ...
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The AAL1gator-4/8 reads the signaling nibble for each channel when it reads the last nibble of each channel’s data unless the SHIFT_CAS bit in the LIN_STR_MODE register is set. If the SHIFT_CAS bit is set then the AAL1gator-4/8 reads the ...
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Figure 9 Transmit Frame Transfer Controller Line 0 Line Interface • • • Line 7 Line Interface The receive line interface is primarily a serial-to-parallel converter. Serial data, which is derived from the RL_DATA signal from the LI Block, is ...
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Figure 10 T1 ESF SDF-MF Format of the T_DATA_BUFFER Figure 11 shows the format of the transmit data buffer for SF-formatted T1 data for lines that are in the SDF-MF mode. Figure 11 T1 SF-SDF-MF Format of the T_DATA_BUFFER Figure ...
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Figure 12 T1 SDF-FR Format of the T_DATA_BUFFER Frame Buffer Number Figure 13 shows the format of the transmit data buffer for E1 data for lines that are in the SDF- MF mode. Figure 13 E1 SDF-MF Format of the ...
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Figure 14 shows the format of the transmit data buffer for E1 data using T1 signaling, for lines that are in SDF-MF mode Figure 14 E1 SDF-MF with T1 Signaling Format of the T_DATA_BUFFER Figure 15 shows the format of ...
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Figure 16 Unstructured Format of the T_DATA_BUFFER Figure 17, Figure 18, Figure 19 and Figure 20 show the contents of the transmit signaling buffer for the different signaling modes. In all cases the upper nibble of each byte is “0000”. ...
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Figure 19 SDF-MF E1 Format of the T_SIGNALING_BUFFER Multiframe Figure 20 SDF-MF E1 with T1 Signaling Format of the T_SIGNALING_BUFFER Multiframe Transmit Conditioning The T_COND_DATA structure allows conditional data to be defined on a per-DS0 basis and the T_COND_SIG structure ...
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Under certain alarm conditions such as Loss of Signal (LOS), an Alarm Indication Signal (AIS) needs to be transmitted downstream. This means that cells need to be generated which carry an AIS pattern. The AAL1gator-4/8 does not do any alarm ...
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CAS Change Detection If CAS change detection is enabled a word is written to the CAS Interrupt FIFO every time the value of the CAS nibble changes and then remains stable for one additional multiframe. CASCHG_FIFO_EMPB is set as long ...
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The following steps (as well as Figure 24 on page 68) describe how the CSD circuit schedules cells for the TALP to build. 1) Once the TFTC writes a complete frame into external memory, it writes the line number and ...
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Figure 24 Frame Advance FIFO Operation Frame Boundaries RL_DATA(0 ) RL_FSYNC(0) RL_DATA(1 ) RL_FSYNC(1) The following is an example of the calculations the CSD circuit performs. This example assumes a structured line with four channels allocated to one queue. 1) ...
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Round 8.625 up, so the frame differential Therefore, the next cell will be sent nine frames ahead of the current cell. Next frame = present frame number + 9 7) The CSD circuit computes the number of ...
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Then the CSD adds the signaling credit adjustment to the total and writes the result to memory, in preparation for the next service on this queue. QUEUE_CREDITS = 48.5 + 0.75 = 49.25 bytes Unstructured lines use a different ...
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Only one cell can be built at a time. Thus if multiple queues are scheduled to send cells during the same frame, additional delay will be incurred. If queues are activated and deactivated so that the number of queues ...
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To send an OAM cell, the microprocessor writes OAM cells into one of two dedicated cell buffers located in external memory. When the cell is assembled in the buffer, the microprocessor must set the appropriate bit in the Command register ...
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A pointer is inserted in the first possible even-numbered cell of every 8-cell sequence. · A pointer value inserted when the structure starts in the byte directly after the pointer itself. · A pointer value of ...
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Figure 25 Payload Generation T FTC writes the bytes in pairs into T_DATA_BUFFER RL_SER . . . . For AAL0 mode the cell build process takes 48 bytes of line data and does not ...
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PCR <= 118,980 cells per second for T3 (assuming 47 bytes for each AAL1 cell). · PCR <= 91,405 cells per second for E3 (assuming 47 bytes for each AAL1 cell). · If all eight lines in an A1SP ...
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When LOOPBACK_ENABLE is set in the TRANSMIT_CONFIG register, cells for that queue will be looped back to the RALP block instead of being transmitted toward the UTOPIA bus. Since this bit is configurable on a per queue basis it can ...
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VCI Mapping The AAL1gator-4/8 supports two options for VCI to queue mapping. Nine bits of the VCI are always used. The nine-bit field can be either located in the least significant bits of the VCI or shifted up 4 bits ...
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Figure 27 Cell Header Interpretation SHIFT_VCI=0 VP_MODE_EN Ignored SHIFT_VCI=1 VP_MODE_EN Ignored Data SHIFT_VCI=X VP_MODE_EN Sequence Number Processing When the cell is a data cell, the RALP verifies the ...
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For the “Robust SN Algorithm”, the RALP makes decisions on the previous cell based on the value of the current SN and SNP and the previous SN and SNP. The RALP either accepts the previous cell, drops the previous cell, ...
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The “Fast SN Algorithm” will, under certain situations, allow bad cells to pass through. When this occurs the cells are marked as potentially bad. Any cells marked as potentially bad will not have pointer verification done on them and ...
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Fast Sequence Number Processing State Machine The RALP sequence number processing state machine begins in the START state. Once a cell is received with a valid SN, the OUT_OF_SYNC state is entered. Any cells received while in the START state, ...
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If the SN is valid and the sequence with the SN of the previous cell, the RALP assumes cells were lost; it inserts a number of dummy cells identical to the number of lost cells, accepts ...
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Figure 28 Fast SN Algorithm invalid SN/discard, force underrun force underrun OUT OF in seq/insert c ells/accept SEQUENCE All cells received while in the SYNC state are accepted whether or not they are good. Any errored cells received while in ...
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Figure 29 Receive Cell Processing for Fast SN Wait for a cell in the receive UTOPIA FIFO. Is the cell a data cell? Is SNP correct correct? Place data and signaling in appropriate timeslots and update write pointers. ...
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If a cell is received with a valid SN and in the correct sequence, then the SYNC state is entered and the previously stored cell is accepted cell with an invalid SN is received, then the ...
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If the SN is valid and the sequence with the SN of the previous cell, the RALP assumes cells were lost; it inserts a number of dummy cells identical to the number of lost cells, accepts ...
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Figure 30 Robust SN Algorithm Invalid discard stored Out of sequence discard stored Out of seq/ accept stored In seq -1+1/accept stored Out In seq/insert cells Of SEQ In seq –1/discard stored If the cell is stored, the RALP then ...
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Line Data Storage The RALP reads the ATM cell from the RALP_FIFO, verifies the header, and determines the queue to which the cell belongs. It then locates the data bytes of the cell and writes them into frame buffers provided ...
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Figure 32 shows the contents of the receive data buffer for ESF-formatted T1 data for lines in the SDF-MF mode. Only the first 24 bytes of each frame buffer and the first 24 frame buffers of every 32 are used. ...
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Figure 34 T1 SDF-FR Format of the R_DATA_BUFFER Figure 35 shows the contents of the receive buffer with E1 data for lines in the SDF-MF mode. Figure 35 E1 SDF-MF Format of the R_DATA_BUFFER Figure 36 shows the contents of ...
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Figure 36 E1 SDF-MF with T1 Signaling Format of the R_DATA_BUFFER Figure 37 shows the contents of the receive data buffers with E1 data for lines in the SDF-FR mode. Figure 37 E1 SDF-FR Format of the R_DATA_BUFFER Figure 38 ...
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Figure 38 Unstructured Format of the R_DATA_BUFFER Figure 39 shows the contents of the receive signaling buffer with an ESF-formatted T1 line in the SDF-MF mode. Even channel bytes are stored in the low-byte end of the data words. Figure ...
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Figure SDF-MF format of the R_SIG_BUFFER 0 1 Multiframe ¸ Figure 41 shows the contents of the receive signaling buffer with an E1 line in the SDF-MF mode. Even channel bytes are stored in the ...
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Figure 42 E1 SDF-MF with T1 Signaling Format of the R_SIG_BUFFER Multiframe Handling Data and Signaling Bytes in a Structure A data structure consists of all of the data bytes for that structure, followed by all of the signaling bytes ...
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Underrun The AAL1gator-4/8 declares an underrun condition for a VC when no data is present in the VC receive buffer. When this situation occurs, the AAL1gator-4/8 plays out conditioned data and frozen signaling onto the timeslots assigned to the VC ...
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Bit integrity may be maintained through an underrun condition if at least one cell is lost and less than 6 cells are lost if the BITI_UNDERRUN is set. In order to detect the amount of lost cells, whenever a cell ...
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Pointer Processing When an incoming cell has a cell pointer, the cell pointer is checked against the local pointer value maintained by the RALP. A single pointer mismatch causes no corrective actions. The pointer is ignored and the cell is ...
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Figure 43 Pointer/Structure State Machine No pointer found Pointer matches prediction and parity good (or not checking parity) Overrun Overrun occurs when the data in the buffer is removed at a slower rate than it is filled. However, because the ...
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Overruns can also occur due to lost/misinserted cells when robust SN processing is done if the buffer is set too small. This is because when the SN processing detects a potentially lost cell event, the cell will be written into ...
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Figure 44 Overrun Detection NOTES : 1 . Normal op erat ion overrun o ccurs, then ERRUN st icky bit ...
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Counters and Sticky Bits The RALP sets sticky bits for overrun, underrun, pointer mismatch, resume, SRTS underrun, SRTS resume, and other conditions. As with most registers, the sticky bits are located in the external RAM. They are set by the ...
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For T1 mode, signaling data may change every 24 th every 16 frame. The RFTC accommodates the T1 Super Frame (SF) mode by treating it like the Extended Super Frame mode( ESF) format. The RFTC generally ignores the multiframe pulses ...
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Each line request is serviced by the main RFTC state machine using a priority encoder (line 0 has the highest priority). The line requests two bytes at a time. This means two channels have to be serviced by the RFTC ...
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Figure 47 Channel-to-Queue Table Operation R_QUEUE_TBL R_ACT_TBL (Note 5) (Notes 1. RFTC fetches R_CH_TO_QUEUE entry for DS0s 6 and 7 for line 2. 2. DS0 6 is being serviced by Queue MOD Queue = ...
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The RFTC supports SRTS only for unstructured data formats on a per-line basis. The SRTS_CDVT value in R_SRTS_CONFIG register must be configured correctly so the time delay value of the SRTS data matches the time delay value of the signal ...
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The CGC consists of four major blocks: External Interface, SRTS, Adaptive, and Frequency Synthesizer. The External Interface passes SRTS and adaptive information out to the user and allows the user to control the Frequency Synthesizer. The SRTS block receives SRTS ...
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CGC BLOCK DIAGRAM Playout Interface Ext Freq Select Interface 9.3.1 Functional Description The CGC consists of four major blocks: External Interface, SRTS, Adaptive, and Frequency Synthesizer. External Interface The External Interface transmits and receives line clock related information that ...
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The External Interface block transmits either SRTS, Adaptive, or Channel Status information on a line basis which enables an external decision to made about altering the line clock frequency. The SRTS output data is the difference between the local and ...
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Channel Underrun Status Output Figure 50 shows an example of the channel underrun status being reported on the CGC Interface. In this example for a structured line, the line number is 3, the channel pair is 7 (channels 14 and ...
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The AAL1gator-4/8 implements a programmable weighted moving average internally. However alternative adaptive algorithm is desired then this information can be processed externally. In High Speed mode, since DS3 clock cannot be internally synthesized, this information ...
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The External Interface block has two input ports that allow an external source to control the frequency synthesizers internal to the CGC. These two ports are CGC_SER_D and CGC_VALID. CGC_SER_D contains the data that selects one of the 171/240 frequencies ...
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SRTS is supported for unstructured data formats on a per-line basis. SRTS support requires an input reference clock (NCLK). The input reference frequency is defined as 155. where n is chosen so the reference clock frequency is greater ...
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Adaptive The Adaptive block determines the appropriate line clock frequencies based on the buffer depth received from the A1SP. Every time a cell is received on a particular line, the Adaptive block is given the current depth of the receive ...
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Note that adaptive clocking, in general, is not well suited for voice applications since low frequency or DC changes of the CDV will pass through most filters and cause frame slips. Adaptive clocking is only supported for unstructured connections inside ...
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In order for this block to work properly, the system clock must be 38.88 MHz. The accuracy of the synthesized clock is dependent on the accuracy of SYS_CLK. Therefore ppm T1 clock is desired, SYS_CLK needs to ...
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Table 7 Frequency Select – T1 Mode Freq Select -128 -127 -126 -125 … -96 -95 -94 -93 -92 … … … 124 125 126 127 * ...
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E1 Mode In E1 mode the 2.048 MHz nominal frequency is synthesized by maintaining a certain ratio of long cycles to short cycles. The long cycle is comprised of 19 SYS_CLK periods (38.88 MHz). The short cycle is comprised of ...
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Table 8 Frequency Select – E1 Mode Freq Select -128 -127 -126 -125 -124 -123 -122 -121 -120 -119 … … 109 110 111 112 … 124 125 126 127 * ...
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Figure 55 shows the memory region broken into three blocks. The first block, A1SP SRAM, is the memory mapped registers which are mostly contained within SRAM. The second block, Internal Registers, is composed of configuration registers common to the entire ...
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Figure 57 Control Registers Memory Map Figure 58 shows the format of the Transmit Data Structures block in more detail. Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2000098 Issue 1 AAL1GATOR-4/8 Telecom Standard ...
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Figure 58 Transmit Data Structures Memory Map Figure 59 shows the format of the Receive Data Structures block in more detail. Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2000098 Issue 1 AAL1GATOR-4/8 Telecom ...
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Figure 59 Receive Data Structures Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2000098 Issue 1 AAL1GATOR-4/8 Telecom Standard Product Data Sheet 08000 R_OAM_QUEUE_TBL 08001 08002 R_OAM_CELL_CNT 08003 R_DROPPED_OAM_CELL_CNT 08004 Unused 0801F 08020 Reserved ...
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Figure 60 below shows the format of the Normal Mode Registers block in more detail. Figure 60 Normal Mode Registers Memory Map 9.4.1 Interrupt Driven Error/Status Reporting The interrupt logic has several layers and can be sourced from any of ...
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Figure 61 Interrupt Hierarchy A1SP_INTR_REG A1SP_TIDLE_FIFO A1SP Interrupts A1SPn Interrupts UTOPIA Interrupts The UTOPIA block sources five interrupts directly to the Master Interrupt Register. The five interrupts are Transmit UTOPIA FIFO full, Loopback FIFO full, UTOPIA parity error, runt cell ...
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A1SP Interrupts The A1SP block sources an interrupt to the Master Interrupt Register. The A1SP interrupt register indicates the source of the interrupt within the A1SP block. Since many indications provided by the A1SP interrupt structure are per channel or ...
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Add Queue FIFO In order to add a queue the processor has to write the ADDQ_FIFO. The ADDQ_FIFO consists of 64 16-bit entries and is accessed using a single address. The format of the ADDQ_FIFO word is shown in ...
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Note that the reference value is optimized to the configuration consisting of all 24 (T1 (E1) queues configured identically as single DS0 with no pointer, full cells, and no CAS. This is the configuration that is most likely ...
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RAM Interface Block (RAMI) The RAMI is the central arbiter for all memory accesses. It provides a priority mechanism that incorporates fairness to satisfy all real-time requirements of the various blocks. All blocks requesting a data transfer with the ...
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Note clocks rates MHz are supported in this mode. However, the aggregate bandwidth cannot exceed 20 Mbps. Therefore, if all 4 lines of the A1SP are used and are the same rate, 5 MHz is the highest ...
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Figure 63 Line Interface Block Architecture To A1SP The different modes of the Line Interface Block require the pin definitions to change depending on the mode you are in. See Section 8.5.1 for exact definitions. The AAL1gator supports several different ...
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In the transmit direction, frame and multi-frame resync events cause the following events to happen: · Frame and bit counters realign to the new frame/multi-frame boundary · A forced underrun will occur so that the AAL1 receiver can realign correctly ...
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In the receive direction, the CLK_SOURCE_RX bit has two possible options. If this bit is set then the line receives its clock from the CRL_CLK pin. If this bit is not set then the line receives its clock from the ...
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It is not necessary to provide an edge at the beginning of every frame or multi-frame. However if a frame or multi-frame pulse is detected on a non-frame or non-multi-frame boundary, then the AAL1gator-4/8 will resync to the new boundary ...
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Note: 1. AAL1gator-4/8 treats all 32 timeslots identically. Although E1 data streams contain 30 timeslots of channel data, 1 timeslot of framing (timeslot 0) and one time slot that can either be signaling or data (time slot 16), data and ...
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Figure 66 Output of T1 Signaling Bits TL_SER 1 (timeslots ) ABCD XXXX XXXX TL_SIG Channel 0 XXXX - indicates signaling is i lid Figure 67 Output of E1 Signaling Bits TL_SER 0 (timeslots ) ABCD XXXX XXXX TL_SIG Channel ...
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See section 14.6.2 for diagrams showing relationship between external transmit H-MVIP data and internal 2 Mbps data. In H-MVIP mode there is a common 16 MHz clock (HMVIP16CLK) whose every other rising edge is used to sample data on all ...
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Memory Mapped Register Description The Chip SW_RESET state is automatically entered after a hardware reset is removed can be asserted by setting the SW_RESET bit in the DEV_ID_REG. (Note memory cannot be accessed while the chip SW_RESET ...
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Notes: 2. All ports marked as “Reserved” must be initialized initial setup. Software modifications to these locations after setup will cause incorrect operation. 3. All read/write port bits marked “Not used” must be written with the value ...
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Field (Bits) Not used (13:6) HS_GEN_DS3_AIS (5) HS_TX_COND (4) HS_RX_COND (3) UDF_HS (2) Unused (1:0) LIN_STR_MODE Organization: Eight 16-bit words. Base address within A1SP: 10 Index Type: Read/Write Function: Stores the per-line configuration. Writes to this memory register ...
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LIN_STR_MODE Word Format Field (Bits) LOW_CDV (15) REF_VAL_ENABLE (14) T1_MODE (13) E1_WITH_T1_SIG (12) HI_RES_SYNTH (11) Reserved (10) MF_ALIGN_EN (9) SHIFT_CAS (8) GEN_SYNC (7) Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2000098 Issue 1 ...
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Field (Bits) CLK_SOURCE_TX (6:4) CLK_SOURCE_RX (3) SRTS_EN (2) FR_STRUCT (1:0) 10.3 Transmit Structures Summary Table 12 Transmit Structures Summary Note the addresses listed below are the offsets within the A1SP address space. Name P_FILL_CHAR Proprietary and Confidential to PMC-Sierra, Inc., ...
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Name Reserved(AQ) T_SEQNUM_TBL T_COND_SIG T_COND_DATA Reserved Reserved Reserved T_OAM_QUEUE T_QUEUE_TBL Reserved Notes: 1. All ports marked as “Reserved” must be initialized initial setup. Software modifications to these locations after setup will cause incorrect operation. 2. All read/write ...
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Field (Bits) Not used (15:8) P_FILL_CHAR (7:0) 10.3.2 T_SEQNUM_TBL Organization: 16 words Base address within A1SP: 20 Index Type: Read/Write Function: Stores all possible first bytes in the payload: CSI, SN, and SNP. This table must be loaded ...
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Type: Read/Write Function: Stores the transmit conditioned signaling. Initialization: Initialize to the conditioned signaling value for the channel. This value typically depends on the type of channel unit that is connected. For example, a Foreign Exchange Office (FXO) needs a ...
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Base address within A1SP: 480 Index Type: Read/Write Function: Stores the transmit conditioned data. Initialization: Initialize to the conditioned data appropriate for the channel, which typically depends on the type of channel connected to the device. For example, ...
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Function: Stores the outgoing signaling data. Figure 68 SDF-MF Format of the T_SIGNALING BUFFER 10.3.6 T_OAM_QUEUE Organization: 2 cells x 32 words Base address within A1SP: 01400 Index Type: Read/Write Function: Stores two transmit OAM cells. Initialization: An ...
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T_OAM_CELL_n Format Offset Word 0 Word 1 Word 2 Word Word 26 10.3.7 T_QUEUE_TBL Organization: 256 x 32 words. Only 128 queues used with A4. Base address within A1SP: 2000 Index Type: Read/Write Function: ...
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Offset Name 8 TX_HEAD(1: TX_HEAD(3: TX_HEAD( QUE_CREDITS h C CSD_CONFIG h D Not used h E T_CHAN_ALLOC(15: T_CHAN_ALLOC(31:16 T_CHAN_LEFT(15: T_CHAN_LEFT(31:16 TRANSMIT_CONFIG h 13 -1F Not used ...
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Field (Bits) TX_ACTIVE (14) FRAMES_PER_CELL (13:8) T_CHAN_NO_SIG (7) T_CHAN_UNSTRUCT (6) Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2000098 Issue 1 AAL1GATOR-4/8 Telecom Standard Product Data Sheet Description When set, this bit enables this ...
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Field (Bits) BYTES_PER_CELL (5:0) T_CELL_CNT Word Format (07 Initialize to “0000” and at all other times the word is read only. The word is maintained by TALP. Field (Bits) T_CELL_CNT (15:0) TX_HEAD(1:2) Word Format (08 This word is maintained by ...
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TX_HEAD(5) Word Format (0A This word is maintained by the microprocessor. . Note: in UDF-HS mode, TALP reads this word only once, before it generates the first cell of the connection result, any writes to this word after ...
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Field (Bits) AVG_SUB_VALU (9:0) T_CHANNEL_ALLOC(15:0) Word Format (0E This word is maintained by the microprocessor. Field (Bits) T_CHANNEL_ALLOC (15:0) T_CHANNEL_ALLOC(31:16) Word Format (0F This word is maintained by the microprocessor. Field (Bits) T_CHANNEL_ALLOC (31:16) T_CHANNEL_LEFT(15:0) Word Format (10 After initialization ...
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Field (Bits) SUPPRESS_XMT (15) LOOPBACK_ENABLE (14) AAL0_MODE_ENABLE (13) COND_MODE (12:11)) Reserved (10) Reserved (9) Not used (8:0) 10.3.8 RESERVED (Transmit Data Buffer) This structure is reserved and must be initialized initial setup. Software modifications to this location ...
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Format: Two data bytes per word, 16 words per frame. T_DATA_BUFFER Word Format Field (Bits) T_DATA_H (15:8) T_DATA_L (7:0) 10.4 Receive Data Structures Summary Table 25 lists the data structures unique to the receive side of the AAL1gator-4/8. Note the ...
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Name Reserved This section describes the structures used by the receive side of the AAL1gator-4/8. Notes: 1. All ports marked as “Reserved” must be initialized initial setup. Software modifications to these locations after setup will cause incorrect ...
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OAM_HEAD Word Format Field(Bits) OAM_HEAD (7:0) OAM_TAIL Word Format Field(Bits) OAM_TAIL (7:0) 10.4.2 R_OAM_CELL_CNT Organization: 1 word Base address within A1SP: 8002 Index Type: Read/Write Function: 16-bit rollover counter that counts the number of OAM cells received. The ...
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R_DROP_OAM_CELL Word Format Field(Bits) R_DROP_OAM_CELL (15:0) 10.4.4 R_SRTS_CONFIG Organization: 2 bytes x 8 lines 4 lines. Base address within A1SP: 8038 Index Type: Read/Write Function: This table stores the CDVT for the SRTS channel, expressed in the number ...
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R_CRC_SYNDROME Organization: 128 words Base address within A1SP: 8080 Index Type: Read/Write Function: This table identifies which bit of the SN/SNP byte has been corrupted, if any. Load after each power cycle. Used internally to perform CRC ...
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Sequence Offset Number ...
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Sequence Offset Number 10.4.6 R_CH_TO_QUEUE_TBL Organization: 128 words (8 lines ...
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R_CH_TO_QUEUE_TBL Format Offset Name N R_CH_TO_QUEUE R_CH_TO_QUEUE Word Format Field(Bits) RX_COND_H (15:14) RX_SIG_COND_H (13) QUEUE_H (12:8) RX_COND_L (7:6) RX_SIG_COND_L (5) QUEUE_L (4:0) Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2000098 Issue 1 AAL1GATOR-4/8 ...
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R_COND_SIG Organization: 16 words lines Base address within A1SP: 8400 Index Type: Read/Write Function: This table stores the signaling to be used when RX_SIG_COND_H or RX_SIG_COND_L equals “1” in the R_CH_TO_QUEUE_TBL. Initialization: Initialize to ...
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Field (Bits) R_COND_B_L (2) R_COND_C_L (1) R_COND_D_L (0) 10.4.8 R_COND_DATA Organization: 16 words lines Base address within A1SP: 8480 Index Type: Read/Write Function: This table stores the data to be used when RX_COND in the ...
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RESERVED (Receive SRTS Queue) This structure is reserved. Software modifications to this structure after setup will cause incorrect operation. Organization: 64 words x 8 lines. 4 lines. Each line is allocated a separate 64-entry queue to store the SRTS ...
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Index (line): 200 h Type: Read/Write Function: The receive signaling queue stores the signaling that is received from the UTOPIA interface. Initialization: The signaling buffer should be initialized to “0”. Also, if R_CHAN_NO_SIG is set for some queues and a ...
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Table 14 R_QUEUE_TBL Format Offset Name 0 R_STATE_0 h 1 R_MP_CONFIG h 2 R_STATE_1 h 3 R_LINE_STATE h 4 R_BUF_CFG h 5 R_SEQUENCE_ERR h 6 R_INCORRECT_SNP h 7 R_CELL_CNT h 8 R_ERROR_STKY h 9 R_TOT_SIZE h A R_DATA_LAST h B ...
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R_STATE_0 Word Format (00 This word is read-only and is maintained by the RALP Field (Bits) Reserved (15) R_STRUCT_FOUND (14) Reservd(OLDUNDRN_N) (13) Reservd(UNDRN_2AGO) (12) Reserved(ACTSN) (11:9) SN_STATE (8: _LAST_SN (5:3) LAST_SN (2:0) R_MP_CONFIG Word Format (01 This word ...
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R_STATE_1 Word Format (02 This word is read-only and is maintained by the RALP. This register is located inside the chip and is reset to “0000” Field (Bits) Reserved (FRC_UNDRN) (15) Reserved (SNCRCST) (14) Reserved (PTRMMST) (13) Reserved (FNDPTR) (12) ...
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Field (Bits) R_CHAN_UNSTRUCT (15) R_CHAN_NO_SIG (14) R_CHAN_DISABLE (13) BITI_UNDERRUN (12) Reserved (11:10) Reserved (9) R_MAX_BUF (8:0) R_SEQUENCE ERROR Word Format (05 This word is read-only and is maintained by the RALP Field (Bits) R_SEQUENCE_ERR (15:0) R_INCORRECT_SNP Word Format (06 This ...
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Field (Bits) R_INCORRECT_SNP (15:0) R_CELL_CNT Word Format (07 This word is read-only and is maintained by the RALP Field (Bits) R_CELL_CNT (15:0) R_ERROR_STKY Word Format (08 Receive sticky bits should be used for statistics gathering purposes only as there is ...
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Field (Bits) SN_CELL_DROP (8) POINTER_RECEIVED (7) PTR_PARITY_ERR (6) SRTS_RESUME (5) SRTS_UNDERRUN (4) RESUME (3) PTR_MISMATCH (2) OVERRUN (1) UNDERRUN (0) R_TOT_SIZE Word Format (09 This word is maintained by the microprocessor Field (Bits) FRAMES_PER_CELL (15:10) R_TOT_SIZE (9:0) R_DATA_LAST Word Format ...
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Field (Bits) Not used (15:13) LAST_CHAN (12:8) Not used (7:6) Reserved (5:4) R_DATA_LAST (3:0) R_TOT_LEFT Word Format (0B This word is read-only and is maintained by RALP Field (Bits) Not used (15) Reserved (14) Reserved (13) Reserved (12:11) Not used ...
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Field (Bits) INSERT_DATA (6:5) DISABLE_SN (4) NODROP_IN_START (3) MAX_INSERT (2:0) R_CHAN_ALLOC(15:0) Word Format (0E This word is maintained by the microprocessor Field (Bits) R_CHAN_ALLOC (15:0) R_CHAN_ALLOC(31:16) Word Format (0F This word is maintained by the microprocessor Field (Bits) R_CHAN_ALLOC (31:16) ...
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Field (Bits) R_DROPPED_CELLS (15:0) R_UNDERRUNS Word Format (13 This word is read-only and is maintained by the RALP Field (Bits) R_UNDERRUNS (15:0) R_LOST_CELLS Word Format (14 This word is read-only and is maintained by the RALP Field (Bits) R_LOST_CELLS (15:0) ...
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Field (Bits) R_POINTER_REFRAME (15:0) R_PTR_PAR_ERR Word Format (17 This word is read-only and is maintained by the RALP Field (Bits) R_PTR_PAR_ERR (15:0) R_MISINSERTED Word Format (18 This word is read-only and is maintained by the RALP Field (Bits) R_MISINSERTED (15:0) ...
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R_OAM_QUEUE Organization: 256 cells x 64 bytes Base address within A1SP: E000 Index Type: Read/Write Function: The receive signaling queue stores the signaling received from the UTOPIA interface. Initialization not necessary to initialize this structure. ...
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RESERVED (Receive Data Buffer) This structure is reserved and must be initialized initial setup. If RX_COND for some channels is set to “11” (insert old data during underrun), then those channels may need to be initialized ...
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Field (Bits) R_DATA_L (7:0) Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2000098 Issue 1 AAL1GATOR-4/8 Telecom Standard Product Data Sheet Description Receive data for: Channel = (offset mod 16 frame ...
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Normal Mode Register Description Normal mode registers are used to configure and monitor the operation of the AAL1gator-4/8. Internal Registers are selected when A[19] is high. Normal mode registers are selected when A[18] is low. Test registers are accessed ...
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Address Register Description 0x80030 Clock Configuration for A1SP Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2000098 Issue 1 AAL1GATOR-4/8 Telecom Standard Product Data Sheet Release Register Mnemonic A_CLK_CFG 180 ...
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Register 0x80000 Reset and Device ID Register (DEV_ID_REG) Bit Type 15 R/W 14:7 Rsvd 6:4 R 3:0 R DEV_ID[3:0] The ID bits can be read to provide a binary number indicating the AAL1gator-4/8 feature version. These bits are incremented only ...
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Register 0x80010 A1SP Command Register (A_CMD_REG) Bit Type Bit 15 R Bit 14 R Bit 13 R Bit 12 R Bit 11 R Bit 10 R Bit 9 R Bit 8 R Bit 7 R Bit 6 R Bit 5 ...
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Register 0x80020 A1SP Add Queue FIFO Register (A_ADDQ_FIFO) Bit Type Rsvd 13:8 WO 7:0 WO This register is the write port word FIFO that is used to add a queue on a first come ...
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Register 0x80030 A1SP Clock Configuration Register (A_CLK_CFG) Bit Type 15: R/W 8:5 R/W 4:0 R/W ADAP_FILT_SIZE When a line is configured to use the internal adaptive clocking algorithm, this field defines the size of the filtering window. The ...
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Register 0x80100 RAM Configuration Register (RAM_CFG_REG) Bit Type 15:2 R/W 1 R/W 0 R/W This register controls the configuration of the external RAM. SSRAM_ZBT_MODE When set to 0, the pipelined single-cycle deselect SSRAM protocol is used on the RAM interface ...
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Register 0x80120 UI Common Configuration Register (UI_COMN_CFG) Bit Type 15 R/W 3 R/W 2 R/W 1 R/W 0 R/W This register controls the general configuration of the Utopia Interface UI_EN When set, enables the UTOPIA Interface in both ...
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SHIFT_VCI Selects the VCI Address range used for mapping to queue numbers. This bit only controls the reception of cells. This field is not used if VP_MODE_EN is set. 0) Will use VCI(7:0) as the queue number if VCI(8) = ...
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Register 0x80121 UI Source Config Reg (UI_SRC_CFG) Bit Type 15 R/W 4 R/W 3 R/W 2 R/W 1:0 R/W This register controls the source side configuration of the Utopia Interface UTOP_MODE(1:0) Selects the UTOPIA operating mode for the ...
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CS_MODE_EN When set, RPHY_ADDR(3)/RCSB input pin is used as a chip select (RCSB) for the source side interface, when clear RPHY_ADDR(3)/RCSB is used as an address bit (RPHY_ADDR(3)). This bit should only be set in Any-PHY mode. ...
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Register 0x80122 UI Sink Config Reg (UI_SNK_CFG) Bit Type 15 R/W 4 R/W 3 R/W 2 R/W 1:0 R/W This register controls the sink side configuration of the Utopia Interface UTOP_MODE(1:0) Selects the operating mode for the sink ...
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CS_MODE_EN When set, TPHY_ADDR(3)/TCSB input pin is used as a chip select (TCSB) for the sink side interface, when clear TPHY_ADDR(3)/TCSB is used as a regular address bit (TPHY_ADDR(3)). This bit should only be set in Any-PHY ...
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Register 0x80123 Slave Source Address Config Register (UI_SRC_ADD_CFG) Bit Type 15:0 R/W CFG_ADDR(15:0) These bits contain the configured slave address used for Utopia-2 and Any-PHY operation in the source direction. Depending on the mode of the UTOPIA/Any-PHY interface different bits ...
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Register 0x80124 Slave Sink Address Config Register (UI_SNK_ADD_CFG) Bit Type 15:0 R/W CFG_ADDR(15:0) These bits contain the configured slave address used for Utopia-2 and Any-PHY operation in the sink direction. Depending on the mode of the UTOPIA/Any-PHY interface different bits ...
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Register 0x80125 Loopback VCI (U2U_LOOP_VCI) Bit Type 15:0 R/W U2U_LOOP_VCI(15:0) If VCI_U2U_LOOP is set in the UI_COMN_CFG_REG, any cell received from the UI bus, with a VCI which matches this programmed VCI, will be sent back out ...
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Register 0x80200H, 01H …03H: Low Speed Line n Configuration Registers(LS_Ln_CFG_REG) Bit Type Bit 15 Rsvd Bit 14 Rsvd Bit 13 Rsvd Bit 12 Rsvd Bit 11 Rsvd Bit 10 Rsvd Bit 9 Rsvd Bit 8 Rsvd Bit 7 Rsvd Bit ...
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Register 0x80210H Line Mode Register(LINE_MODE_REG) Bit Type Bit 15 Rsvd Bit 14 Rsvd Bit 13 Rsvd Bit 12 Rsvd Bit 11 Rsvd Bit 10 Rsvd Bit 9 Rsvd Bit 8 Rsvd Bit 7 Rsvd Bit 6 Rsvd Bit 5 Rsvd ...
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Address Register Description 0x81020 A1SP Status Register 0x81030 A1SP CAS Change FIFO 0x81040 A1SP Receive Status FIFO 0x81100 Master Interrupt Enable Register 0x81110 A1SP Interrupt Enable Register 0x81140 A1SP Receive Status FIFO Enable Register 0x81150 A1SP Receive Queue Error Enable ...
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Register 0x81000 Master Interrupt Register (MSTR_INTR_REG) Bit Type R2C 9 R2C 8 R2C 7 R2C 6 R2C 5 R2C 4 R2C ...
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UTOP_PAR_ERR When set, indicates there was a parity error encountered in the UTOPIA interface. This bit is cleared on read. On read parity error encountered in UTOPIA interface 1) Parity error encountered in UTOPIA interface T_UTOP_FULL When set, ...
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Register 0x81010 A1SP Interrupt Register (A1SP_INTR_REG) Bit Type R2C 5 R2C 4 R2C 3 R2C 2 R2C 1 R2C 0 R2C ...