LM96000 National Semiconductor, LM96000 Datasheet
LM96000
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LM96000 Summary of contents
Page 1
... VCCP, 2.5V, 3.3VSBY, 5.0V, and 12V supplies (in- ternal scaling resistors). To set fan speed, the LM96000 has three PWM outputs that are each controlled by one of three temperature zones. High and low PWM frequency ranges are supported. The LM96000 includes a digital filter that can be invoked to smooth temperature readings for better control of fan speed ...
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... VCCP_IN 23 www.national.com 24 Pin TSSOP NS Package MTC24E Top View LM96000CIMT (61 units per rail), or LM96000CIMTX (2500 units per tape and reel) Type Name and Function/Connection Digital I/O System Management Bus Data. Open-drain output. 5V tolerant, (Open-Drain) SMBus 2.0 compliant. Digital Input System Management Bus Clock. Tied to Open-drain output. 5V tolerant, SMBus 2 ...
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... Digital Input Input for monitoring tachometer output of fan 3. Digital Input Input for monitoring tachometer output of fan Address Select Mode, determines the SMBus address of the LM96000. Digital Open-Drain Fan speed control 1. When in XOR tree test mode, functions as Output XOR Tree output. ...
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... VCCP_IN and All Other Inputs −0.05V to (V+ + 0.05V) VID0–VID4 2500V Typical Supply Current 250V = T over T =0˚ MIN MAX is the junction temperature of the LM96000 Conditions Converting, Interface and Fans Inactive, Peak Current Converting, Interface and Fans Inactive, Average Current T =25˚ =0˚ ...
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... Spin-Up Time Interval Accuracy SPIKE SMOOTHING FILTER Time Interval Deviation Time Interval Range SMBUS TIMING CHARACTERISTICS f SMBus Operating Frequency SMB (Continued over T =0˚ MIN MAX is the junction temperature of the LM96000 Conditions V =0. OUT OUT OUT V ...
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... Parasitic components and/or ESD protection circuitry are shown below for the LM96000’s pins. The nominal breakdown voltage the zener is 6.5V. Care should be taken not to forward bias the parasitic diode D1 present on pins D+ and D− ...
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... If the theoretical input voltage was applied to an LM96000 that has positive error, the LM96000’s reading would be less than the theoretical. Note 13: This specification is provided only to indicate how often temperature and voltage data is updated. The LM96000 can be read at any time without regard to conversion state (and will yield last conversion result) ...
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... START bit (bit 0), in the Ready/Lock/Start/Override register (address 40h), is set. Once the fan mode is updated, by setting the START bit to 1, the LM96000 will operate using the values that were set by the BIOS in the fan control limit and parameter registers (adress 5Ch through 6Eh). ...
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... AUTO FAN CONTROL OPERATING MODE The LM96000 includes the circuitry for automatic fan control. In Auto Fan Mode, the LM96000 will automatically adjust the PWM duty cycle of the PWM outputs. PWM outputs are assigned to a thermal zone based on the fan configuration registers possible to have more than one PWM output assigned to a thermal zone ...
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Functional Description Register Read/ Register Address Write Name 49h R/W 3.3V High Limit 4Ah R/W 5V Low Limit 4Bh R/W 5V High Limit 4Ch R/W 12V Low Limit 4Dh R/W 12V High Limit 4Eh R/W Processor (Zone1) Low Temp 4Fh ...
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... This reading will cause the zone limit bit(s) (bits 6 and 4) in the Interrupt Status Register (41h) and the remote diode fault status bit(s) (bit the Interrupt Status Register 2 (42h set. The Temperature Reading registers are updated automatically by the LM96000 at a minimum frequency of 4 Hz. These registers are read only — a write to these registers has no effect. ...
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... FF FFh indicates that the fan is not spinning, or that the tachometer input is not connected to a valid signal. These registers are read only — a write to these registers has no effect. When the LSByte of the LM96000 16-bit register is read, the other byte (MSByte) is latched at the current value until it is read. At the end of the MSByte read the Fan Tachometer Reading registers are updated. ...
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... The four least significant bits of the Version/Stepping register [3.0] contain the current stepping of the LM96000 silicon. The four most significant bits [7.4] reflect the LM96000 base device number when set to a value of 0110b. For the LM96000, this register will read 01101000b (68h). Bit 3 of the stepping field is set to indicate that the LM96000 is a super-set of the LM85 family of products. ...
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... This register will hold a set bit(s) until the event is read by software. The contents of this register will be cleared (set to 0) automatically by the LM96000 after it is read by software, if the fault condition is no longer exists. Once set, the Interrupt Status Register 1 bits will remain set until a read event occurs, even if the fault condition no longer exists This register is read only — ...
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... Interrupt Status Register 2 will hold a set bit until the event is read by software. The contents of this register will be cleared (set to 0) automatically by the LM96000 after it is ready by software, if fault condition no longer exists. Once set, the Interrupt Status Register 2 bits will remain set until a read event occurs, even if the fault no longer exists This register is read only — ...
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... R VID0–4 The VID register contains the values of LM96000 VID0–VID4 input pins. This register indicates the status of the VID lines that interconnect the processor to the Voltage Regulator Module (VRM). Software uses the information in this register to determine the voltage that the processor is designed to operate at. With this information, software can then dynamically determine the correct values to place in the VCCP Low Limit and VCCP High Limit registers. This register is read only — ...
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... LM96000 in the Interrupt Status Register 1 (41h). For example, if the temperature read from the Remote1− and Remote1+ inputs exceeds the Processor (Zone1) High Temp register limit setting, Interrupt Status Register 1 ZN1 bit will be set. The temperature limits in these registers are represented as 8 bit, 2’ ...
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Functional Description to ensure that the limit is high enough not to cause sporadic alerts. The fan tachometer will not cause a bit to be set in Interrupt Status Register 2 if the current value in Current PWM Duty registers ...
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Functional Description SPIN[2:0] 000 001 010 011 100 101 110 111 4.15 Registers 5F-61h: Auto Fan Speed Range, PWM Frequency Register Read/ Register Address Write Name 5Fh R/W Zone1 Range/Fan1 Frequency 60h R/W Zone2 Range/Fan2 Frequency 61h R/W Zone3 Range/Fan3 ...
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... Above (Zone 1 Fan Temp Limit) + (Zone 1 Range), the duty cycle will be 100%. PWM frequency bits [3:0] The PWM frequency bits [3:0] determine the PWM frequency for the fan.The LM96000 has high and low frequency ranges for the PWM outputs, that are controlled by the HLFRQ bit. ...
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... If the Remote1 or Remote2 pins are connected to a processor or chipset, instantaneous temperature spikes may be sampled by the LM96000. If these spikes are not ignored, the CPU fan (if connected to LM96000) may turn on prematurely and produce unpleasant noise. For this reason, any zone that is connected to a chipset or processor should have spike smoothing enabled. ...
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Functional Description 4.17 Registers 64-66h: Minimum PWM Duty Cycle Register Read/ Register Address Write Name 64h R/W Fan1 PWM Minimum 65h R/W Fan2 PWM Minimum 66h R/W Fan3 PWM Minimum These registers specify the minimum duty cycle that the PWM ...
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Functional Description 25.7KHz PWM Frequency PWM Duty Cycle Level (%) Value in Decimal 14. 21. 28. 35. 42. 109 50.00 ...
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Functional Description TABLE 10. Temperature Limit vs Register Setting (Continued) Temperature 4.19 Registers 6A-6Ch: Absolute Temperature Limit Register Read/ Register Address Write Name 6Ah R/W Zone1 Absolute Temp Limit 6Bh R/W Zone2 Absolute Temp Limit 6Ch R/W Zone3 Absolute Temp ...
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... PWM1 output must control the fan that has it’s tachometer output connected to the TACH1 LM96000 input. PWM2 output must control the fan that has it’s tachometer output connected to the TACH2 LM96000 input. PWM3 output must control the fans that have their tachometer outputs connected to the TACH3 or TACH4 LM96000 inputs. Setting (Tn[1:0]) Mode Function ...
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... XOR TEST MODE The LM96000 incorporates a XOR tree test mode. When the test mode is enabled by setting the “XEN” bit high in the Test Register at address 6Fh via the SMBus, the part will enter XOR test mode. Since the test mode an XOR tree, the order of the signals in the tree is not important. SMBDAT and SMBCLK are not to be included in the test tree ...
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Applications Information Typical Applications Schematic 27 20084609 www.national.com ...
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... Physical Dimensions inches (millimeters) unless otherwise noted Order Number LM96000CIMT or LM96000CIMTX National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. ...