MSP3410D Micronas, MSP3410D Datasheet
MSP3410D
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MSP3410D Summary of contents
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... MICRONAS Edition May 14, 1999 6251-482-2PD PRELIMINARY DATA SHEET MSP 3400D, MSP 3410D Multistandard Sound Processors MICRONAS ...
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... ADR Bus Interface 15 4.6. Digital Control Output Pins Bus Interface Bus Interface: Device and Subaddresses 18 5.1. Protocol Description 19 5.2. Proposal for MSP 34x0D I 19 5.2.1. Symbols 19 5.2.2. Write Telegrams 19 5.2.3. Read Telegrams 19 5.2.4. Examples 20 5.3. Start-Up Sequence: Power-Up and I 2 PRELIMINARY DATA SHEET 2 C Telegrams 2 C-Controlling Micronas ...
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... Loudness – Loudspeaker and Headphone Channel 43 7.3.6. Spatial Effects – Loudspeaker Channel 44 7.3.7. Volume – SCART1 and SCART2 Channel 44 7.3.8. Channel Source Modes 45 7.3.9. Channel Matrix Modes 45 7.3.10. SCART Prescale 46 7.3.11. FM/AM Prescale 46 7.3.12. FM Matrix Modes (see also Table 4–1) 46 7.3.13. FM Fixed Deemphasis Micronas hex hex MSP 34x0D 3 ...
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... Outline Dimensions 57 9.2. Pin Connections and Short Descriptions 60 9.3. Pin Configurations 64 9.4. Pin Circuits (pin numbers refer to PLCC68 package) 66 9.5. Electrical Characteristics 66 9.5.1. Absolute Maximum Ratings 67 9.5.2. Recommended Operating Conditions 71 9.5.3. Characteristics 77 10. Application Circuit 79 11. Appendix A: MSP 34x0D Version History 80 12. Data Sheet History 4 PRELIMINARY DATA SHEET Micronas ...
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... MSP 3410B, the MSP 3400B, and the MSP 3400C. To achieve full software-compatibility with these types, the demodulator part must be programmed as described in the data sheet of the MSP 3410B. Micronas MSP 34x0D 1.1. Common Features of MSP 34x0D – AVC: Automatic Volume Correction – ...
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... D/A converters supplying two selectable pairs of SCART outputs. output level per channel: max output resistance: max. 0 S/N-Ratio (20 Hz ... 16 kHz) Loudspeaker OUT Subwoofer OUT Headphones OUT SCART1 OUT SCART2 OUT PRELIMINARY DATA SHEET 2 S bus , , RMS , RMS Micronas ...
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... M-Korea 4.5/4.724212 Satellite 6.5 Satellite 7.02/7.2 Note: NICAM demodulation cannot be done with the MSP 3400D Micronas In the case of NICAM/FM (AM) mode, there are three different audio channels NICAM B, and FM/AM-Mono. NICAM A and B may belong either to a stereo dual-language trans- mission. Information about operation mode and the quality of the NICAM signal can be read by the CCU via the control bus ...
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... B/G L 5.85 MHz 5.85 MHz 728 kbit/s Differentially encoded quadrature phase shift keying (DQPSK) by means of Roll-off filters 1.0 0.4 0.4 5.5 MHz 6.5 MHz AM mono FM mono terrestrial cable PRELIMINARY DATA SHEET D/K 5.85 MHz 0.4 6.5 MHz FM-Mono 13 dB Hungary Poland Micronas ...
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... Type of modulation Modulation depth Modulation frequency MHz SAW Filter Sound IF Tuner Mixer Vision Demo- dulator SCART Inputs Composite Video Fig. 3–1: Typical MSP 34x0D application Micronas Carrier FM1 B/G D kHz kHz 25 kHz mono (L+R)/2 (L+R)/2 language A mono: stereo: 117.5 Hz ...
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... LOUD- D/A SPEAKER L FM2 NICAM A LOUD- D/A SPEAKER R NICAM B SUBWOOFER D/A IDENT DSP D/A HEADPHONE L D/A HEADPHONE R SCARTL D/A SCART1_L SCARTR D/A SCART1_R D/A SCART2_L SCART2_R D/A SCART Switching Facilities PRELIMINARY DATA SHEET XTAL_OUT 2 D_CTR_OUT0/1 DACM_L Loudspeaker DACM_R DACM_SUB Subwoofer DACA_L Headphone DACA_R SC1_OUT_L SCART 1 SC1_OUT_R SC2_OUT_L SCART 2 SC2_OUT_R Micronas ...
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... Phase and AM Dis- Lowpass crimination Differen- tiator Carrier Amplitude Detect AD_CV[9] Carrier Detect Amplitude Phase and AM Dis- Lowpass Differen- crimination tiator Phase FIR2 MSP 34x0D ADR MSP3410D only NICAMA NICAM Decoder NICAMB FM2 Mute Lowpass IDENT Mixer Mute Lowpass FM1/AM MODE_REG[8] 11 ...
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... NICAM mode and bit error rate are sup- plied by the NICAM decoder. It can be read out via the bus. An automatic switching facility (AUTO_FM) between NICAM and FM/AM CCU instructions in case of bad NICAM reception. PRELIMINARY DATA SHEET reduces the amount of Micronas ...
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... V power supply (‘Stand-by’-mode), the switches S1, S2, and S3 (see Fig. 4–3) maintain their position and function. This facilitates the copying from Micronas selected SCART inputs to SCART outputs in the TV set’s stand-by mode. In case of power-on start or starting from stand-by, the IC switches automatically to the default configuration, shown in Fig. 4– ...
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SCARTL SCART Analog Inputs SCARTR Prescale DC level readout FM1 FM/AM FM1/AM Deemphasis Adaptive 50/75 s FM-Matrix Deemphasis J17 Prescale FM2 Demodulated DC level readout FM2 IF Inputs NICAM NICAMA Deemphasis J17 NICAMB Prescale S1L I S1 ...
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... In this case, the system clock is locked to a synchro- nizing signal (I2S_CL, I2S_WS) supplied by the coprocessor chip. Remark on using the crystal: External capacitors at each crystal pin to ground are required (see General Crystal Recommendations on page 69). Micronas MSP Sound IF- FM- Channel- Channel 2 Matrix Select FM1 (5 ...
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... S timing diagram is shown in Fig. 4–6. F I2SWS SONY Mode PHILIPS Mode Detail C L LSB R MSB L LSB R MSB Detail A,B I2S_CL I2S_DA_IN I2S_DA_OUT PRELIMINARY DATA SHEET 2 S serial R LSB L LSB 16 bit right channel R LSB L LSB 16 bit right channel T T I2S1 I2S2 T T I2S3 I2S4 Micronas ...
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... WR_DSP 0001 0010 RD_DSP 0001 0011 Micronas Due to the internal architecture of the MSP 34x0D, the IC cannot react immediately ical response time is about 0.3 ms for the DSP proces- sor part and 1 ms for the demodulator part if NICAM processing is active. If the receiver (MSP) can’t receive another complete byte of data until it has performed some other function ...
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... ACK S read Wait low device address subaddr ACK data byte high PRELIMINARY DATA SHEET 13..1 LSB 0 0 data byte ACK data byte ACK P high low ACK data byte ACK data byte NAK P high low ACK data byte low ACK P Micronas ...
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... Read Telegrams <daw <dar dd dd> read data from demodulator <daw <dar dd dd> read data from DSP 5.2.4. Examples RESET MSP statically < 00> clear RESET < 00> set loudspeaker channel source < 20> to NICAM and matrix to STEREO Micronas 1 f I2C T T I2C4 I2C3 T T I2C6 ...
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... Power-Up Reset: Threshold and Timing (Note: 0.7 DVSUP means 3.5 Volt with DVSUP=5.0 Volt) Fig. 5–3: Power-up sequence 20 2 C-Controlling t/ms High-to-Low Threshold t/ms t/ms PRELIMINARY DATA SHEET Note: The reset should not reach high level be- fore the oscillator has started. This requires a reset delay of >2 ms Micronas ...
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... These data have to be inserted LSB-bound and filled with zero bits into the 16-bit transmission word. Table 4–1 explains how to assign FM carriers to the MSP Sound IF channels and the corresponding matrix modes in the audio processing part. Micronas 2 C bus trans- MSP 34x0D 21 ...
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... NICAM: bit [10:3] of additional data bits NICAM: CIB1 and CIB2 control bits NICAM error rate, updated with 182 ms only to be used in MSPB compatibility mode only to be used in MSPB compatibility mode Not for customer use. Not for customer use. PRELIMINARY DATA SHEET 8 bit offset (total 72 bits) Micronas ...
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... Note: All parameters in the DSP section (Audio Baseband Processing), except the identification mode register, are not affected by the Demodulator Short-Programming. They still have to be defined by the control pro- cessor. Micronas 0020 Internal Setting 2) MODE_ ...
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... NICAM none NICAM or FM/AM, 700 dec depending on ERROR_RATE NICAM or FM/AM, set by depending on customer ERROR_RATE always FM/AM none PRELIMINARY DATA SHEET Comment Compatible to MSP 3410B, i.e. automatic switching is disabled automatic switching with internal threshold automatic switching with external threshold Forced FM-Mono mode, i.e. automatic switching is disabled Micronas ...
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... A/D converter may result. pp Due to the robustness of the internal processing, the IC works up to and even more than FM/NICAM or FM1/FM2 ratio are supposed. In this overflow case, a loss of FM S/N ratio of about 10 dB may appear. Micronas Set by Short-Programming hex Settings AD_CV-FM ...
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... FM/NICAM or FM1/FM2 ratio are supposed. In this overflow case, a loss of FM S/N ratio of about 10 dB may appear. 26 Gain Input Level at pin ANA_IN1+ and ANA_IN2+ 3.00 dB maximum input level 3.85 dB 4.70 dB 5.55 dB 6.40 dB 7.25 dB 8.10 dB 8.95 dB 9.80 dB 10.65 dB 11.50 dB 12.35 dB 13.20 dB 14.05 dB 14.90 dB 15.75 dB 16.60 dB 17.45 dB 18.30 dB 19.15 dB 20.00 dB maximum input level: 0.14 V PRELIMINARY DATA SHEET 1) (FM (NICAM norm conditions pp Micronas ...
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... Mode of MSP Ch1/ ADR Interface [15] AM Gain Gain for AM Demodulation case of NICAM operation slave mode is not possible case slave mode, no synchronization to NICAM is allowed. Micronas hex Definition 0 : strongly recommended 0 : active 1 : tri-state 0 : active 1 : tri-state 0 : Master 2 S bus 1 : Slave 0 : Sony ...
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... IMREG2 4 FM/AM_Coef (5) 5 FM/AM_Coef (4) 6 FM/AM_Coef (3) 7 FM/AM_Coef (2) 8 FM/AM_Coef (1) 9 FM/AM_Coef (0) PRELIMINARY DATA SHEET MSP Ch2 FM1 AM FM1 High-Deviation FM Bits Value see Table 6– Bits Value 8 04 hex 8 40 hex 8 00 hex see Table 6– Micronas ...
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... REG[13] For compatibility, except for the FIR2 AM and the autosearch sets, the FIR filter programming as used for the MSP 3410B is also possible. ADR coefficients are listed in the DRP data sheet. Micronas hex FM Satellite FIR filter corresponds to a band-pass with a band- ...
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... PRELIMINARY DATA SHEET ; DCO2_LO 00A3 , DCO2_HI 00AB hex hex Freq. [MHz] DCO_HI hex hex 5.76 0500 5.85 0514 5.94 0528 6.6 05BA 6.65 05C5 6.8 05E7 7.2 0640 7.56 0690 hex DCO_LO hex 0000 0000 0000 0AAA 0C71 01C7 0000 0000 Micronas ...
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... Note: Similar as for the Demodulator Short-Programming, the Autodetection does not affect most of the para- meters of the DSP section (Audio Baseband Processing): The following exceptions are to be considered: identification mode: Autodetection resets and sets the corresponding identification mode Prescale FM/AM and FM matrix and Deemphasis FM are undefined after Autodetection Micronas Result of Autodetect 007E hex ...
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... A, NICAM B). FM1 carries same channel as NICAM A 1 Data transmission only; no audio x Unimplemented sound coding option (not yet defined by EBU NICAM 728 specification) hex ADD_BITS 0038 LSB hex A[7] A[6] A[5] A[4] A[3] CIB_BITS 003E LSB hex CIB1 CIB2 Micronas ...
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... RESET maximum frequency 0000 0000 Micronas 6.6.9. AGC_GAIN It is possible to read out the actual setting of AGC_GAIN in Automatic Gain Mode. In standard applications, this register is not of interest for the cus- tomer. AGC_GAIN max. amplification (20 dB) min ...
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... PRELIMINARY DATA SHEET Demodulator Short Programming Write into MSP 34x0D: For example: Addr: 0020 , Data 0008 hex Alternatively, for terrestrial reception, the Autodetect feature can be applied. , high part) hex Write into MSP 34x0D: For example: Addr: 0020 , Data: 0003 hex hex hex Micronas ...
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... UK TV sound stan- dard, which is coded with 000A of register 0020 hex Micronas 6.8.3. Multistandard Including System B/G with NICAM/FM-Mono and German DUAL-FM Fig. 6–3 shows a flow diagram for the CCU software, applied for the MSP 3410D set which supports all standards according to system B/G. For the instruc- tions used in the diagram, please refer to Table 6– ...
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... DC Level Readout FM1 (DC Notch On described with the MSP 34x0B, but the above mentioned method is faster. If this DC Level method is applied with the MSP 34x0D recommended to set MODE_REG[15 (AM gain = 12 dB) and to use the new Autosearch FIR2 coefficient set as given in Table 6–11. corresponding Micronas ...
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... Quasi-peak detector matrix Prescale SCART 000D Prescale FM/AM 000E FM matrix Deemphasis FM 000F Adaptive Deemphasis FM Prescale NICAM 0010 Micronas ; if necessary, these registers are readable as well. hex High/ Adjustable Range, Operational Modes Low H [+12 dB ... 114 dB, MUTE] hex L 1/8 dB Steps, Reduce Volume / Tone Control H [0 ...
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... NICAM, SCART, I S1, I hex L [SOUNDA, SOUNDB, STEREO, MONO...] PRELIMINARY DATA SHEET Reset Mode 10 hex 00 hex ] 0/0 B/G 10 hex ON BASS/TREB off hex off 100% /100% linear mode NORMAL 00 hex linear mode 2 S2] FM SOUNDA Micronas ...
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... Quasi-peak readout right 001A DC level readout FM1/Ch2-L 001B DC level readout FM2/Ch1-R 001C MSP hardware version code 001E MSP major revision code MSP product code 001F MSP ROM version code Micronas ; these registers are not writable. hex High/Low Output Range H [80 ... 7F ] hex hex hex H& ...
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... Example: Red. Volume Red. Tone Con. Compromise PRELIMINARY DATA SHEET 0000 [3..0] hex 0006 [3..0] hex 0000 0 hex RESET 0001 1 hex 0010 2 hex Vol.: Bass: Treble 4.5 7.5 5 Micronas ...
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... Left 100 %, Right 100 % 0000 0000 RESET Left 100 %, Right 99.2 % 1111 1111 Left 100 %, Right 0.8 % 1000 0010 Left 100 %, Right muted 1000 0001 Micronas Logarithmic Mode Balance Loudspeaker Channel [L/R] Balance Headphone Channel [L/R] Left 127 dB, Right 0 dB Left 126 dB, Right 0 dB Left 1 dB, Right ...
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... In Super Bass mode, the corner frequency is shifted up. The point of constant volume is shifted from 1 kHz to 2 kHz. 0004 H hex 0033 H hex 0100 0100 44 hex 0100 0000 40 hex 0000 0100 04 hex 0000 0000 00 hex RESET 0004 L hex 0033 L hex 0000 0000 00 hex RESET 0000 0100 04 hex Micronas ...
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... Micronas There are several spatial effect modes available: Mode A (low byte = 00 hex H used spatial effect. Here, the kind of spatial effect depends on the source mode. If the incoming signal is in mono mode, Pseudo Stereo Effect is active; for ste- ...
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... PRELIMINARY DATA SHEET 0008 H hex 0009 H hex 000A H hex 0041 H hex 000B H hex 000C H hex 0000 0000 00 hex RESET 0000 0001 01 hex 0000 0011 03 hex 0000 0100 04 hex 0000 0010 02 hex 0000 0101 05 hex 0000 0110 06 hex Micronas ...
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... If the difference signal on channel B (right) is near to zero, and the sum signal on channel A (left) is high, the incoming audio signal is mono. If there is a significant level on the difference signal, the incoming audio is stereo. Micronas 7.3.10. SCART Prescale L Volume Prescale SCART L ...
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... PRELIMINARY DATA SHEET hex hex 000E L hex 0000 0000 00 hex RESET 0000 0001 01 hex 0000 0010 02 hex 000F H hex 0000 0000 00 hex RESET 0000 0001 01 hex 0000 0100 04 hex 0011 1111 3F hex 000F L hex 0000 0000 00 hex RESET 0011 1111 3F hex Micronas ...
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... ACB Register Definition of Digital Control Output Pins ACB Register 0013 hex D_CTR_OUT0 low (RESET) x0 high x1 D_CTR_OUT1 low (RESET) 0x high 1x Micronas Definition of SCART Switching Facilities (see Fig. 4–3 on page 13) H ACB Register 00 DSP IN hex Selection of Source: * SC1_IN_L/R MONO_IN 20 hex SC2_IN_L/R SC3_IN_L/R 7F hex ...
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... PRELIMINARY DATA SHEET 0017 L hex 0000 0000 00 hex Reset 0011 1111 3F hex 0020 H hex 0000 0000 00 hex RESET 1111 1111 FF hex 0029 [15...12] hex 0000 0 hex RESET 1000 8 hex 0029 [11...8] hex 1000 8 hex 0100 4 hex 0010 2 hex 0001 1 hex Micronas ...
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... Note: AVC should not be used in any Dolby Pro Logic mode, except PANORAMA, where no other than the loudspeaker output is active. Micronas 7.3.24. Subwoofer Channel The subwoofer channel is created by combining the left and right channels directly behind the tone control filter block ...
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... These registers are not writable. 7.6.1. Stereo Detection Register Stereo Detection Register Stereo Mode MONO STEREO BILINGUAL Loudspeaker Headphone SCART2 SCART1 SCART1…2 0018 H hex Reading (two’s complement) near zero positive value (ideal reception hex negative value (ideal reception: 80 hex) Micronas ...
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... A change in the hardware version code defines hard- ware optimizations that may have influence on the chip’s behavior. The readout of this register is identical to the hardware version code in the chip’s imprint. Micronas 7.6.5. MSP Major Revision Code H+L Major Revision MSP 34x0D H+L The MSP 34x0D is the fourth generation of ICs in the ] MSP family ...
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... No 1: ADR/SaRa 1: ADR/SaRa MSP 3410D B4 Yes No No I2S_DA_IN2 ADR_CL, ADR_WS, ADR_DA Yes Yes Yes Yes not used not used 0: active 1: tri-state 0: active 1: tri-state NICAM no function no function no function off 0: use FIR1 1: use FIR2 0: normal mode 1: ADR/SaRa Micronas ...
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... Band Equalizer (DSP W Addr. 0021 0025 ) hex hex Balance Headphone channel (DSP W Addr. 0030 hex 1) This feature will be implemented in MSP 3400C from version C7 on. Micronas MSP 3400C MSP 3400D Not necessary Not necessary hex ...
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... No Yes No Yes No Yes No Yes 1) Yes Yes ) hex No Yes No Yes PRELIMINARY DATA SHEET MSP 3410B F7 MSP 3410D B4 No Yes [+20 ... 12 dB] No Yes [+15 ... 12 dB] No Yes normal hex 04 : Super hex Bass No Yes No Yes No Yes No Yes No Yes No Yes No Yes No Yes Micronas ...
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... Weight approximately 4.8 g Dimensions ±0.1 57.7 ±0.1 1 0.457 ±0.05 1.778 ±0.1 1. 1.778 = 55.118 Fig. 9–2: 64-Pin Plastic Shrink Dual Inline Package (PSDIP64) Weight approximately 9.0 g Dimensions in mm Micronas x 45 ° 1 1.9 4.05 0.1 ±0.15 4.75 SPGS0016-4/ ±0.1 19.3 ±0.1 18 ±0.1 47 ±0.06 0.27 ±0.5 20.1 ± ...
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... Fig. 9–4: 80-Pin Plastic Quad Flat Pack (PQFP80) Weight approximately 1.61 g Dimensions 1.75 12 1.5 Fig. 9–5: 64-Pin Plastic Low-Profile Quad Flat Pack (PLQFP64) Weight approximately 0.35 g Dimensions 0.8 ±0.03 0.17 1.8 1.28 2.70 0.1 ±0 0.5 = 7.5 0.5 0.145 1.4 10 0.1 D0025/2E PRELIMINARY DATA SHEET 23 x 0 SPGS0025-1/1E Micronas ...
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... Micronas Pin Name Type Connection (if not used) ADR_WS OUT ADR_DA OUT LV I2S_DA_IN1 IN LV I2S_DA_OUT OUT LV I2S_WS IN/OUT LV I2S_CL IN/OUT LV I2C_DA IN/OUT X I2C_CL IN/OUT X NC ...
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... SCART 3 input, right SCART 3 input, left Analog Shield Ground 4 SCART 4 input, right SCART 4 input, left Not connected Analog reference voltage Analog ground Analog ground Not connected Not connected Volume capacitor MAIN Analog power supply 8V Volume capacitor AUX SCART 1 output, left Micronas ...
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... Due to compatibility with MSP 3410D-B4 and older versions possible to connect with ground as well. Micronas Pin Name Type Connection (if not used) SC1_OUT_R OUT LV VREF1 X SC2_OUT_L OUT LV SC2_OUT_R OUT ...
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... SC2_IN_R SC2_IN_L SC3_IN_R ASG2 Fig. 9–6: 68-pin PLCC package 60 DVSUP DVSS I2S_DA_IN2 RESETQ 60 DACA_R 59 DACA_L 58 VREF2 57 DACM_R 56 DACM_L DACM_SUB SC2_OUT_R 50 SC2_OUT_L 49 VREF1 48 SC1_OUT_R 47 SC1_OUT_L 46 CAPL_A 45 AHVSUP 44 CAPL_M AHVSS AGNDC NC SC4_IN_L SC4_IN_R ASG4 SC3_IN_L PRELIMINARY DATA SHEET Micronas ...
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... VREF2 27 38 CAPL_A DACM_R 28 37 SC1_OUT_L DACM_L 29 36 SC1_OUT_R VREF1 DACM_SUB 31 34 SC2_OUT_L SC2_OUT_R Fig. 9–7: 64-pin PSDIP package Micronas MSP 34x0D XTAL_OUT AUD_CL_OUT 2 51 XTAL_IN D_CTR_OUT1 3 50 TESTEN D_CTR_OUT0 4 49 ANA_IN2+ ADR_SEL 5 48 ANA_IN STANDBYQ 6 47 ANA_IN1+ ...
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... Fig. 9–9: 80-pin PQFP package 62 ASG2 SC3_IN_R SC3_IN_L ASG4 SC4_IN_R SC4_IN_L NC AGNDC AHVSS AHVSS CAPL_M 39 AHVSUP 38 CAPL_A 37 SC1_OUT_L 36 SC1_OUT_R 35 VREF1 34 SC2_OUT_L 33 SC2_OUT_R 32 ASG3 DACM_SUB DACM_L 27 DACM_R 26 VREF2 25 DACA_L DACA_R NC NC RESETQ I2S_DA_IN2 DVSS DVSS DVSS DVSUP PRELIMINARY DATA SHEET Micronas ...
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... STANDBYQ I2C_CL I2C_DA I2S_CL I2S_WS I2S_DA_OUT I2S_DA_IN1 ADR_DA DVSUP ADR_WS ADR_CL Fig. 9–10: 64-pin PLQFP package Micronas SC3_IN_L ASG4 SC4_IN_R SC4_IN_L AGNDC AHVSS 32 CAPL_M 31 AHVSUP 30 CAPL_A 29 SC1_OUT_L 28 SC1_OUT_R 27 VREF1 26 SC2_OUT_L 25 SC2_OUT_R 24 NC ...
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... Fig. 9–15: Output/Input Pins 18, 20, and 21 (AUD_CL_OUT, XTALIN/OUT) ANAIN1+ ANAIN2+ ANAIN VREFTOP Fig. 9–16: Input Pins 23-25, and 29 (ANA_IN2+, ANA_IN-, ANA_IN1+, VREFTOP) 0...2 V Fig. 9–17: Capacitor Pins 44 and 46 (CAPL_M, CAPL_A 3.75 V Fig. 9–18: Input Pin 28 (MONO_IN) 2 Micronas ...
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... V Fig. 9–19: Input Pins 30, 31, 33, 34, 36, 37, 40, and 41 (SC1-4_IN_L/R) AHVSUP 0...1.2 mA 3.3 k Fig. 9–20: Output Pins 56, 57, 59, 60, and 54 (DACA_L/R, DACM_L/R, DACM_SUB) 125 k 3.75 V Fig. 9–21: Pin 42 (AGNDC 120 k 300 3.75 V Fig. 9–22: Output Pins 47, 48, 50, and 51 (SC_1/2_OUT_L/R) Micronas MSP 34x0D 65 ...
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... AHVSUP 0.3 9.0 DVSUP 0.3 6.0 AVSUP 0.3 6.0 AVSUP, 0.5 0.5 DVSUP 1200 1300 1200 1000 1) 960 0.3 V SUP2 20 +20 3) SCn_IN_s, 0.3 V SUP1 MONO_IN 3) SCn_IN_s MONO_IN SCn_OUT_s , , DACp_s CAPL_p, AGNDC “p” means “M” or “A” Unit +0 +0 Micronas ...
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... C START Condition Setup Time I2C1 STOP Condition Setup Time I2C2 C-Clock Low Pulse Time I2C3 C-Clock High Pulse Time I2C4 C-BUS Frequency I2C Micronas MSP 34x0D Pin Name Min. Typ. AHVSUP 7.6 8.0 DVSUP 4.75 5.0 AVSUP 4.75 5.0 RESETQ 0.7 0.45 ADR_SEL 0.8 STANDBYQ 0.8 0.5 ...
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... S-Word Strobe Input Hold Time I2SWS2 after Falling Edge of Clock when 2 MSP in I S-Slave-Mode 68 PRELIMINARY DATA SHEET Pin Name Min. Typ. I2S_DA_IN1/2 0.75 0.5 I2S_DA_IN1/2, 20 I2S_CL 0 I2S_CL 1.024 0.9 I2S_WS 32.0 I2S_CL, I2S_WS 0.75 0 Max. Unit 0.25 V SUP2 0.2 V SUP2 V SUP2 V SUP2 ns ns MHz 1.1 kHz 0.25 V SUP2 0.2 V SUP2 V SUP2 V SUP2 ns ns Micronas ...
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... To define the capacitor size, reset the MSP without transmitting any further I quency at AUD_CL_OUT-pin. Change the capacitor size until the free running frequency matches 18.432 MHz as closely as possible.The higher the capacity, the lower the resulting clock frequency. Micronas Pin Name Min. 1) ...
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... SCn_OUT_s 10 CAPL_M, 10 CAPL_A DACM_s, 10 DACA_s VREFTOP 20% 10 20% 100 0 0.1 0.8 0.1 0.45 BG ANA_IN1+, 7 ANA_IN2+, ANA_IN Max. Unit F nF +20% nF 2.0 V RMS 2.0 V RMS k 6 +10 MHz 0 192 kHz 360 Micronas ...
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... S-Output High Voltage I2SOH S-Clock Output Frequency I2SCL S-Word Strobe Output Frequency I2SWS S-Clock High/Low-Ratio I2S1/I2S2 Micronas = 7 4.75 to 5.25 V for min./max. values SUP1 SUP2 = for typical values, T SUP1 SUP2 Pin Name Min. Typ. Max. XTAL_IN 18.432 ...
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... load AGNDC kHz 0.05 mA signal kHz 0.1 mA signal kHz RMS signal kHz 0.1 mA signal kHz signal dB with respect to 1 kHz kHz RMS signal Micronas ...
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... DSP to SCART Output from DSP to Main or AUX Output 1) “n” means “1”, “2”, “3”, or “4”; “s” means “L” or “R” DSP measured at I S-Output 3) 2 DSP Input at I S-Input Micronas Pin Name Min. Typ. Max. 1 DACp_s ) 2.1 3.3 4.6 2.1 5.0 1 ...
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... Hz...20 kHz) same signal source on left and right disturbing chan- nel, effect on each observed output channel dB SCART output load resis- dB tance SCART output load resis- dB tance Micronas ...
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... THD Total Harmonic Distortion + Noise demodulated signal on Main/ AUX/SCART output 1) “n” means “1”, “2”, “3”, or “4”; “s” means “L” or “R”; SPM: Short Programming Mode Micronas Pin Name Min. Typ. Max. AGNDC 80 MONO_IN, 70 ...
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... FM-carrier kHz, 40 kHz deviation; RMS dB 2.12 kHz, Modulator input level = 0 dBref dB 1 FM-carrier 5.5 MHz Modulator input level = 14.6 dBref; RMS dB Modulator input level = 12 dB dBref; RMS dB 2 FM-carriers 5.5/5.74 MHz kHz, 40 kHz deviation; RMS FM-carriers 5.5/5.74 MHz kHz, 40 kHz deviation; RMS dB Micronas ...
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... DVSS 12 (6) ADR_SEL DVSS 8 (10) I2C_DA 9 (9) I2C_CL 1 (16) ADR_WS 68 (17) ADR_CL 3 (15) ADR_DA 6 (12) I2S_WS 7 (11) I2S_CL 4 (14) I2S_DA_IN1 65 (20) I2S_DA_IN2 5 (13) I2S_DA_OUT ResetQ (from CCU, see section 5.3. ) Micronas if ANA_IN2+ not used C see section 9.5.2. 10 100 +8 3.3 100 ...
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... DVSUP and DVSS pins. The ASG pins should be connected as closely as pos- sible to the MSP to ground. If they are lead with the SCART input lines as shielding line, they should NOT be connected to ground at the SCART connector. 78 PRELIMINARY DATA SHEET Micronas ...
Page 79
... PLQFP64 – digital input specification changed as of version C5 and later (see section 9.5. on page 66) – max. analog high supply voltage AHVSUP 8.7 V – supply currents changed as of version C5 and later (see section 9.5.3. on page 71) – Pin ASG3 no longer supported Micronas MSP 34x0D 79 ...
Page 80
... By this publication, Micronas GmbH does not assume responsibil- ity for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. ...
Page 81
... The MSP-family (MSP 3410D, MSP 3400D, MSP 3415D, MSP 3405D, MSP 3417D, MSP 3407D) is currently avail- able in different technologies (0.8 µ, 0.5 µ, and 0.45 µ). The specific differences of the various implementations are listed in the attached table. Micronas Preliminary Data Sheet Supplement Compatibility Differences ...
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... Micronas Compatibility Differences between 0.5/0.45µ and 0.8µ MSPD Devices MSP-Type Version Code Technology Mask Iteration Code Feature Documented in Datasheet Reference General Hardware Power Consumption Datasheet Total Electromagnetic Radiation (EMR) V typical Datasheet AGNDC0 DC typical Datasheet VREFTOP Maximum V Datasheet sup1 Digital Input Pin characteristics ...
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... Micronas MSP-Type Version Code Technology Mask Iteration Code Feature Documented in D/A-Outputs S/N-ratio Pinning SCART2_Out pin Datasheet DAC-Headphone pins Datasheet Audio_Clock_Out Datasheet The following pins refer to PQFP80: Pin 52 Datasheet Pin 32 Datasheet Pin 14 Datasheet Pin 16 Datasheet *1) In spite of increased DC-level controller-algorithms for automatic Sat-Carrier detection should run properly Date: 11 ...