W83194R-67A Winbond, W83194R-67A Datasheet
W83194R-67A
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W83194R-67A Summary of contents
Page 1
... CPU/PCI frequencies which are externally selectable with smooth transitions. W83194R-67AA also provides 13 SDRAM clocks controlled by the none-delay buffer_in pin. The W83194R-67A accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply. Spread spectrum built in at ¡Ó 0.5% or ¡Ó 0.25% to reduce EMI. Programmable stopping individual clock outputs and frequency selection through I stabilization, which requires CPU and PCI clocks be stable within 2 ms after power-up ...
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... Vss Vss W83194R-67A PRELIMINARY 48MHz 24MHz REF(0:1) 2 CPUCLK_F CPUCLK(0:2) 3 SDRAM_F SDRAM(0:11) 12 PCICLK(0:4) 5 PCICLK_F REF1/ *FS2 VddL1 CPUCLK_F CPUCLK0 Vss CPUCLK1 CPUCLK2 *CPU_STOP# Vss SDRAM_F SDRAM 0 SDRAM 1 Vddq3 SDRAM 2 ...
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... Latched input for FS3 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. OUT Low skew (< 250ps) PCI clock outputs. Synchronous to CPU clocks with 1/-4ns skew(CPU early Inputs to fanout for SDRAM outputs W83194R-67A PRELIMINARY FUNCTION FUNCTION Publication Release Date: Feb. 1999 Revision 0.30 ...
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... Power supply for CPU clock outputs, either 2.5V or 3.3V Power supply for PCICLK_F, PCICLK[1:4], 3.3V. Power supply for SDRAM_F,SDRAM[0:11], and PLL core, nominal 3.3V. 27 Power for 24 & 48MHz output buffers and PLL core W83194R-67A PRELIMINARY FUNCTION 2 C 2-wire control interface with internal 2 C 2-wire control interface with FUNCTION FUNCTION Publication Release Date: Feb ...
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... W83194R-67A PRELIMINARY REF,IOAPIC (MHz) 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 PIN 2 PCI_STOP# (Input) REF0 (Output) Publication Release Date: Feb ...
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... The W83194R-67A may be disabled in the low state according to the following table in order to reduce power consumption. All clocks are stopped in the low state, but maintain a valid high period on transitions from running to stop ...
Page 7
... SSEL0 (for frequency table selection by software via Selection by hardware 1 = Selection by software I SSEL3 (for frequency table selection by software via Normal 1 = Spread Spectrum enabled 0 = Running 1 = Tristate all outputs - 7 - W83194R-67A PRELIMINARY Byte0,1,2... Ack until Stop Byte2, 3, 4... Ack until Stop byte must be sent following the ...
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... Description Latched FS2# Reserved Reserved Reserved CPUCLK2 (Active / Inactive) CPUCLK1 (Active / Inactive) CPUCLK0 (Active / Inactive) CPUCLK_F (Active / Inactive W83194R-67A PRELIMINARY REF,IOAPIC (MHz) 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14 ...
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... Reserved - Latched FS0# 48MHz (Active / Inactive) 24MHz (Active / Inactive) SDRAM_F(Active / Inactive) SDRAM(8:11) (Active / Inactive) SDRAM(4:7) (Active / Inactive) SDRAM(0:3) (Active / Inactive) Reserved Reserved Reserved Reserved Latched FS1# Reserved Latched FS3# Reserved - 9 - W83194R-67A PRELIMINARY Description Description Description Publication Release Date: Feb. 1999 Revision 0.30 ...
Page 10
... Latched Frequency Selects(FS#) will be inverted logic load of the input frequency select pin conditions. Description Reserved Reserved Reserved Reserved Reserved Reserved REF1 (Active / Inactive) REF0 (Active / Inactive) Description Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip W83194R-67A PRELIMINARY Publication Release Date: Feb. 1999 Revision 0.30 ...
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... CCJ 500 500 J 0.4 1.6 t TLH t THL V 1.5 over V 2.1 RBE - 11 - W83194R-67A PRELIMINARY Rating - 0 7 150 125 + Units Test Conditions % Measured at 1. Load Measured at 1. Load Measured at 1. KHz Load on CPU and PCI ...
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... Ioz 10 I dd3 I dd2 CPUS3 CPUS2 I PD3 - 12 - W83194R-67A PRELIMINARY = + Units Test Conditions All outputs V dc All outputs using 3.3V power CPU = 66.6 MHz PCI = 33.3 Mhz with load mA Same as above mA ...
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... Typ Max -29 OH(min) -23 29 OL(min) OL(max) 1.0 RF(min) 4.0 RF(max) Min Typ Max OH(min) -46 OL(min) 53 OL(max) 0.5 RF(min) 1.3 RF(max W83194R-67A PRELIMINARY Units Test Conditions mA Vout = 1 Vout = 2.0V mA Vout = 1 Vout = 0 10pF Load ns 20pF Load Units Test Conditions mA Vout = 1 Vout = 3.135V mA Vout = 1. Vout = 0 ...
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... Rise/Fall Time Min T Between 0.8 V and 2.0 V Rise/Fall Time Max T Between 0.8 V and 2.0 V Min Typ Max -33 OH(min) -33 30 OL(min) 38 OL(max) 0.5 RF(min) 2.0 RF(max W83194R-67A PRELIMINARY Units Test Conditions mA Vout = 1 Vout = 3.135 V mA Vout = 1. Vout = 0 15pF Load ns 30pF Load Publication Release Date: Feb. 1999 Revision 0.30 ...
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... PCI clocks are stopped. The PCI clocks will always be stopped in a low state and resume output with full pulse width. In this case, PCI “c locks on latency “ is less than 2 PCI clocks and “c locks off latency ” is less then 2 PCI clocks W83194R-67A PRELIMINARY Publication Release Date: Feb. 1999 Revision 0.30 ...
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... Vdd Pad Device Vdd Series 10k Terminating Resistor 10k Ground Programming Header Ground Pad Series 10k Terminating Resistor Pin - 16 - W83194R-67A PRELIMINARY Clock Trace EMI Reducing Cap Optional Ground Clock Trace EMI Reducing Cap Optional Ground Publication Release Date: Feb. 1999 Revision 0.30 ...
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... W83194R-67A 13.0 HOW TO READ THE TOP MARKING W83194R-67A 28051234 814GBB 1st line: Winbond logo and the type number: W83194R-67A 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 814 814: packages made in '98, week 14 G: assembly house ID ...
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... Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064 Publication Release Date: Feb. 1999 - 18 - W83194R-67A PRELIMINARY Winbond Electronics (North America) Corp. 2730 Orchard Parkway San Jose, CA 95134 U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668 ...