LM4832MT/NOPB National Semiconductor, LM4832MT/NOPB Datasheet - Page 16

• Manufacturer Part Number: LM4832MT/NOPB
• Description: IC AMP AUDIO PWR .25W AB 28TSSOP
• Manufacturer: National Semiconductor
• Series: Boomer®r
• Type: Class ABr

Specifications of LM4832MT/NOPB

• Output Type: 2-Channel (Stereo)
• Max Output Power X Channels @ Load: 250mW x 2 @ 8 Ohm
• Voltage - Supply: 4.5 V ~ 5.5 V
• Features: 3D, Depop, I²C, Microphone, Mute, Shutdown, Tone and Volume Control
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP
• Operational Class: Class-AB
• Audio Amplifier Output Configuration: 1-Channel Mono/2-Channel Stereo
• Output Power (typ): 0.25x2@8OhmW
• Audio Amplifier Function: Microphone/Speaker
• Total Harmonic Distortion: 0.15@8Ohm@200mW%
• Single Supply Voltage (typ): 5V
• Dual Supply Voltage (typ): Not RequiredV
• Power Supply Requirement: Single
• Rail/rail I/o Type: No
• Power Supply Rejection Ratio: 45dB
• Single Supply Voltage (min): 4.5V
• Single Supply Voltage (max): 5.5V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Package Type: TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *LM4832MT; LM4832MT

www.national.com
Application Information
I
The LM4832 uses a serial bus, which conforms to the I
protocol, to control the chip’s functions with two wires: clock
and data. The clock line is uni-directional. The data line is
bi-directional(open-collector) with a pullup resistor (typically
10 kΩ).The maximum clock frequency specified by the I
standard is 400 kHz. In this discussion, the master is the
controlling microcontroller and the slave is the LM4832.
The I
Address Bit 1 and Address Bit 2 TTL/CMOS inputs on the
chip. The LM4832’s four possible I
the form 10000X
determined by the voltage levels at the Address Bit 2 and
Address Bit 1 pins, respectively. If the I
address a number of chips in a system and the LM4832’s
chip address can be changed to avoid address conflicts.
The timing diagram for the I
is latched in on the stable high level of the clock and the data
line should be held high when not in use. The timing diagram
is broken up into six major sections:
The “start” signal is generated by lowering the data signal
while the clock signal is high. The start signal will alert all
devices attached to the I
dress against their own chip address.
The 8-bit chip address is sent next, most significant bit first.
Each address bit must be stable while the clock level is high.
After the last bit of the address is sent, the master checks for
the LM4832’s acknowledge. The master releases the data
line high (through a pullup resistor). Then the master sends
a clock pulse. If the LM4832 has received the address
correctly, then it holds the data line low during the clock
pulse. If the data line is not low, then the master should send
a “stop” signal (discussed later) and abort the transfer.
The 8 bits of data are sent next, most significant bit first.
Each data bit should be valid while the clock level is stable
high.
After the data byte is sent, the master must generate another
acknowledge to see if the LM4832 received the data.
If the master has more data bytes to send to the LM4832,
then the master can repeat the previous two steps until all
data bytes have been sent.
The “stop” signal ends the transfer. To signal “stop”, the data
signal goes high while the clock signal is high.
3D AUDIO ENHANCEMENT
The LM4832 has a 3D audio enhancement effect that helps
improve the apparent stereo channel separation when, be-
cause of cabinet or equipment limitations, the left and right
speakers are closer to each other than optimal.
An external RC network, shown in Figure 3, is required to
enable the effect. The amount of the effect is set by the 20
2
C INTERFACE
2
C address for the LM4832 is determined using the
2
X
1
0 (binary), where the X
2
C bus to check the incoming ad-
2
C is shown in Figure 2. The data
2
C chip addresses are of
2
C interface is used to
(Continued)
2
and X
1
bits are
2
2
C
C
16
kΩ resistor. A 0.1 µF capacitor is used to reduce the effect at
frequencies below 80 Hz. Decreasing the resistor size will
make the 3D effect more pronounced and decreasing the
capacitor size will raise the cutoff frequency for the effect.
The 680 kΩ resistor across the 0.1 µF capacitor reduces
switching noise by discharging the capacitor when the effect
is not in use.
TONE CONTROL RESPONSE
Bass and treble tone controls are included in the LM4832.
The tone controls use two external capacitors for each ste-
reo channel. Each has a corner frequency determined by the
value of C2 and C3 (see Figure 4) and internal resistors in
the feedback loop of the internal tone amplifier.
Typically, C2 = C3 and for 100 Hz and 10 kHz corner
frequencies, C2 = C3 = 0.0082 µF. Altering the ratio between
C2 and C3, changes the midrange gain. For example, if C2
= 2(C3), then the frequency response will be flat at 20 Hz
and 20 kHz, but will have a 6 dB peak at 1 kHz.
With C = C2 = C3, the treble turn-over frequency is nominally
and the bass turn-over frequency is nominally
when maximum boost is chosen. The inflection points (the
frequencies where the boost or cut is within 3 dB of the final
value) are, for treble and bass respectively,
Increasing the values of C2 and C3 decreases the turnover
and inflection frequencies: i.e., the Tone Control Response
Curves shown in Typical Performance Section will shift left
when C2 and C3 are increased and shift right when C2 and
C3 are decreased. With C2 = C3 = 0.0082 µF, 2 dB steps are
achieved at 100 Hz and 10 kHz. Changing C2 and C3 to
0.01 µF shifts the 2 dB step frequency to 72 Hz and 8.3
kHz.If the tone control capacitors’ size is decreased these
frequencies will increase.With C2 = C3 = 0.0068 µF the 2 dB
steps take place at 130 Hz and 11.2 kHz.
FIGURE 5. 3D Effect Components
f
f
BT
BI
f
f
TT
TI
= 1/(2πC(169.6 kΩ))
= 1/(2πC(30.4 kΩ)),
= 1/(2πC(1.9 kΩ))
= 1/(2πC(14 kΩ))
10001428