DS90CF384AMTDX National Semiconductor, DS90CF384AMTDX Datasheet

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DS90CF384AMTDX

Manufacturer Part Number
DS90CF384AMTDX
Description
+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHz
Manufacturer
National Semiconductor
Datasheet

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© 1999 National Semiconductor Corporation
DS90CF384A/DS90CF364A
+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD)
Link— 65 MHz, +3.3V LVDS Receiver 18-Bit Flat Panel
Display (FPD) Link— 65 MHz
General Description
The DS90CF384A receiver converts the four LVDS data
streams (Up to 1.8 Gbps throughput or 227 Megabytes/sec
bandwidth) back into parallel 28 bits of CMOS/TTL data (24
bits of RGB and 4 bits of Hsync, Vsync, DE and CNTL). Also
available is the DS90CF364A that converts the three LVDS
data streams (Up to 1.3 Gbps throughput or 170 Megabytes/
sec bandwidth) back into parallel 21 bits of CMOS/TTL data
(18 bits of RGB and 3 bits of Hsync, Vsync and DE). Both
Receivers’ outputs are Falling edge strobe. A Rising edge or
Falling edge strobe transmitter (DS90C383A/DS90C363A)
will interoperate with a Falling edge strobe Receiver without
any translation logic.
This chipset is an ideal means to solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
Block Diagrams
TRI-STATE
®
is a registered trademark of National Semiconductor Corporation.
See NS Package Number MTD56
Order Number DS90CF384AMTD
DS90CF384A
DS100870
DS100870-27
Features
n 20 to 65 MHz shift clock support
n 50% duty cycle on receiver output clock
n Best–in–Class Set & Hold Times on RxOUTPUTs
n Rx power consumption
n Rx Power-down mode
n ESD rating
n Supports VGA, SVGA, XGA and Dual Pixel SXGA.
n PLL requires no external components
n Compatible with TIA/EIA-644 LVDS standard
n Low profile 56-lead or 48-lead TSSOP package
Grayscale
See NS Package Number MTD48
Order Number DS90CF364AMTD
>
7 kV (HBM),
DS90CF364A
<
<
200µW (max)
142 mW (typ)
>
700V (EIAJ)
@
65MHz
October 1999
www.national.com
DS100870-28

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DS90CF384AMTDX Summary of contents

Page 1

... Block Diagrams DS90CF384A Order Number DS90CF384AMTD See NS Package Number MTD56 TRI-STATE ® registered trademark of National Semiconductor Corporation. © 1999 National Semiconductor Corporation DS100870 Features MHz shift clock support n 50% duty cycle on receiver output clock n Best–in–Class Set & Hold Times on RxOUTPUTs < ...

Page 2

... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( CMOS/TTL Input Voltage CMOS/TTL Output Voltage LVDS Receiver Input Voltage Junction Temperature Storage Temperature Lead Temperature (Soldering, 4 sec) ...

Page 3

Electrical Characteristics Note 2: Typical values are given for V = 3.3V and T CC Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless ...

Page 4

AC Timing Diagrams (Continued) FIGURE 2. “16 Grayscale” Test Pattern (DS90CF384A)(Notes www.national.com DS100870-12 4 ...

Page 5

AC Timing Diagrams (Continued) FIGURE 3. “16 Grayscale” Test Pattern (DS90CF364A)(Notes Note 5: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O. Note 6: The 16 grayscale test ...

Page 6

AC Timing Diagrams (Continued) FIGURE 6. DS90CF384A/DS90CF364A (Receiver) Clock In to Clock Out Delay FIGURE 7. DS90CF384A/DS90CF364A (Receiver) Phase Lock Loop Set Time FIGURE 8. 28 Parallel TTL Data Inputs Mapped to LVDS Outputs - DS90CF384A www.national.com DS100870-6 DS100870-7 6 ...

Page 7

AC Timing Diagrams (Continued) FIGURE 9. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs - DS90CF364A FIGURE 10. DS90CF384A/DS90CF364A (Receiver) Power Down Delay DS100870-8 7 DS100870-10 www.national.com ...

Page 8

AC Timing Diagrams (Continued) FIGURE 11. DS90CF384A (Receiver) LVDS Input Strobe Position www.national.com 8 DS100870-25 ...

Page 9

AC Timing Diagrams (Continued) FIGURE 12. DS90CF364A (Receiver) LVDS Input Strobe Position 9 DS100870-26 www.national.com ...

Page 10

AC Timing Diagrams (Continued) C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max Tppos — Transmitter output pulse position (min and max) RSKM = Cable Skew (type, length) + ...

Page 11

DS90CF384A Pin Description — 24-Bit FPD Link Receiver Pin Name I/O No. RxIN RxIN− RxOUT O 28 RxCLK IN RxCLK IN− RxCLK OUT O 1 PWR DOWN ...

Page 12

Pin Diagram DS90CF384A www.national.com DS90CF364A DS100870-23 12 DS100870-13 ...

Page 13

Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Molded Thin Shrink Small Outline Package, JEDEC Order Number DS90CF384AMTD NS Package Number MTD56 13 www.national.com ...

Page 14

... NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant ...

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