DS90CR218MTD National Semiconductor, DS90CR218MTD Datasheet
DS90CR218MTD
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DS90CR218MTD Summary of contents
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... Up to 197 Megabytes/sec bandwidth n 345 mV (typ) swing LVDS devices for low EMI n PLL requires no external components n Rising edge data strobe n Compatible with TIA/EIA-644 LVDS standard n Low profile 48-lead TSSOP package DS90CR218 DS100871-1 Order Number DS90CR218MTD See NS Package Number MTD48 November 1999 DS100871-27 www.national.com ...
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Pin Diagrams DS90CR217 Typical Application www.national.com DS100871-21 DS90CR218 2 DS100871-22 DS100871-23 ...
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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( CMOS/TTL Input Voltage −0. CMOS/TTL Output Voltage −0. LVDS Receiver Input Voltage −0. LVDS Driver Output Voltage − ...
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Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter TRANSMITTER SUPPLY CURRENT I Transmitter Supply Current CCTZ Power Down RECEIVER SUPPLY CURRENT I Receiver Supply Current Worst CCRW Case I Receiver Supply Current Power CCRZ ...
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Receiver Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Symbol CLHT CMOS/TTL Low-to-High Transition Time ( Figure 3 ) CMOS/TTL High-to-Low Transition Time ( Figure 3 ) CHLT RSPos0 Receiver Input Strobe Position for Bit 0 ...
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AC Timing Diagrams (Continued) DS100871-5 FIGURE 3. DS90CR218 (Receiver) CMOS/TTL Output Load and Transition Times FIGURE 4. D590CR217 (Transmitter) Input Clock Transition Time Note 7: Measurements DIFF Note 8: TCCS measured between earliest and latest LVDS ...
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AC Timing Diagrams (Continued) FIGURE 7. DS90CR218 (Receiver) Setup/Hold and High/Low Times FIGURE 8. DS90CR217 (Transmitter) Clock In to Clock Out Delay FIGURE 9. DS90CR218 (Receiver) Clock In to Clock Out Delay FIGURE 10. DS90CR217 (Transmitter) Phase Lock Loop Set ...
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AC Timing Diagrams (Continued) FIGURE 11. DS9OCR218 (Receiver) Phase Lock Loop Set Time FIGURE 12. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs (DS90CR217) www.national.com FIGURE 13. Transmitter Powerdown Delay 8 DS100871-14 DS100871-16 DS100871-17 ...
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AC Timing Diagrams (Continued) FIGURE 14. Receiver Powerdown Delay FIGURE 15. Transmitter LVDS Output Pulse Position Measurement DS100871-18 9 DS100871-19 www.national.com ...
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AC Timing Diagrams (Continued) FIGURE 16. Receiver LVDS Input Strobe Position www.national.com 10 DS100871-28 ...
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AC Timing Diagrams (Continued) C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max Tppos — Transmitter output pulse position (min and max) RSKM Cable Skew (type, length) + Source ...
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Applications Information DS90CR218 Pin Description — Channel Link Receiver Pin Name I/O No. PWR DWN I 1 TTL level input. When asserted (low input) the receiver outputs are low Power supply pins for TTL outputs. CC GND ...
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Applications Information (Continued) characteristic impedance (90 to 120 typical) of the cable. Figure 18 shows an example. No additional pull-up or pull- down resistors are necessary as with some other differential technologies such as PECL. Surface mount resistors are FIGURE ...
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Applications Information FIGURE 20. Single-Ended and Differential Waveforms www.national.com (Continued) 14 DS100871-26 ...
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... Physical Dimensions inches (millimeters) unless otherwise noted Order Number DS90CR217MTD or DS90CR218MTD LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1 ...