TE28F640J3C-150

Manufacturer Part NumberTE28F640J3C-150
DescriptionTE28F640J3C-150Intel StrataFlash Memory (J3)
ManufacturerIntel Corporation
TE28F640J3C-150 datasheet
 
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256-Mbit J3 (x8/x16)
Table 14. Command Bus-Cycle Definitions (Sheet 2 of 2)
Scalable or
Basic
Command
Command
(2)
Set
Clear Block Lock-Bits
SCS
Protection Program
NOTES:
1. Commands other than those shown above are reserved by Intel for future device implementations and should not be used.
2. The Basic Command Set (BCS) is the same as the 28F008SA Command Set or Intel Standard Command Set. The Scalable
Command Set (SCS) is also referred to as the Intel Extended Command Set.
3. Bus operations are defined in
Table
4. X = Any valid address within the device.
BA = Address within the block.
IA = Identifier Code Address: see
Table
QA = Query database Address.
PA = Address of memory location to be programmed.
RCD = Data to be written to the read configuration register. This data is presented to the device on A[16:1]; all other address
inputs are ignored.
5. ID = Data read from Identifier Codes.
QD = Data read from Query database.
SRD = Data read from Status Register. See
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE#.
CC = Configuration Code.
6. The upper byte of the data bus (D[15:8]) during command writes is a “Don’t Care” in x16 operation.
7. Following the Read Identifier Codes command, read operations access manufacturer, device and block lock codes. See
Section 10.2
for read identifier code data.
8. If the WSM is running, only D7 is valid; D[15:8] and D[6:0] float, which places them in a high-impedance state.
9. After the Write to Buffer command is issued check the XSR to make sure a buffer is available for writing.
10.The number of bytes/words to be written to the Write Buffer = N + 1, where N = byte/word count argument. Count ranges on
this device for byte mode are N = 00H to N = 1FH and for word mode are N = 0x00 to N = 0x0F. The third and consecutive
bus cycles, as determined by N, are for writing data into the Write Buffer. The Confirm command (0xD0) is expected after
exactly N + 1 write cycles; any other command at that point in the sequence aborts the write to buffer operation. See
18, “Write to Buffer Flowchart” on page 59
11.The write to buffer or erase operation does not begin until a Confirm command (0xD0) is issued.
12.Attempts to issue a block erase or program to a locked block.
13.Either 0x40 or 0x10 are recognized by the WSM as the byte/word program setup.
14.Program suspends can be issued after either the Write-to-Buffer or Word/Byte-Program operation is initiated.
15.The clear block lock-bits operation simultaneously clears all block lock-bits.
36
First Bus Cycle
Bus
Cycles
(3)
(4)
(5,6)
Req’d.
Oper
Addr
Data
2
Write
X
0x60
2
Write
X
0xC0
12.
17.
Table 18
for a description of the Status Register bits.
for additional information
Second Bus Cycle
Notes
(3)
(4)
(5,6)
Oper
Addr
Data
Write
X
0xD0
1,15
Write
PA
PD
1
Figure
Datasheet