M28529G-12 Mindspeed Technologies, M28529G-12 Datasheet
M28529G-12
Specifications of M28529G-12
Related parts for M28529G-12
M28529G-12 Summary of contents
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... Memory expandable bytes via external bus • UTOPIA level 2 interfaces • Glueless serial and interleaved highway interfaces to Mindspeed Framers • Octet or Bit level cell delineation • Variable link data rates (64K–8.192 Mb/ 28529-DSH-001-K Functional Block Diagram ® Mindspeed Technologies Mindspeed Proprietary and Confidential September 2007 ...
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... Ordering Information Manufacturing Part Model Number Number M28525 M28525-12 M28525G* M28525G-12 M28529 M28529-12 M28529G* M28529G-12 *The G in the part number indicates that this is an RoHS compliant package. Refer to www.mindspeed.com for additional information. Revision History Revision Level A Advance April 2003 B Advance May 2003 ...
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... IMA Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 1.2.2 Diagnostics/Loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 1.2.3 Cell Delineation Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 1.2.4 Control and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 1.2.4.1 Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 1.2.4.2 ATM Interface .12 1.2.4.3 PHY Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 1.2.4.4 Counters/Status Register Section .13 1.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 1.4 Applications .14 1.4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 28529-DSH-001-K ® Mindspeed Technologies Mindspeed Proprietary and Confidential iii ...
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... Dual Clav/Enb Operation .89 1.14 Transmission Convergence Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 1.14.1 ATM Cell Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 1.14.1.1 HEC Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 1.14.2 ATM Cell Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 1.14.2.1 Cell Delineation .90 1.14.2.2 Cell Delineation Control Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 1.14.2.3 Cell Screening . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 1.14.2.4 Cell Scrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 28529-DSH-001-K ® Mindspeed Technologies Mindspeed Proprietary and Confidential Table of Contents iv ...
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... Idle Cell Mask Control Register .170 2.2.37 0x28—ENCELLT (Transmit Cell Interrupt Control Register .170 2.2.38 0x29—ENCELLR (Receive Cell Interrupt Control Register .171 2.2.39 0x2C—TXCELLINT (Transmit Cell Interrupt Indication Status Register .171 28529-DSH-001-K ® Mindspeed Technologies Mindspeed Proprietary and Confidential Table of Contents v ...
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... Memory Test Address (Bits 0–7 .191 2.4.7 0x806—IMA_MEM_HI_TEST (IMA Memory Test Address (Bits 8–15 .192 2.4.8 0x807—IMA_MEM_TEST_CTL (IMA Memory Test Control / Address MSBs .192 2.4.9 0x808—IMA_MEM_TEST_DATA (IMA Memory Test Data .192 28529-DSH-001-K ® Mindspeed Technologies Mindspeed Proprietary and Confidential Table of Contents vi ...
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... IMA_RX_GRPn_STAT_CTL_CHANGE (Receive Group Status & Control Change Indication .225 2.5.27 IMA_RX_GRPn_ACTUAL_GRP_ID (Actual Receive Group ID .226 2.5.28 IMA_RX_GRPn_STAT_CTL (Receive Group Status and Control .227 2.5.29 IMA_RX_GRPn_TIMING_INFO (Receive Timing Information .228 2.5.30 IMA_RX_GRPn_TEST_CTL (Receive Test Control .229 28529-DSH-001-K ® Mindspeed Technologies Mindspeed Proprietary and Confidential Table of Contents vii ...
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... IMA Version 1.1 PICS Proforma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .275 4.1.1 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .275 4.1.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .275 4.1.3 Symbols and Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .275 4.1.4 Conformance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .275 4.1.5 IMA PICS Proforma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .276 4.1.5.1 Global Statement of Conformance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .276 28529-DSH-001-K ® Mindspeed Technologies Mindspeed Proprietary and Confidential Table of Contents viii ...
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... Instructions for Completing the PICS Proforma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .276 4.1.5.3 IMA Protocol Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .276 4.1.6 PICS Proforma References .292 4.2 Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292 4.3 Power Sequencing .293 28529-DSH-001-K ® Mindspeed Technologies Mindspeed Proprietary and Confidential Table of Contents ix ...
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... Figure 1-26. Details of the TC Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 Figure 1-27. Cell Delineation Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 Figure 1-28. Header Error Check Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 Figure 1-29. CN8370 Interface Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 Figure 1-30. CN8370 Interface - T1 Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 Figure 1-31. CN8370 Interface - E1 Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 Figure 1-32. Fractional T1 Timing .98 28529-DSH-001-K ® Mindspeed Technologies Mindspeed Proprietary and Confidential ix ...
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... Figure 3-25. ATM-side UTOPIA Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265 Figure 3-26. External Memory Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267 Figure 3-27. JTAG Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .268 Figure 3-28. One-second Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269 Figure 3-29. M28525/9 Mechanical Drawing (Bottom View .270 28529-DSH-001-K ® Mindspeed Technologies Mindspeed Proprietary and Confidential List of Figures x ...
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... Figure 3-30. M28525/9 Mechanical Drawing (Top and Side Views .271 Figure 3-31. M28529 Pinout Diagram, UTOPIA-to-Serial (Bottom View .272 Figure 3-32. M28525 Pinout Diagram Utopia-to-Serial (Bottom View .273 Figure 3-33. M28525/9 Pinout Diagram UTOPIA-to-UTOPIA (Bottom View .274 28529-DSH-001-K ® Mindspeed Technologies Mindspeed Proprietary and Confidential List of Figures xi ...
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... Table 1-28. Cell Screening—Accept/Reject Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 Table 2-1. Address Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 Table 2-2. Device Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 Table 2-3. Port Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 Table 2-4. Cell Transmit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 28529-DSH-001-K ® Mindspeed Technologies Mindspeed Proprietary and Confidential xi ...
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... IMA Data Cell (IDC) Rate Implementation Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281 Table 4-5. Link Differential Delay (LDD) Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282 Table 4-6. IMA Interface Operation (IIO) Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282 Table 4-7. IMA Frame Synchronization (IFS) Mechanism Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285 28529-DSH-001-K ® Mindspeed Technologies Mindspeed Proprietary and Confidential List of Tables xii ...
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... IMA Interface OAM Operation Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286 Table 4-9. Test Pattern Procedure (TPP) Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .291 Table 4-10. IMA Interaction with Plane Management Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292 Table 4-11. Management Information Base (MIB) Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292 28529-DSH-001-K ® Mindspeed Technologies Mindspeed Proprietary and Confidential List of Tables xiii ...
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... For example, users who need a data rate higher than the standard T1, (1.544 Mbps) must pay for an entire DS3 (44 Mbps). Often the extra cost cannot be justified. 28529-DSH-001 ® Mindspeed Technologies Mindspeed Proprietary and Confidential Figure 1- ...
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... This example shows a group composed of three links and an IMA frame length of 16. (An invalid frame length used for brevity, the default frame length is 128.) 28529-DSH-001-K Figure 1 1.544 Mb Figure 1-3. It consists of a single IMA overhead ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description where 3 T1 lines are combined into one 4.5 Mb/s 500027_053 2 ...
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... ATM ATM Always at least 1 ICP cell per frame ATM ATM ATM ICP ATM IMA control Protocol Cell ICP n IFSN = n ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description ATM ATM ATM This cell was in the previous frame ATM ATM ATM ICP ...
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... This is one out of the 2 ICP cells comprising the stuff event (mandatory) Status and Control Change Indication 255 and cycling (count to be incremented every time there is a change to octets 12 to 49). Logical IMA group ID ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description 4 ...
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... Bits 4–0 Tx LID of the timing reference link (TRL)—Range Test Pattern Command Bits 7–6 Unused, set to 00 Bit 5 Test Link Command (0: inactive, 1: active) Bits 4–0 Tx LID of test link—Range Value from 0 to 255 Value from 0 to 255 ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description 5 ...
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... Bit 7 Set to 0 for IMA Filler cell Bits 6–0 Unused and set to 0 Set to 0x6A (as defined in ITU-T I.432) Bits 15-10 Reserved field for future use—default value is all zeros Bits 9-0 CRC-10 as defined in ITU-T Recommendation I.610 ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description 6 ...
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... IMA group the link group but cannot be used due to line fault etc. assigned to a group and ready but is waiting for the other end fully configured and carrying traffic ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description Table 1-3. ...
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... This function polls the error counters and failure monitoring registers of the IMA device and must be called at a regular periodic interval. This function should be called when the device interrupt line has been asserted. ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description 110 ms 220 ms 137 ...
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... This is an application defined function that enables interrupts from the IMA hardware device. This is an application defined function that accepts asynchronous event messages from M28525/9 the software. ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description Short Description M28525/9 Subsystem parameters. M28525/9 ...
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... ATM layer cells across all links in the Active state. This includes the negotiation of group parameters (i.e., symmetry and M values), the bringing up of the IMA group, and the graceful addition/recovery and 28529-DSH-001-K ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description 10 ...
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... Each group can have links. • Memory expandable bytes via external bus • Supports IMA versions 1.0 and 1.1 28529-DSH-001-K and in the ATM standard on IMA. Description ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description Table 1-6. Again, this will be 11 ...
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... All control registers are read/write 1.2.4.2 ATM Interface • ATM-side UTOPIA Interface: • 8/16-bit UTOPIA Level 2 Slave • MHz operation • Support for dual Clav and Enable signals • Supports 32 ATM addresses 28529-DSH-001-K ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description 12 ...
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... The M28529 provides direct connection to 32 serial/interleaved highway links or a PHY side UTOPIA bus. In addition, an external memory bus allows the differential delay memory to access Mbytes of external RAM.The M28529 supports both version 1.0 and 1.1 of IMA standard AF-PHY-0086.001 28529-DSH-001-K ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description 13 ...
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... The M2852x is typically used with line framer devices like the CX28398 T1/E1 octal framer or the M28985 ZipWireMulti™ Octal G.shdsl Transceiver with Embedded Microprocessor. Figure 1-4. M2852x Connected to a CX28398 Transceiver itc 28529-DSH-001-K Figure 1 ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description illustrates a typical application ...
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... Layer Layer Layer Layer Device Device Device Device Utopia Utopia Utopia DSLAM Uplink card or ATM Switch card ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description Figure 1-4. The M28529 can be used CO CO ATM Switch ATM Switch Framer Framer LIU LIU ...
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... CX28398 CX28398 Serial Table 1-7 provides a quick comparison of the two devices. External memory interface (1) 2 Mbyte (1) 2 Mbyte ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description RNC M28529 M28529 ATM ATM IMA IMA Layer Layer Framer Framer Device Controller Device ...
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... Cell Delineation is performed internally and the M2852x interfaces directly to the framers. These framers could be T1/E1 or DSL. Further details can be found in the Mindspeed reference design available online. Configuration information is shown in 28529-DSH-001-K Table 1-8. ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description 17 ...
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... External Memory Interface MemAddr[19:0] MemCtrl_CE MemCtrl_OE MemData[15:0] MemCtrl_WE MemCtrl_Clk ExtMemSel MemCtrl_ADSC* (1) Pulled High ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description I/O One Second Input/Output OneSecIO I Transmit Clock SPTxClk[0] O Transmit Data SPTxData[0] I/O Transmit Data Marker SPTxSync[0] SPTxClk[31] I Transmit Clock ...
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... IMA Block 1 IMA TC Counters Micro interface JTAG IMA UTOPIA using Internal TC block; UTOPIA-to-Serial mode using 32 internal serial ports. ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description TC Block cell processor Line interface 0 cell processor Line interface 1 cell processor Line interface 30 cell processor ...
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... When asserted high, the device will not respond to input signal transitions on MicroClk, MW/R, MRd*, or MAS*, MWr*. Additionally, when MCS* is asserted high, the MicroData[7:0] pins are in a high-impedance state but the MicroInt* pin remains operational. ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description Description 20 ...
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... When active low, the device needs servicing. It remains active until the pending interrupt is processed by the Interrupt Service Routine. This pin is an open drain output for an OR logic implementation. An external pull-up resistor is required for this pin. ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description Description 21 ...
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... Receive data stream are stored in the SRAM for the purpose of N24 differential delay compensation. N25 This bus is enabled by pulling the ExtMemSel pin high. N26 P26 P25 P24 P23 R26 P22 R24 T26 R23 T25 T24 U26 ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description Description 1.15.1. 22 ...
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... This signal is enabled by pulling the ExtMemSel pin high. AB25 O Receive SRAM clock signal. This signal is enabled by pulling the ExtMemSel pin high. L26 O Receive SRAM address enable (active low) address strobe. This signal is enabled by pulling the ExtMemSel pin high. ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description Description 23 ...
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... Most of the IMA logic circuits use this clock (or a derivative of it). It can also be used as a T1/E1 reference clock. Refer to Section 1.12. E16 I/PU If Ref_Xclk used as a reference clock, set the frequency as shown in Section A19 O Transmit Reference Clocks. B19 ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description Description 1.12. 24 ...
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... A17 Note that ports 16-31 are no connects in the M28525. C16 B16 C11 B10 D11 AA3 AD1 AC2 AE6 AD7 AC8 AF6 AF12 AC13 AD13 AE13 AD18 AE19 AF20 AD19 ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description Description (1) 25 ...
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... Note that ports 16–31 are no-connects in the M28525. A18 D16 A11 D12 B11 A10 AA2 AB1 AC1 AB2 AE5 AD6 AC7 AF5 AC12 AF11 AD12 AE12 AD17 AE18 AF18 AF19 ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description Description (1) 26 ...
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... A16 Note that ports 16–31 are no-connects in the M28525. C15 B15 C10 B9 A8 D10 AA4 AB3 AE1 AD2 AE7 AD8 AC9 AF7 AF13 AF14 AC14 AD14 AC18 AE20 AF21 AD20 ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description Description (1) 27 ...
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... UTOPIA-UTOPIA mode. The designer is cautioned to ensure that PhyIntFcSel never gets configured low AC4 AD4 AF2 AF3 AE9 AD10 AF9 AC11 AD15 AF16 AE16 AC16 AE22 AC20 AD21 AF24 ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description Description (1) 28 ...
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... When the PHY serial interface is enabled, this is the transmit line data output. A12 Note that ports 16–31 are no-connects in the M28525. E13 C12 AD5 AC6 AE4 AF4 AE10 AF10 AD11 AE11 AD16 AE17 AF17 AC17 AE23 AC21 AD22 AF25 ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description Description (1) 29 ...
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... When the PHY serial interface is enabled, this is the transmit line clock input. D14 Note that ports 16–31 are no-connects in the M28525. C14 B14 AC3 AB4 AF1 AE2 AE8 AD9 AC10 AF8 AF15 AE14 AC15 AB14 AC19 AE21 AF22 AF23 ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description Description (1) 30 ...
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... D26 I Parity status signal bit UTOPIA mode, a parity calculation is performed over atmUTxData[7:0] for each clock cycle of atmUTxClk. Odd parity is used bit UTOPIA mode, this signal is the parity of atmUTxData[15:0]. This signal is optional. ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description Description 31 ...
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... Enable Data transfer and output enable for receive ATM cells (active low). When using single Clav mode (DualClavEnb, bit4 in D18 ATMINTFC register 0xF03, is set low), only atmURxEnb[0] is used and atmURxEnb[1] is not used but must be pulled up. This is most common configuration. ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description Description 32 ...
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... Receive ATM cells output from the IMA D24 subsystem and also selects the channel sourcing the atmURxClAv signal. All 5 bits are not required in every application. C25 B26 E24 ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description Description 33 ...
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... Supply Voltage (1.8 V) 28529-DSH-001-K No. I/O E9 Power supply connections. (1.8 V) E10 E17 J5 J22 K5 K10 K11 K16 K17 K22 L10 L17 T10 T17 U5 U10 U11 U16 U17 U22 V5 V22 AB9 AB10 AB17 AB18 ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description Description 34 ...
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... E19 E20 G5 G22 H5 H22 K12 K15 L5 L22 M2 M5 M10 M17 M22 R10 R17 R22 T5 T22 Power supply connections. (3 U12 U15 W5 W22 Y5 Y22 AB7 AB8 AB11 AB12 AB15 AB16 AB19 AB20 AE3 ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description Description 35 ...
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... Pin Label Signal Name VSS Ground 28529-DSH-001-K No. I/O A1 Ground connections. B2 B12 D17 D23 E5 E6 E14 E21 E22 F5 F22 K13 K14 L11 L12 L13 L14 L15 L16 M11 M12 M13 M14 M15 M16 ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description Description 36 ...
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... No. I/O N2 Ground connections. N10 N11 N12 N13 N14 N15 N16 N17 N22 P5 P10 P11 P12 P13 P14 P15 P16 P17 R11 R12 R13 R14 R15 R16 R25 T11 T12 ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description Description 37 ...
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... V logic, this pin must be D4 connected using 3.3 V system, connect to 3.3 V. A25 Spare (unused) pins on the package. Reserved for future use and should be left unconnected. B1 AA23 AB23 AC05 AC25 ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description Description 38 ...
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... Interfac e MemData[15:0] MemCtrl_CE MemCtrl_OE MemCtrl_WE ExtMemSel MemCtrl_Clk MemCtrl_ADSC* (1) Pulled High ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description I/O One Second Input/Output OneSecIO I PHY Transmit Cell Available phyUTxSOC O PHY Transmit Start of Cell O PHY Transmit Data Bus phyUTxPrty O PHY Transmit Parity ...
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... UTOPIA-to-UTOPIA Configuration Information ATMMux [7,6] PhyIntFcSel (ATMINTFC, 0xF03) (Pin AD24) 01 Low General Note: Use of external memory is optional. 28529-DSH-001-K IMA UTOPIA using the PHY Side UTOPIA; Internal TC block and serial ports not used. ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description Description 40 ...
Page 56
... When asserted high, the device will not respond to input signal transitions on MicroClk, MW/R, MRd*, or MAS*, MWr*. Additionally, when MCS* is asserted high, the MicroData[7:0] pins are in a high-impedance state but the MicroInt* pin remains operational. ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description Description 41 ...
Page 57
... When active low, the device needs servicing. It remains active until the pending interrupt is processed by the Interrupt Service Routine. This pin is an open drain output for an external wired OR logic implementation. An external pull-up resistor is required for this pin. ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description Description 42 ...
Page 58
... Differential delay SRAM Data Bus. ATM cells extracted from the Receive data stream are stored in the SRAM for the purpose of N24 differential delay compensation. N25 N26 P26 P25 P24 P23 R26 P22 R24 T26 R23 T25 T24 U26 ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description Description 1.15.1. 43 ...
Page 59
... I/PU Controls the boundary-scan Test Access Port (TAP) controller operation. This pin has a pull-up resistor. C4 I/PU The serial test data input. This pin has a pull-up resistor The serial test data output. ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description Description 44 ...
Page 60
... Cell Available signals for Receive PHY interfaces. phyURxClAv[n] is active when one or more complete cells can be transferred. To AF18 I/PD support different PHY devices, separate cell available signals are provided. This allows expansion to 32 points. ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description Description Device Addresses 0–15, 31 0– ...
Page 61
... Cell Available signals for Transmit ATM cells. When phyUTxClAv[n] is active high, the PHY has space available for one or more D1 complete cells. To support different PHY devices, separate cell available signals are provided IMA_SysClk divided by two. ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description Description Device Addresses 0–15, 31 0–31 46 ...
Page 62
... Most of the IMA logic circuits use this clock (or a derivative of it). It can also be used as a T1/E1 reference clock. Refer to E16 I/PU If this used as a reference clock, set the frequency as shown in Section A19 O Transmit Reference Clocks. B19 ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description Description Section 1.12. 1.12. 47 ...
Page 63
... D26 I Parity status signal bit UTOPIA mode, a parity calculation is performed over atmUTxData[7:0] for each clock cycle of atmUTxClk. Odd parity is used bit UTOPIA mode, this signal is the parity of atmUTxData[15:0]. This signal is optional. ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description Description 48 ...
Page 64
... Only atmURxEnb[0] is used (atmURxEnb[1] will be ignored) when D18 I/PU the DualClavEnb (bit 4) is low (default) in the ATMINTFC register 0xF03. This is most common configuration. When using single clav mode (DualClavEnb bit is set to 0), atmURxEnb[1] must be pulled up. ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description Description 49 ...
Page 65
... Receive ATM Cell Bus address. This address determines the source channel of the Receive ATM cells output from the IMA subsystem D24 and also selects the channel sourcing the atmURxClAv signal. C25 B26 E24 ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description Description 50 ...
Page 66
... Supply Voltage (1.8 V) 28529-DSH-001-K No. I/O E9 Power supply connections. (1.8 V) E10 E17 J5 J22 K5 K10 K11 K16 K17 K22 L10 L17 T10 T17 U5 U10 U11 U16 U17 U22 V5 V22 AB9 AB10 AB17 AB18 ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description Description 51 ...
Page 67
... G22 H5 H22 K12 K15 L5 L22 M2 M5 M10 M17 M22 R17 R10 R22 T5 T22 Power supply connections. (3.3 V) U12 (Continued) U15 W5 W22 Y5 Y22 AB7 AB8 AB11 AB12 AB15 AB16 AB19 AB20 AE3 U3 ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description Description 52 ...
Page 68
... Pin Label Signal Name VSS Ground 28529-DSH-001-K No. I/O A1 Ground connections. B2 B12 D17 D23 E5 E6 E14 E21 E22 F5 F22 K13 K14 L11 L12 L13 L14 L15 L16 M11 M12 M13 M14 M15 M16 ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description Description 53 ...
Page 69
... AB22 AC24 AD3 AE15 AC23 Provides ESD protection when interfacing with 5 V systems. If using this device in a system with 5 V logic, this pin must be D4 connected using 3.3 V system, connect to 3.3 V. ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description Description 54 ...
Page 70
... I/O A3 Unused Inputs with internal pulldown A10 A11 A15 A16 A17 A18 B10 B11 B14 B15 B16 B17 B18 C10 C11 C14 C15 C16 C17 D10 D11 D12 D14 D15 D16 ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description Description 55 ...
Page 71
... M2852x Pin Descriptions (16 of 18) Pin Label Signal Name Unused Input 28529-DSH-001-K No. I/O J3 Unused Inputs with Internal Pulldown AA2 AA3 AA4 AB1 AB2 AB3 AB4 AC1 AC2 AC3 AC7 AC8 AC9 AC10 AC18 AC19 ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description Description 56 ...
Page 72
... Unused Inputs with Internal Pulldown AD2 AD6 AD7 AD8 AD9 AD18 AD19 AD20 AE1 AE2 AE5 AE6 AE7 AE8 AE19 AE20 AE21 AF1 AF5 AF6 AF7 AF8 AF20 AF21 AF22 AF23 ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description Description 57 ...
Page 73
... AC21 AD16 AD22 AE17 AE23 AF17 AF25 B6 C12 D13 Note: Leave unconnected. D8 E13 A25 Spare (unused) pins on the package. Reserved for future use and should be left unconnected. B1 AA23 AB23 AC5 AC25 ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description Description 58 ...
Page 74
... Serial Stream Muxing into Interleaved Highway Interleaved Serial Stream Highway 28529-DSH-001-K Table 1-12 for the grouping, changes to the pinout Table 1-16. Table 1-13 desribes the functionality of each of the interleaved Interleaved Serial Stream Highway ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description Section 1.14.2.5.5. The 59 ...
Page 75
... IHTxSync[2] D8 IHTxData[2] B7 IHTxInDo[2] C9 IHTxClk[2] ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description Description When the Interleaved Highway interface is enabled, this is the frame sync input. When the Interleaved Highway interface is enabled, this is the receive line clock input. When the Interleaved Highway interface is enabled, this is the receive timeslot indicator input ...
Page 76
... IHRxClk[6] AD7 IHRxInDo[6] AE7 IHRxData[6] AE9 IHTxSync[6] AE10 IHTxData[6] AD10 IHTxInDo[6] AE8 IHTxClk[6] Table 1-16 become unused. ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description Interleaved Highway 7 No. Pin Label No. AF12 IHRxSync[7] AD18 AC12 IHRxClk[7] AD17 AC13 IHRxInDo[7] AE19 AF13 ...
Page 77
... Unused I/O (Pulled down/Outputs tristate) F2 Note: Leave unconnected. F1 Unused Output (tristate Note: Leave unconnected. Highway 3 H2 Unused Input (Pulled Down Unused I/O (Pulled down/Outputs tristate) N5 Note: Leave unconnected. N1 Unused Output (tristate Note: Leave unconnected. 28529-DSH-001-K ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description 62 ...
Page 78
... Unused Input (Pulled Down) AC14 AC15 AD12 AD13 AD14 AE12 AE13 AE14 AF11 AF14 AC16 Unused I/O (Pulled down/Outputs tristate) AE16 Note: Leave unconnected. AC17 Unused Output (tristate) AE17 AF17 Note: Leave unconnected. 28529-DSH-001-K ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description 63 ...
Page 79
... Unused Input (Pulled Down) AD20 AE18 AE20 AE21 AF18 AF19 AF20 AF21 AF22 AF23 AD21 Unused I/O (Pulled down/Outputs tristate) AF24 Note: Leave unconnected. AC21 Unused Output (tristate) AD22 AF25 Note: Leave unconnected. 28529-DSH-001-K ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description 64 ...
Page 80
... Table 1-17. Cell Delineation Configuration Information ATMMux [7,6] PhyIntFcSel (ATMINTFC, 0xF03) (Pin AD24) 10 High 28529-DSH-001-K Table 1-17. TC Block Direct; Device used as Stand-alone cell delineator with 32 serial ports; IMA block not used. ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description Description 65 ...
Page 81
... SPTxData will be corrupted in in Source Loopback mode 0 28529-DSH-001-K TC Transmit Port ATM Cell Transmitter ATM Cell Receiver TC Receive Port Cell Validation Cell VPI/VCI Screening Alignment ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description UTOPIA Level 2 Interface Host atmUTxClk Interface atmUTxClAv Transmit ...
Page 82
... Configuring a port for line loopback mode disables all UTOPIA signals for that port. 28529-DSH-001-K ATM Cell Transmitter ATM Cell Receiver Cell Cell Validation Alignment VPI/VCI Screening ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description UTOPIA Level 2 Interface IMA Interface atmUTxClk ...
Page 83
... OneSec Micro JTAG Interface Pins JTAG MICRO INTERFACE INTERFACE Figure 1-15. This loopback occurs in the PHY layer UTOPIA ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description TC PORTS Cell processor Line interface 0 Cell processor Line interface 1 PHY-SIDE INTERFACE Cell processor Line interface 30 ...
Page 84
... C s OneSe c Micro JTA G Interface Pins JTAG MICRO INTERFACE INTERFACE ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description During IMA System Loopback 0 data will flow through the TC block to the serial interface if enabled. TC PORTS Cell Line interface processor 0 Cell Line interface ...
Page 85
... IMA_SysClk Slave / External IMA_RefClk SPRxClk or IHRxClk Slave / External Rx Cell stream IMA_SysClk or IMA_RefClk IMA_SysClk Master / Internal IMA_RefClk Figure ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description Table 1-18) for the Tx direction Direction Sources SPRxClk or IHRxClk Rx Cell stream (1) IMA_SysClk or IMA_RefClk SPRxClk or IHRxClk ...
Page 86
... Digital Phase Locked Loop This block generates a bit rate clock that is phase locked to the PHY side RxClAv signal. It can monitor all 32 ports on the bus. Any port can be selected as the group timing reference. 28529-DSH-001-K Description ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description 71 ...
Page 87
... Figure 1-16. M28529 Clock Diagram Mux N ote 1 28529-DSH-001 Mux Tx Mux N ote 1 ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description 72 ...
Page 88
... Maximum Aggregate BW (Mbps) < Frequency of IMA_SysClk (MHz) * (20 / 9). • 16 IMA groups • Maximum Aggregate BW (Mbps) < Frequency of IMA_SysClk (MHz) * (24 / 9). 28529-DSH-001-K IMA_SysClk/16 < Link Rate < IMA_SysClk kbps INT_FREQ < Link Rate < INT_FREQ kbps ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description Link Rate > IMA_SysClk kbps Link Rate > INT_FREQ kbps 73 ...
Page 89
... IMA core is not used. The requirements of the SPRxClk, IHRxClk, and IMA_RefClk inputs are summarized below: 28529-DSH-001-K # groups Maximum BW (Mbps) 0 157.3 1 152.9 ≤ 16 131.1 ≤ 32 109.2 0 211.2 1 205.3 ≤ 16 176.0 ≤ 32 146.7 ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description 74 ...
Page 90
... Clock Period Maximum Minimum 256 / IMA_SysClk 4 / IMA_SysClk N/A N/A N/ 8.192 MHz N/A N/A 256 / IMA_SysClk 16 / IMA_SysClk ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description IMA Link Rate (2) Maximum Min (4 / IMA_SysClk, INT_FREQ / 4) INT_FREQ / 4 1.920 Mbps 2.048 Mbps IMA_SysClk / 16 Table 1-24 provides ...
Page 91
... MHz kHz, ≥ 49.152 MHz ≥ 40.96 MHz No ≥ 49.152 MHz Section 1.12.2.2. Figure 1-17), T1/E1 line rate clocks and IMA_SysClk are used to ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description IMA_RefClk Ref? Requirements Opt. T1: 1.544 MHz E1: 2.048 MHz (3) Yes T1: 1 ...
Page 92
... System Clock. The “Slave / External” configuration usually relies on the clock synthesizers. 28529-DSH-001-K 1.544 MHz (T1) or 2.048 MHz (E1) Tx_TRL[1:0] SPRxClk[0] Framer SPTxClk[0] M28529 32 SPRxClk[31] Framer SPTxClk[31] ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description 1x Clock Source 1.544 MHz (T1) or 2.048 MHz (E1) IMA_RefClk 24x Oscillator IMA_SysClk 37.056 MHz (T1) or 49.152 MHz (E1) ...
Page 93
... T1/E1 applications. 28529-DSH-001-K Clock Selection 8 kHz NTR Tx_TRL[0] SPRxClk[0] DSP Framer SPTxClk[0] 32 NTR SPRxClk[31] DSP Framer SPTxClk[31] Figure 1-19 similar to Figure 1-17 ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description Local Oscillator IMA_RefClk IMA_SysClk MHz M28529 with the TC blocks external to 78 ...
Page 94
... SPRxClk[23] Framer TC Figure 1-20 8 kHz NTR Tx_TRL[0] PHY Rx UTOPIA Framer TC 32 NTR Framer TC Phy Tx UTOPIA ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description 1x Clock Source 1.544 MHz (T1) or 2.048 MHz (E1) IMA_RefClk 24x Oscillator IMA_SysClk 37.056 MHz (T1) M28529 or 49.152 MHz (E1) shows the DSL UTOPIA application ...
Page 95
... The IMA_SysClk is being used to derive the TX IDCR clock. The device is configured using a software driver. The following code is an example of calls to the driver: IMA_LINK_TYPE = IMA_DS1 IMA_DSL_USE_REF_CLK2 = IMA_INACTIVE IMA_DSL_REF_GENERATOR = IMA_INACTIVE IMA_ALT_RX_TRL = IMA_INACTIVE IMA_GRP_TX_TRL_SRC = IMA_REF_XCLK (grp#) IMA_GRP_RX_TRL_SRC = IMA_RX_TRL_(x) (grp#) 28529-DSH-001-K ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description 80 ...
Page 96
... The device is configured using a software driver. The following code is an example of calls to the driver: 28529-DSH-001-K n*8kHz NCO 1 Synchronizer RM ref 1 Pre-Scaler Synchronizer RM ref /16 /24 ref 1 Synchronizer RM ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description up/down adjust Phase Comparator 424 n*8kHz NCO Note 2 n*8kHz NCO Note 2 81 ...
Page 97
... Mbps. 28529-DSH-001-K n*8kHz NCO 1 Synchronizer RM ref ref 1 Pre-Scaler Synchronizer RM ref /16 /24 ref 1 Synchronizer RM ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description up/down adjust Phase Comparator 424 IDCR Clk Mux n*8kHz NCO Note 2 n*8kHz NCO Note 2 82 ...
Page 98
... The device is configured using a software driver. The following code is an example of calls to the driver: IMA_LINK_TYPE = IMA_VAR_RATE IMA_DSL_REF_CLK_FREQUENCY = 40960000 IMA_DSL_USE_REF_CLK2 = IMA_INACTIVE IMA_DSL_REF_GENERATOR = IMA_ACTIVE IMA_ALT_RX_TRL = IMA_ACTIVE IMA_GRP_LINK_BANDWIDTH = 2304 (grp#) IMA_GRP_CLK_REF_FACTOR = IMA_NO_DIV (grp#) IMA_GRP_TX_TRL_SRC = IMA_REF_XCLK (grp#) IMA_GRP_RX_TRL_SRC = IMA_RX_TRL_(x) (grp#) 28529-DSH-001-K ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description 83 ...
Page 99
... On the receive side of the UTOPIA interface, incoming cells are placed in the receive FIFO until sent. Both FIFOs on the ATM side are 4 cells deep. 28529-DSH-001-K n*8kHz NCO 1 Synchronizer RM ref 1 Pre-Scaler Synchronizer RM ref /16 /24 ref 1 Synchronizer RM ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description up/down adjust Phase 1 RM Comparator RM 424 n*8kHz NCO Note 2 n*8kHz NCO Note 2 84 ...
Page 100
... UTOPIA Level 2 interface operates MHz in 16 bit mode (Note: 33 MHz for TC Mode Only) and 33 MHz in 8 bit mode. The PHY-Side UTOPIA interface operates at half the IMA_Sysclk rate (IMA_SysClk/2) 28529-DSH-001-K Figure 1-26 Figure 1-24. ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description and described below. 85 ...
Page 101
... In single Clav mode, address 0x1F can be assigned as a valid port address to enable 32 unique addresses. The behavior of Clav when a port is not selected can be set to either driven low or tri-state. See the IMA_ATM_UTOPIA_BUS_CTL register, 0x813, bit 1. 28529-DSH-001-K ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description Table 1-25. Figure 1-24 ...
Page 102
... IMA UTOPIA using the PHY Side UTOPIA; UTOPIA-to-UTOPIA; TC block/serial ports not used. IMA UTOPIA using Internal TC block; UTOPIA-to-Serial mode; 32 internal serial ports TC only; Device used as Stand-alone cell delineator with 32 serial ports; IMA block not used. ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description PHY Layer Utopia Bus Table 1-25 and Section 1 ...
Page 103
... Only the Transmit side is shown for clarity. The Receive side is identical. 28529-DSH-001-K Figure UTOPIA data/ address bus phyUTxClav_0 phyUTxEnb_0 M28529 phyUTxClav_1 phyUTxEnb_1 ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description 1-25. This effectively provides two buses IMA Link Number 1 CX28985 UTOPIA Port 0− CX28985 UTOPIA Port 8− ...
Page 104
... HEC calculation can be disabled by setting bit 7 of CGEN (0x08 When HEC is disabled, the M2852x leaves the contents of the HEC field unchanged and transmits whatever data is placed in that field by the ATM layer. 28529-DSH-001-K ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description 89 ...
Page 105
... Status and Control ATM Cell Transmitter ATM Cell Receiver Cell Cell Validation Alignment VPI/VCI Screening One Second Interface TMS TDO 8kHzIn TDI ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description Control Lines UTOPIA Interface Level 2 Interface IMA Transmit atmUTxClk UTOPIA atmUTxClAv ...
Page 106
... HEC bytes in DSS). 28529-DSH-001-K 1-27). Synchronization will be held until seven consecutive incorrect HECs 1 Correct HEC Pre-Sync 1 Errored HEC 7 Errored HECs ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description 6 Correct HECs Sync 500027_006 Figure 1-28.) ...
Page 107
... Cell Delineation in Sync State No Errors Detected (Pass Cell) Apparent Single-bit Error (Correct Error and Pass Cell) Apparent Multi-bit Error (Drop Cell) Table 1-26 shows the control bits function. ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description No Errors Detected (Pass Cell) Correction Mode 500027_007 ...
Page 108
... The RejHdr bit (bit 7) in the CVAL register (0x0C) determines whether matching cells are rejected or accepted set to 0, matching cells are accepted set to 1, matching cells are rejected. See Table 1-27 28529-DSH-001-K Description and Table 1-28. ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description 93 ...
Page 109
... Fail 0 Fail 1 Match x Match Result Accept Cell Reject Cell Reject Cell Accept Cell scramble the payload, leaving the five header bytes untouched polynomial to scramble the entire cell, except the HEC byte. HEC is ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description 94 ...
Page 110
... The 8370 is a single port transceiver which is shown here for simplicity. 28529-DSH-001-K Figure 1-29. The M28529 receives a T1/E1 data stream from Tx Frame Marker Serial Data TPCMI Rx Frame Marker Serial Data Clock Clock Source ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description M28529 SPTxSync SPTxData SPRxSync SPRxData SPTxClk, SPRxClk 95 ...
Page 111
... Tx Serial Data LSB T1 Mod Count 0 Rx Framer Marker TS24 Rx Serial Data LSB T1 Mod Count 0 General Notes: In T1, ATM Cells are mapped into time slots 1-24 28529-DSH-001-K TS1 F MSB 192 TS1 F MSB 192 ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description 96 ...
Page 112
... The clocks are gapped internally in the M28525/9 during inactive timeslots. ATM cell bytes are continuously mapped into active timeslots. 28529-DSH-001-K TS0 MSB 255 TS0 MSB 255 ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description 97 ...
Page 113
... The M2852x receives a data stream from the external framer, performs bit level cell 28529-DSH-001-K TS1 TS0 (overhead) TS1 (inactive) TS1 Figure 1-34. This mode allows connection with framers that ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description TS2 (inactive) TS3 TS2 TS3 TS2 TS3 ...
Page 114
... Tx Serial Data TxData SPTxData Tx Sync TxSync SPTxSync (1) Rx Sync SPRxSync Rx Serial Data RxData SPRxData Tx Clock TxClk SPTxClk Rx Clock RxClk SPRxClk Transparent Cell Transport OH Figure ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description M28529 PORT X 500027_014 1-35. This mode allows connection with 99 ...
Page 115
... This interface is designed to communicate with Mindspeed's CX2839x framer devices, running in internally multiplexed mode. 28529-DSH-001-K Tx Serial Data TSER SPTxData SPTxSync +3.3 V SPRxSync Rx Serial Data RSER SPRxData Clock SPTxClk BClk SPRxClk Transparent Cell Transport MSB ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description M28529 PORT X 500027_014a Figure 1-36 and Figure 1- 100 ...
Page 116
... RPCMO RSBCKI CX2839x TXINDO TFSYNC TPCMI TSBCKI Note: Device Configured for Internally Multiplexed Mode 8.152 MHz Receive Clock 28529-DSH-001-K 8.152 MHzTransm it Clock ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description IHRxINDo IHRxSync IHRxData IHRxClk M28529 IHTxInDo IHTxSync IHTxData IHTxClk 101 ...
Page 117
... Input pins IHRxSync and IHTxSync are provided to indicate the first bit (MSB) of the first timeslot of the first data stream, in the receive and transmit directions respectively. The streams are multiplexed in order of the lowest numbered stream to highest number. 28529-DSH-001-K Receive Fram e Sync Transm it Fram e Sync ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description IHRxINDo IHRxSync IHRxData IHRxClk ...
Page 118
... N ote: O nly the transm t fram e structure is shown, but the receive fram e structure is identical 28529-DSH-001-K shows how the datastreams are combined on the interleave highway. TS31B TS31C TS31D TS0A ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description Figure 1- TS0B TS0C TS0D ...
Page 119
... TC processor are tied low (inactive state when IOMODE[6] and IOMODE[4] are set to default values in xDSL mode) so that they have no effect NOTE: The T1/E1 streams must be locked to the 8.192 MHz clock rate. Figure 1- block diagram showing how four serial links are combined. 28529-DSH-001 ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description ...
Page 120
... When the reset bit is deasserted, all changes to the registers take place simultaneously. 28529-DSH-001-K Line interface n Line interface n+1 TC cell Line interface n+2 Line interface TC cell n+3 ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description Mux 105 ...
Page 121
... When configured as an input, status registers and counters may be latched on the rising edge of this input. See Bit 0 of the GENCTRL register (0xF00). NOTE: When latching is disabled and a counter is wider than one byte, the LSB should be read first to retain the values of the other bytes for a subsequent read. 28529-DSH-001-K ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description 106 ...
Page 122
... EnIntPin (bit 3) in the GENCTRL register (0x0F00). Figure 1-42 illustrates the flow chart of the interrupt generation process and involved in the interrupt generation process. 28529-DSH-001-K ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description Figure 1-43 illustrates the registers 107 ...
Page 123
... SUMINT No Interrupt Indication Enabled ? Yes Set SUMINT Interrupt Indication Bit SUMPORT No Port Indication Enabled ? Yes Set SUMPORT Interrupt Indication Bit Interrupt No Pin (MInt*) Enabled ? Yes Set Interrupt Pin (MInt*) ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description Return 500027_015 108 ...
Page 124
... Input to Latch Enabled by 5 ENSUMINT Input to Latch Enabled by ENSUMPORT0 (0xF06) SUMINT (0x000) Resvd 7 Resvd 6 5 Resvd Resvd 4 Resvd 3 Resvd 2 1 TxCellInt 0 RxCellInt Input to Latch Enabled by ENSUMINT ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description MicroInt OneSecInt Input to Latch Enabled by ENONESECINT (0xF19) 109 ...
Page 125
... In Level 2, OneSecInt and ExInt are cleared when the register is read. However, the TxCellInt and RxCellInt bits are cleared only when the corresponding Level 1 register is read and cleared. Level 3 bits are cleared when the entire corresponding Level 2 register has been read and cleared. 28529-DSH-001-K ® Mindspeed Technologies Mindspeed Proprietary and Confidential Functional Description 110 ...
Page 126
... Port 17 Control and Status Registers 0480-04BF Port 18 Control and Status Registers 28529-DSH-001-K Table 2-1 Table 2-3 lists the port-level control and status registers. Description ® Mindspeed Technologies Mindspeed Proprietary and Confidential lists the address ranges that Port Base Address (Hex) 0000 0040 0080 00C0 ...
Page 127
... Summary Interrupt Control Register (TC Ports 16-23) — Summary Interrupt Status Register (TC Ports 24-31) — Summary Interrupt Control Register (TC Ports 24-31) — Reserved, set register to all 0’s ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Port Base Address (Hex) 04C0 0500 0540 ...
Page 128
... Transmit Idle Cell Payload Control Register — Error Pattern Control Register — Cell Validation Control Register — UTOPIA Control Register 1 — UTOPIA Control Register 2 ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Page Number page 184 page 185 page 185 page 186 page 186 ...
Page 129
... Transmit Cell Status Control Register (1) Receive Cell Status Control Register (2) Idle Cell Receive Counter (low byte) (2) Idle Cell Receive Counter (high byte) ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Page Number page 158 page 158 page 159 page 159 page 160 ...
Page 130
... Non-Matching Cell Counter (low byte) (2) Non-Matching Cell Counter (high byte) — Reserved, set to a logical 0 — Reserved, set to a logical 0 Description ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Page Number page 174 page 175 page 175 page 176 page 176 ...
Page 131
... Name Address 0x0D UTOP1 UTOPIA Control Register 1 0x0E UTOP2 UTOPIA Control Register 2 28529-DSH-001-K Description Description ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Page Number page 156 page 162 page 163 page 163 page 164 page 164 page 165 page 165 ...
Page 132
... Receive Cell Interrupt Indication Status Register 0x2E TXCELL Transmit Cell Status Register 0x2F RXCELL Receive Cell Status Register 28529-DSH-001-K Description Description ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Page Number page 181 page 181 page 182 page 182 page 183 page 183 ...
Page 133
... Memory Test Data Link Diagnostic Control Link Differential Delay Receive Link Anomalies IMA Phy Side UTOPIA Loopback Address Diagnostic Diagnostic Register TRL Control Address ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Page Number page 173 page 174 page 174 page 175 ...
Page 134
... Tx GRP 1 Tx Test Pattern Tx GRP 2 Rx Test Pattern Tx GRP 2 Control Tx GRP 2 First Link Address Tx GRP 2 Tx Group ID Tx GRP 2 Status / Control Tx GRP 2 Timing Control ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Page Number page 196 page 197 page 197 page 198 ...
Page 135
... Receive UTOPIA Address 0x01 Cell Count MSBs Receive UTOPIA Address 0x02 Cell Count LSBs Receive UTOPIA Address 0x02 Cell Count MSBs Receive UTOPIA Address 0x03 Cell Count LSBs Receive UTOPIA Address 0x03 Cell Count MSBs ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Page Number page 214 ...
Page 136
... Rx Link 6 Control Rx Link 7 Control Rx Link 0 Status Rx Link 1 Status Rx Link 2 Status Rx Link 3 Status Rx Link 4 Status Rx Link 5 Status Rx Link 6 Status Rx Link 7 Status ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Page Number page 232 page 233 page 234 page 235 page 236 121 ...
Page 137
... Rx Link 0 OIF-IMA Counter Rx Link 1 OIF-IMA Counter Rx Link 2 OIF-IMA Counter Rx Link 3 OIF-IMA Counter Rx Link 4 OIF-IMA Counter Rx Link 5 OIF-IMA Counter Rx Link 6 OIF-IMA Counter Rx Link 7 OIF-IMA Counter ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Page Number page 237 page 238 page 239 page 240 ...
Page 138
... Rx GRP 1 Timing Control Rx GRP 1 Test Control Rx GRP 1 Tx Test Pattern Rx GRP 2 Rx Test Pattern Rx GRP 2 SCCI Rx GRP 2 Rx Group ID Rx GRP 2 Status / Control ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Page Number page 243 page 220 page 221 page 222 ...
Page 139
... Tx GRP 6 First Link Address Tx GRP 6 Tx Group ID Tx GRP 6 Status / Control Tx GRP 6 Timing Control Tx GRP 6 Test Control Tx GRP 6 Tx Test Pattern Tx GRP 7 Rx Test Pattern ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Page Number page 228 page 229 page 230 ...
Page 140
... Receive UTOPIA Address 0x05 Cell Count MSBs Receive UTOPIA Address 0x06 Cell Count LSBs Receive UTOPIA Address 0x06 Cell Count MSBs Receive UTOPIA Address 0x07 Cell Count LSBs Receive UTOPIA Address 0x07 Cell Count MSBs ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Page Number page 209 ...
Page 141
... Rx Link 14 Control Rx Link 15 Control Rx Link 8 Status Rx Link 9 Status Rx Link 10 Status Rx Link 11 Status Rx Link 12 Status Rx Link 13 Status Rx Link 14 Status Rx Link 15 Status ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Page Number page 232 page 233 page 234 page 235 page 236 126 ...
Page 142
... Rx Link 8 OIF-IMA Counter Rx Link 9 OIF-IMA Counter Rx Link 10 OIF-IMA Counter Rx Link 11 OIF-IMA Counter Rx Link 12 OIF-IMA Counter Rx Link 13 OIF-IMA Counter Rx Link 14 OIF-IMA Counter Rx Link 15 OIF-IMA Counter ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Page Number page 237 page 238 page 239 page 240 ...
Page 143
... Rx GRP 5 Timing Control Rx GRP 5 Test Control Rx GRP 5 Tx Test Pattern Rx GRP 6 Rx Test Pattern Rx GRP 6 SCCI Rx GRP 6 Rx Group ID Rx GRP 6 Status / Control ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Page Number page 243 page 220 page 221 page 222 ...
Page 144
... Tx GRP 10 First Link Address Tx GRP 10 Tx Group ID Tx GRP 10 Status / Control Tx GRP 10 Timing Control Tx GRP 10 Test Control Tx GRP 10 Tx Test Pattern Tx GRP 11 Rx Test Pattern ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Page Number page 228 page 229 page 230 ...
Page 145
... Receive UTOPIA Address 0x09 Cell Count MSBs Receive UTOPIA Address 0x0A Cell Count LSBs Receive UTOPIA Address 0x0A Cell Count MSBs Receive UTOPIA Address 0x0B Cell Count LSBs Receive UTOPIA Address 0x0B Cell Count MSBs ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Page Number page 209 ...
Page 146
... Rx Link 22 Control Rx Link 23 Control Rx Link 16 Status Rx Link 17 Status Rx Link 18 Status Rx Link 19 Status Rx Link 20 Status Rx Link 21 Status Rx Link 22 Status Rx Link 23 Status ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Page Number page 232 page 233 page 234 page 235 page 236 131 ...
Page 147
... Rx Link 16 OIF-IMA Counter Rx Link 17 OIF-IMA Counter Rx Link 18 OIF-IMA Counter Rx Link 19 OIF-IMA Counter Rx Link 20 OIF-IMA Counter Rx Link 21 OIF-IMA Counter Rx Link 22 OIF-IMA Counter Rx Link 23 OIF-IMA Counter ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Page Number page 237 page 238 page 239 page 240 ...
Page 148
... Rx GRP 9 Timing Control Rx GRP 9 Test Control Rx GRP 9 Tx Test Pattern Rx GRP 10 Rx Test Pattern Rx GRP 10 SCCI Rx GRP 10 Rx Group ID Rx GRP 10 Status / Control ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Page Number page 243 page 220 page 221 page 222 ...
Page 149
... Tx GRP 14 First Link Address Tx GRP 14 Tx Group ID Tx GRP 14 Status / Control Tx GRP 14 Timing Control Tx GRP 14 Test Control Tx GRP 14 Tx Test Pattern Tx GRP 15 Rx Test Pattern ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Page Number page 228 page 229 page 230 ...
Page 150
... Receive UTOPIA Address 0x0D Cell Count MSBs Receive UTOPIA Address 0x0E Cell Count LSBs Receive UTOPIA Address 0x0E Cell Count MSBs Receive UTOPIA Address 0x0F Cell Count LSBs Receive UTOPIA Address 0x0F Cell Count MSBs ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Page Number page 209 ...
Page 151
... Rx Link 30 Control Rx Link 31 Control Rx Link 24 Status Rx Link 25 Status Rx Link 26 Status Rx Link 27 Status Rx Link 28 Status Rx Link 29 Status Rx Link 30 Status Rx Link 31 Status ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Page Number page 232 page 233 page 234 page 235 page 236 136 ...
Page 152
... Rx Link 24 OIF-IMA Counter Rx Link 25 OIF-IMA Counter Rx Link 26 OIF-IMA Counter Rx Link 27 OIF-IMA Counter Rx Link 28 OIF-IMA Counter Rx Link 29 OIF-IMA Counter Rx Link 30 OIF-IMA Counter Rx Link 31 OIF-IMA Counter ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Page Number page 237 page 238 page 239 page 240 ...
Page 153
... Rx GRP 13 Timing Control Rx GRP 13 Test Control Rx GRP 13 Tx Test Pattern Rx GRP 14 Rx Test Pattern Rx GRP 14 SCCI Rx GRP 14 Rx Group ID Rx GRP 14 Status / Control ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Page Number page 243 page 220 page 221 page 222 ...
Page 154
... Tx GRP 18 First Link Address Tx GRP 18 Tx Group ID Tx GRP 18 Status / Control Tx GRP 18 Timing Control Tx GRP 18 Test Control Tx GRP 18 Tx Test Pattern Tx GRP 19 Rx Test Pattern ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Page Number page 228 page 229 page 230 ...
Page 155
... Receive UTOPIA Address 0x13 Cell Count MSBs Receive Groups 17–20 Configuration Tables Rx GRP 17 Configuration Rx GRP 17 Control Rx GRP 17 First Link Address Rx GRP 17 Rx Group ID Rx GRP 18 Configuration ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Page Number page 209 page 210 page 211 ...
Page 156
... Rx GRP 19 Rx Group ID Rx GRP 19 Status / Control Rx GRP 19 Timing Control Rx GRP 19 Test Control Rx GRP 19 Tx Test Pattern Rx GRP 20 Rx Test Pattern Rx GRP 20 SCCI ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Page Number page 221 page 222 page 223 page 220 ...
Page 157
... Tx GRP 23 Test Control Tx GRP 23 Tx Test Pattern Tx GRP 24 Rx Test Pattern Tx GRP 24 Control Tx GRP 24 First Link Address Tx GRP 24 Tx Group ID Tx GRP 24 Status / Control ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Page Number page 226 page 227 page 228 page 229 ...
Page 158
... Rx GRP 23 Configuration Rx GRP 23 Control Rx GRP 23 First Link Address Rx GRP 23 Rx Group ID Rx GRP 24 Configuration Rx GRP 24 Control Rx GRP 24 First Link Address Rx GRP 24 Rx Group ID ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Page Number page 213 page 214 page 215 page 216 ...
Page 159
... Rx GRP 24 Tx Test Pattern Transmit Groups 25–28 Configuration Tables Tx GRP 25 Rx Test Pattern Tx GRP 25 Control Tx GRP 25 First Link Address Tx GRP 25 Tx Group ID Tx GRP 25 Status / Control ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Page Number page 224 page 225 page 226 ...
Page 160
... Transmit UTOPIA Address 0x19 Cell Count MSBs Transmit UTOPIA Address 0x1A Cell Count LSBs Transmit UTOPIA Address 0x1A Cell Count MSBs Transmit UTOPIA Address 0x1B Cell Count LSBs Transmit UTOPIA Address 0x1B Cell Count MSBs ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Page Number page 213 ...
Page 161
... Rx GRP 25 Rx Group ID Rx GRP 25 Status / Control Rx GRP 25 Timing Control Rx GRP 25 Test Control Rx GRP 25 Tx Test Pattern Rx GRP 26 Rx Test Pattern Rx GRP 26 SCCI Rx GRP 26 Rx Group ID ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Page Number page 218 page 220 page 221 page 222 ...
Page 162
... Tx GRP 30 Control Tx GRP 30 First Link Address Tx GRP 30 Tx Group ID Tx GRP 30 Status / Control Tx GRP 30 Timing Control Tx GRP 30 Test Control Tx GRP 30 Tx Test Pattern ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Page Number page 227 page 228 page 229 page 230 ...
Page 163
... Receive UTOPIA Address 0x1F Cell Count LSBs Receive UTOPIA Address 0x1F Cell Count MSBs Receive Groups 29–32 Configuration Tables Rx GRP 29 Configuration Rx GRP 29 Control Rx GRP 29 First Link Address Rx GRP 29 Rx Group ID ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Page Number page 208 page 209 page 210 ...
Page 164
... Rx GRP 31 SCCI Rx GRP 31 Rx Group ID Rx GRP 31 Status / Control Rx GRP 31 Timing Control Rx GRP 31 Test Control Rx GRP 31 Tx Test Pattern Rx GRP 32 Rx Test Pattern ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Page Number page 220 page 221 page 222 page 223 ...
Page 165
... TxCellInt register (0x2C). When a logical 1 is read, this bit indicates a Receive Cell Interrupt. This interrupt is a summary interrupt and signifies that an interrupt indication occurred in the RxCellInt register (0x2D). ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Page ...
Page 166
... These interrupts can appear on the MicroInt* pin (pin AA1), provided that EnPortInt in the ENSUMPORT0-3 register (0x0F06, 0x0F08, 0x0F0A, 0x0F0C) is enabled for this port and EnIntPin (bit 3) in the GENCTRL register (0x0F00) is enabled. ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Description ...
Page 167
... Purpose In General Purpose Mode, the SPRxSync and SPTxSync pins are ignored. (However, good design practice would have them tied high.) ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Description Figure 1-12. During Figure 1-13. 110— ...
Page 168
... This bit when set to a logical 1 shifts the serial Tx data by 1/2 a cycle. This results in the Tx data being output a 1/2 SPTxClk cycle later than when the Tx inputs are sampled. This feature is disabled when set to 0. Reserved, set to 0. Reserved, set to 0. ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Description 153 ...
Page 169
... When written to a logical 1, this bit enables the Transmit DSS Scrambler. When written to a logical 0, the Transmit DSS Scrambler is disabled. When written to a logical 1, this bit enables the Receive DSS Scrambler. When written to a logical 0, the Receive DSS Scrambler is disabled. ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Description 154 ...
Page 170
... When written to a logical 1, this bit inserts a Cell Loss Priority (CLP) bit in the outgoing header from the TXHDR registers. When written to a logical 0, the CLP field is not changed prior to transmission. These bits hold the Transmit Idle Cell Payload values for outgoing idle cells. ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Description Description ...
Page 171
... When written to a logical 1, this bit disables Loss of Cell Delineation. When disabled, cells are passed even if cell delineation has not been found. When written to a logical 0, cells are passed only while cell alignment has been achieved. See ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Description ...
Page 172
... These bits are the Multi-PHY Device Address. Each M2852x port should have a unique address. These bits correspond to the URxAddr and UTxAddr pins. When the pin matches the bit values, the port is accessed. This port ignores any transactions meant for another port or PHY device. (1) ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Description Description ...
Page 173
... These bits hold the Transmit Header values for Octet 1 of the outgoing cell. Insertion of the bits is controlled by the HDRFIELD register (0x09). GFC/VPI bits (for UNI they are GFC bits, for NNI they are VPI bits) VPI bits ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Description Description 158 ...
Page 174
... HDRFIELD register (0x09). VPI bits VCI bits These bits hold the Transmit Header values for Octet 3 of the outgoing cell. Insertion of the bits is controlled by the HDRFIELD register (0x09). VCI bits ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Description Description 159 ...
Page 175
... These bits hold the Transmit Idle Cell Header values for Octet 1 of the outgoing cell. GFC/VPI bits (for UNI they are GFC bits, for NNI the are VPI bits) VPI bits ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Description Description ...
Page 176
... These bits hold the Transmit Idle Cell Header values for Octet 2 of the outgoing cell. VPI bits VCI bits These bits hold the Transmit Idle Cell Header values for Octet 3 of the outgoing cell. VCI bits ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Description Description 161 ...
Page 177
... These bits hold the Transmit Idle Cell Header values for Octet 4 of the outgoing cell. VCI bits Payload-type bits Cell Loss Priority bit These bits hold the Receive Header values for Octet 1 of the incoming cell. ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Description Description 162 ...
Page 178
... RxHdr3[ RxHdr3[0] 28529-DSH-001-K These bits hold the Receive Header values for Octet 2 of the incoming cell. These bits hold the Receive Header values for Octet 3 of the incoming cell. ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Description Description 163 ...
Page 179
... RxMsk1[ RxMsk1[0] 28529-DSH-001-K These bits hold the Receive Header values for Octet 4 of the incoming cell. These bits hold the Receive Header Mask for Octet 1 of the incoming cell. ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Description Description 164 ...
Page 180
... RxMsk3[ RxMsk3[0] 28529-DSH-001-K These bits hold the Receive Header Mask for Octet 2 of the incoming cell. These bits hold the Receive Header Mask for Octet 3 of the incoming cell. ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Description Description 165 ...
Page 181
... RxIdl1[0] 28529-DSH-001-K These bits hold the Receive Header Mask for Octet 4 of the incoming cell. These bits hold the Receive Idle cell header for Octet 1 of the incoming cell. ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Description Description 166 ...
Page 182
... RxIdl3[0] 28529-DSH-001-K These bits hold the Receive Idle cell header for Octet 2 of the incoming cell. These bits hold the Receive Idle cell header for Octet 3 of the incoming cell. ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Description Description 167 ...
Page 183
... IdlMsk1[0] 28529-DSH-001-K These bits hold the Receive Idle cell header for Octet 4 of the incoming cell. These bits hold the Receive Idle cell header mask for Octet 1 of the incoming cell. ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Description Description ...
Page 184
... These bits hold the Receive Idle cell header mask for Octet 2 of the incoming cell. These bits hold the Receive Idle cell header mask for Octet 3 of the incoming cell. ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Description Description ...
Page 185
... When written to a logical 1, this bit enables the Receive FIFO Overflow Interrupt. When written to a logical 1, this bit enables the Cell Sent Interrupt. Reserved for factory test, ignore. Reserved, set to a logical 0. Reserved, set to a logical 0. ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Description Description 170 ...
Page 186
... When a logical 1 is read, this bit indicates that a Receive FIFO Overflow occurred. When a logical 1 is read, this bit indicates that a cell has been sent. Reserved for factory test, ignore. Reserved, set to a logical 0. Reserved, write to a logical 0. ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Description Description 171 ...
Page 187
... UTOPIA FIFO. When a logical 1 is read, this bit indicates that a non-idle cell was formatted and transmitted. Reserved for factory test, ignore. Reserved, set to a logical 0. Reserved, set to a logical 0. ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Description Description 172 ...
Page 188
... Received cell counter bit 7. Received cell counter bit 6. Received cell counter bit 5. Received cell counter bit 4. Received cell counter bit 3. Received cell counter bit 2. Received cell counter bit 1. Received cell counter bit 0 (LSB). ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Description Description 173 ...
Page 189
... LOCD Event counter bit 7 (MSB). LOCD Event counter bit 6. LOCD Event counter bit 5. LOCD Event counter bit 4. LOCD Event counter bit 3. LOCD Event counter bit 2. LOCD Event counter bit 1. LOCD Event counter bit 0 (LSB). ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Description Description 174 ...
Page 190
... Transmitted cell counter bit 15. Transmitted cell counter bit 14. Transmitted cell counter bit 13. Transmitted cell counter bit 12. Transmitted cell counter bit 11. Transmitted cell counter bit 10. Transmitted cell counter bit 9. Transmitted cell counter bit 8. ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Description Description 175 ...
Page 191
... Received cell counter bit 7. Received cell counter bit 6. Received cell counter bit 5. Received cell counter bit 4. Received cell counter bit 3. Received cell counter bit 2. Received cell counter bit 1. Received cell counter bit 0 (LSB). ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Description Description 176 ...
Page 192
... Uncorrected HEC Error counter bit 5. Uncorrected HEC Error counter bit 4. Uncorrected HEC Error counter bit 3. Uncorrected HEC Error counter bit 2. Uncorrected HEC Error counter bit 1. Uncorrected HEC Error counter bit 0 (LSB). ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Description Description 177 ...
Page 193
... Non-matching cell counter bit 15 (MSB). Non-matching cell counter bit 14. Non-matching cell counter bit 13. Non-matching cell counter bit 12. Non-matching cell counter bit 11. Non-matching cell counter bit 10. Non-matching cell counter bit 9. Non-matching cell counter bit 8. ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Description Description 178 ...
Page 194
... OneSecIO pin for low-high-low. Part number controlled by bondout Port version - 0101 32 TC Port version - 1001 Version number of the device. Number starts at “0000” for the initial version ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Description Description 179 ...
Page 195
... For single Clav mode, UrxEnb[1] and UtxEnB[1] are not used but must be pulled up. Reserved, set to zero. Reserved, set to zero. The value written into these bits will be asserted on the StatOut[1:0] output pins. ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Description Description Description ...
Page 196
... When set, this bit enables PortInt[3] to appear on the MicroInt* output. When set, this bit enables PortInt[2] to appear on the MicroInt* output. When set, this bit enables PortInt[1] to appear on the MicroInt* output. When set, this bit enables PortInt[0] to appear on the MicroInt* output. ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Description Description ...
Page 197
... When set, this bit enables PortInt[11] to appear on the MicroInt* output. When set, this bit enables PortInt[10] to appear on the MicroInt* output. When set, this bit enables PortInt[9] to appear on the MicroInt* output. When set, this bit enables PortInt[8] to appear on the MicroInt* output. ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Description Description ...
Page 198
... When set, this bit enables PortInt[19] to appear on the MicroInt* output. When set, this bit enables PortInt[18] to appear on the MicroInt* output. When set, this bit enables PortInt[17] to appear on the MicroInt* output. When set, this bit enables PortInt[16] to appear on the MicroInt* output. ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Description Description ...
Page 199
... When set, this bit enables PortInt[25] to appear on the MicroInt* output. When set, this bit enables PortInt[24] to appear on the MicroInt* output. These bits can be written and read by the system. These bits are not used for any purpose inside the device. ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Description Description ...
Page 200
... When set, this bit enables fractional T1/E1 logic for TC port 7. When set, this bit enables fractional T1/E1 logic for TC port 6. When set, this bit enables fractional T1/E1 logic for TC port 5. When set, this bit enables fractional T1/E1 logic for TC port 4. ® Mindspeed Technologies Mindspeed Proprietary and Confidential Registers Description Description ...