M28529G-12 Mindspeed Technologies, M28529G-12 Datasheet - Page 86

• Manufacturer Part Number: M28529G-12
• Description: ATM IMA 8.192Mbps 1.8V/3.3V 484-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of M28529G-12

• Package: 484BGA
• Utopia Type: Level 2
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.71|3.135 V
• Maximum Operating Supply Voltage: 1.89|3.465 V
• Maximum Output Rate: 8.192 Mbps

Table 1-19.
28529-DSH-001-K
Serial Port Synchronizer
IMA_SysClk Dividers
IMA_RefClk Synchronizer
IDCR Source Mux
Rx IDCR Clock
Tx IDCR Clock
Bit Rate Clock Generator
Digital Phase Locked Loop
Clock Section
IMA Block Clock Sections
This block contains a transition detector and a synchronizer. It synchronizes the clocks from the TC block Serial ports to
the IMA_SysClk divided by 16 and the rate multiplier (RM). It handles all 32 internal serial ports independently. The rate
multiplier is configured to values 1, 2, or 4 based on the range of the link rate.
This block contains two dividers: a divide by 16, a divide by 24, and divide by rate multiplier (RM). The divide_16 is
used to synchronize external clocks to internal logic. The divide_24 allows the IMA_SysClk to be used to generate both
the Rx IDCR and the Tx IDCR clocks (provided that IMA_SysClk is 24 times the bit rate).
This block contains a transition detector and a synchronizer. It synchronizes the IMA_RefClk to the IMA_SysClk divided
by 16 and the RM factor.
This software controlled mux selects which clock sources are feed to the appropriate IDCR clock dividers.
This block divides the bit rate clock down to a link cell data rate clock based on the values of frame length (M), number
of links in the group (N), frame payload (P) and frame bit (F), then adjusts based on the rate multiplier (RM). (The 2048/
2049 factor results from the IMA standards requirement of inserting a stuff event every 2048 cells.) This block can
generate 16 independent Rx IDCR clock outputs (one per group).
This block divides the bit rate clock down to a Link cell data rate clock based on the values of frame length (M), number
of links in the group (N), frame payload (P) and frame bit (F), then adjusts based on the rate multiplier (RM). (The 2048/
2049 factor results from the IMA standards requirement of inserting a stuff event every 2048 cells.) This block can
generate 16 independent Rx IDCR clock outputs (one per group).
This block generates a clock that represents the link data rate. It can generate 16 independent Tx and 16 independent Rx
clocks. In normal operation, all parameters are configured automatically by the software driver. It contains the following
blocks:
• Pre-scaler—This block divides the selected input (either IMA_RefClk or IMA_SysClk) by the factor of Pnum divided
• Synchronizer—Synchronizes the Pre-Scaler output to the internal logic using the IMA_SysClk divided by 16 and the
• Numerically Controlled Oscillator—This clock circuit generates the link bit rate.
This block generates a bit rate clock that is phase locked to the PHY side RxClAv signal. It can monitor all 32 ports on
the bus. Any port can be selected as the group timing reference.
by Pden.
RM factor.
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