M28529G-12 Mindspeed Technologies, M28529G-12 Datasheet - Page 100

• Manufacturer Part Number: M28529G-12
• Description: ATM IMA 8.192Mbps 1.8V/3.3V 484-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of M28529G-12

• Package: 484BGA
• Utopia Type: Level 2
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.71|3.135 V
• Maximum Operating Supply Voltage: 1.89|3.465 V
• Maximum Output Rate: 8.192 Mbps

With regard to IMA, each IMA group is considered one logical port and will only take up one UTOPIA address. For
example, a group with 8 T1 links could be assigned to address 0; the IMA engine handles the translation between
the ATM layer and the physical links. In addition, each pass-though connection also requires one address.
To provide maximum flexibility for system design the M28529 has 3 UTOPIA Level 2 interface modes. This allows
the M28529 to be used in either UTOPIA-to-UTOPIA or UTOPIA-to-Serial IMA applications or it can function as a
stand-alone cell delineator block. These interfaces are shown in
1. IMA direct—This interface allows the ATM layer to interface directly to the IMA engine. This would be the
2. TC block direct—This interface is selected when the IMA engine is disabled and the device is being used as a
3. PHY side UTOPIA—This interface is selected when the TC block is disabled and the designer wishes to
1.13.1
Three primary functions are performed by the UTOPIA controller: polling, selection, and data transfer. These
functions are basically the same for both the transmit and receive sides of the UTOPIA bus. The following example
describes the transmit functions. Refer to
The ATM layer UTOPIA controller polls the connected PHY ports by transmitting the port addresses on the
UTxAddr lines. If a port is ready to transfer data, it asserts UTxClAv. Note that the process of polling a port does
NOT result in that port being selected to transfer data! Polling allows the controller to determine which port is ready
for data; it must then select that port before sending data. It does so by reasserting the desired address and then
asserting UtxEnb*. The PHY will then be ready to transfer data on the UTxData lines. UTxEnb* is deasserted when
the transfer is completed. Polling can continue during the data transfer process but not during port selection. It
operates independently of the state of UTxEnb*.
To pause the data transfer, UTxEnb* can be deasserted. To continue the transfer, the controller must reselect the
port by transmitting its address one clock cycle before asserting UTxEnb*. The controller must ensure that the cell
transfer from this port has been completed, to avoid a start-of-cell error.
On the ATM side, the UTOPIA interface is a slave. On the PHY side, the UTOPIA interface is a master.
1.13.2
The ATM side UTOPIA interface on the M2852x devices have two bus width options, 8-bit or 16-bit, depending on
the selection of AtmBusWidth, bit 5, of the ATMINTFC register (0xF03). The PHY side UTOPIA interface also has
two bus width options 8-bit or 16-bit, depending on the selection of PHYBusWidth, bit 5, of the PHYINTFC register
(0xF02).
The protocols and timing are the same in both modes, except that 8-bit mode uses only the lower half of the data
bus (TxData[7:0] and RxData[7:0]) and odd parity is only generated or checked over those bits. The ATM-Side
UTOPIA Level 2 interface operates up to 50 MHz in 16 bit mode (Note: 33 MHz for TC Mode Only) and 33 MHz in
8 bit mode. The PHY-Side UTOPIA interface operates at half the IMA_Sysclk rate (IMA_SysClk/2)
28529-DSH-001-K
normal mode for all IMA applications. It is controlled by registers in the IMA section.
stand-alone cell delineator. It may also be invoked during troubleshooting to verify serial port operation without
having to run the IMA drivers. It is configured by registers in the TC section.
interface to a device via an UTOPIA interface. This allows the M28529 IMA engine to address up to 32 ports on
the line side.
NOTE:
General UTOPIA Operation
UTOPIA 8-bit and 16-bit Bus Widths (PHY and ATM)
By convention, data being transferred from the PHY to the ATM layer
is considered received data, while data from the ATM layer to the
PHY is called transmitted data.
Mindspeed Proprietary and Confidential
Mindspeed Technologies
Figure
1-24.
Figure 1-26
®
and described below.
Functional Description
85