M28529G-12 Mindspeed Technologies, M28529G-12 Datasheet - Page 107

• Manufacturer Part Number: M28529G-12
• Description: ATM IMA 8.192Mbps 1.8V/3.3V 484-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of M28529G-12

• Package: 484BGA
• Utopia Type: Level 2
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.71|3.135 V
• Maximum Operating Supply Voltage: 1.89|3.465 V
• Maximum Output Rate: 8.192 Mbps

Functional Description
Figure 1-28. Header Error Check Process
Cell Delineation in Sync State
Errors Detected
(Drop Cell)
No Errors Detected
No Errors Detected (Pass Cell)
Detection
(Pass Cell)
Mode
Apparent Single-bit Error
(Correct Error and Pass Cell)
Correction
Mode
Apparent Multi-bit Error (Drop Cell)
500027_007
When the M2852x is in general purpose mode, a synchronization pulse from the framer interface is not always
available. In this mode, the M2852x performs a bit serial search to find byte and cell alignment. The M2852x
selects a starting window of 32 sequential bits and calculates the HEC over this window. This HEC is then
compared to the next eight incoming bits. If they do not match, the M2852x shifts the 32-bit window by 1 bit and
recalculates the HEC until a valid HEC position is found. Once byte-alignment is achieved, cell delineation is
performed.
1.14.2.2
Cell Delineation Control Modes
The M28529 contains two independent “HEC Check” state machines. The Cell Delineator (CD) State Machine is
used to find Cell Delineation and, conversely, to declare loss of cell delineation (LOCD). The other is the Cell Valid
(CV) State Machine, which is used to validate the cells to pass to the UTOPIA FIFOs.
These state machines are controlled by two register bits, (CVAL register, 0x0C), that allow the M28529 to be
programmed for special applications.
Table 1-26
shows the control bits function.
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