M28529G-12 Mindspeed Technologies, M28529G-12 Datasheet - Page 35

• Manufacturer Part Number: M28529G-12
• Description: ATM IMA 8.192Mbps 1.8V/3.3V 484-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of M28529G-12

• Package: 484BGA
• Utopia Type: Level 2
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.71|3.135 V
• Maximum Operating Supply Voltage: 1.89|3.465 V
• Maximum Output Rate: 8.192 Mbps

Table 1-9.
28529-DSH-001-K
StatOut[0]
StatOut[1]
MSyncMode
Reset*
8kHzIn
OneSecIO
MW/R, MRd*
MCS*
Pin Label
M28529 Pin Descriptions (1 of 19)
Status Output
Microprocessor
Synchronous/
Asynchronous Bus Mode
Select
Device Reset
8 kHz Input
One-Second Input/Output
Microprocessor Write/
Read
Microprocessor Chip
Select
Signal Name
Mindspeed Proprietary and Confidential
Mindspeed Technologies
AD26
AD25
AB24
AE24
AE26
No.
W4
T4
V1
I/PD
I/PU
I/O
I/O
O
I
I
I
General purpose output pins under software control.
Selects synchronous or asynchronous bus mode, which
determines the functions of two pins, MW/R,MRd* (pin W4) and
MAS*,MWr* (pin Y2). A logic 1 selects the synchronous bus
mode. In this mode, these pins are defined as follows: MW/R (W4)
and MAS* (Y2). A logic 0 selects the asynchronous SRAM-type
bus mode. In this mode, the pins are defined as follows: MRd*
(W4) and MWr* (Y2).
When asserted low, resets the device. The microprocessor clock
must be present before reset is released. If configuring the device
for pass-through operation, a minimum delay of 25 uS for
IMA_Sysclk of 66 MHz or 33us for IMA_Sysclk of 50 MHz is
required from the release of reset to the first access of the
IMA_RX_TRANS_TABLE register or the
IMA_RX_ATM_TRANS_TABLE register (0x818/0x819).
A clock input used to derive OneSecIO. Typically operates at a
frequency of 8 kHz.
Software can configure this pin as an output that equals the input
from the 8kHzIn divided by 8000. When configured as an input,
status registers and counters may be latched on the rising edge of
this input. See Bit 0 of the Genctrl register (0xF00).
When MSyncMode is asserted high, this pin is a read/write control
pin. In this mode, when MW/R is asserted high, a write access is
enabled and the MicroData[7:0] pin values will be written to the
memory location indicated by the MicroAddr[11:0] pins. Also,
when MW/R is asserted low in this mode, a read access is enabled
and the memory location indicated by the MicroAddr[11:0] pins is
read. Its value is placed on the MicroData[7:0] pins. Both read and
write accesses assume the device is chip selected (MCS* = 0), the
address is valid (MAS* = 0), and the device is not being reset
(Reset* = 1).
When MSyncMode is asserted low, this pin is a read control pin. In
this mode, when MRd* is asserted low, a read access is enabled
and the memory location indicated by the MicroAddr[11:0] pins is
read. Its value is placed on the MicroData[7:0] pins.
When asserted low, the device is selected for read and write
accesses. When asserted high, the device will not respond to input
signal transitions on MicroClk, MW/R, MRd*, or MAS*, MWr*.
Additionally, when MCS* is asserted high, the MicroData[7:0] pins
are in a high-impedance state but the MicroInt* pin remains
operational.
®
Description
Functional Description
20