M28529G-12 Mindspeed Technologies, M28529G-12 Datasheet - Page 130

• Manufacturer Part Number: M28529G-12
• Description: ATM IMA 8.192Mbps 1.8V/3.3V 484-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of M28529G-12

• Package: 484BGA
• Utopia Type: Level 2
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.71|3.135 V
• Maximum Operating Supply Voltage: 1.89|3.465 V
• Maximum Output Rate: 8.192 Mbps

Table 2-3.
Table 2-4
Table 2-4.
Table 2-5
28529-DSH-001-K
Footnote:
(1) One-second latching is enabled by setting EnStatLat (bit 5) in the GENCTRL register (0xF00) to a logical 1.
(2) One-second latching is enabled by setting EnCntrLat (bit 4) in the MODE register (0xF00) to a logical 1.
Port Offset
Port Offset
Address
Address
0x33
0x34
0x35
0x37
0x38
0x39
0x3B
0x3C
0x3D
0x3E
0x08
0x09
0x0A
0x0B
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x3F
lists the control registers used for transmission of traffic.
lists the control registers used for reception of traffic.
LOCDCNT
TXCNTL
TXCNTH
CORRCNT
RXCNTL
RXCNTH
UNCCNT
NONCNTL
NONCNTH
CGEN
HDRFIELD
IDLPAY
ERRPAT
TXHDR1
TXHDR2
TXHDR3
TXHDR4
TXIDL1
TXIDL2
TXIDL3
TXIDL4
Port Control and Status Registers (3 of 3)
Cell Transmit Registers
Name
Name
—
—
Cell Generation Control Register
Header Field Control Register
Transmit Idle Cell Payload Control Register
Error Pattern Control Register
Transmit Cell Header Control Register 1
Transmit Cell Header Control Register 2
Transmit Cell Header Control Register 3
Transmit Cell Header Control Register 4
Transmit Idle Cell Header Control Register 1
Transmit Idle Cell Header Control Register 2
Transmit Idle Cell Header Control Register 3
Transmit Idle Cell Header Control Register 4
Type
—
—
R
R
R
R
R
R
R
R
R
Mindspeed Proprietary and Confidential
Mindspeed Technologies
One-second
Latching
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
—
—
LOCD Event Counter
Transmitted Cell Counter (low byte)
Transmitted Cell Counter (high byte)
Corrected HEC Error Counter
Received Cell Counter (low byte)
Received Cell Counter (high byte)
Uncorrected HEC Error Counter
Non-Matching Cell Counter (low byte)
Non-Matching Cell Counter (high byte)
Reserved, set to a logical 0
Reserved, set to a logical 0
Description
Description (Continued)
®
Registers
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Number
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Number
Page
Page
—
—
115