CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet

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CN8236 ATM ServiceSAR Plus with xBR Traffic Management The CN8236 Service Segmentation and Reassembly Controller integrates ATM terminal functions, PCI Bus Master and Slave controllers, and a UTOPIA level interface with service-specific functions in a single package ...

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... The following are trademarks of Conexant Systems, Inc.: Mindspeed Technologies™, the Mindspeed™ logo, and “Build It First”™. Product names or services listed in this publication are for identification purposes only, and may be trademarks of third parties. ...

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... Mindspeed provides an evaluation environment for the CN8236/RS8254EVM which provides a working reference design, an example of a software driver, and facilities for generating and terminating all service categories of ATM traffic. This system accelerates ATM system development by providing a rapid prototyping environment. 28236-DSH-001-B Mindspeed Technologies ™ ...

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... Rx FIFO buffer full – Frame relay DE with priority threshold – LECID filtering and echo suppression – Per-VCC firewalls Mindspeed Technologies ™ • Dynamic channel lookup (NNI or UNI addressing) – Supports full address space – Deterministic – Flexible VCI count per VPI – ...

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... Boundary scan for board-level testing • Source loopback, for diagnostics • Glueless connection to Mindspeed’s ATM physical layer device, the RS825x and Bt8223 Standards Compliance • UNI/NNI 3.1 • TM 4.0/TM4.1 • Bellcore GR-1248 • ATM Forum B-ICI V2.0 28236-DSH-001-B Mindspeed Technologies ™ ...

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... Mindspeed Technologies ™ ...

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... Automated Segmentation Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 Automated Reassembly Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2.4 2.5 Advanced xBR Traffic Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2.5.1 CBR Traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 2.5.2 VBR Traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 2.5.3 ABR Traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 2.5.4 UBR Traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 2.5.5 GFR Traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 28236-DSH-001 1 2-1 Mindspeed Technologies ™ 7 ...

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... VCC Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.2.2 Submitting Segmentation Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.2.2.1 User Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.2.2.2 Buffer Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.2.2.3 Host Linked Segmentation Buffer Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.2.2.4 Transmit Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 8 ATM ServiceSAR Plus with xBR Traffic Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Mindspeed Technologies ™ CN8236 28236-DSH-001-B ...

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... AAL5 COM Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 5.3.1.2 AAL5 EOM Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 5.3.1.3 AAL5 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 5.3.2 AAL3/4 Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 5.3.2.1 AAL3/4 Per-Cell Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 5.3.2.2 AAL3/4 Additional BOM/SSM Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 5.3.2.3 AAL3/4 Additional COM Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 28236-DSH-001 5-1 Mindspeed Technologies ™ Table of Contents 9 ...

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... Virtual FIFO Buffer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28 5.4.10.1 Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28 5.4.10.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28 5.4.10.3 Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28 5.4.11 Firewall Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29 5.4.11.1 Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29 5.4.11.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29 5.4.11.3 Credit Return . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29 10 ATM ServiceSAR Plus with xBR Traffic Management Mindspeed Technologies ™ CN8236 28236-DSH-001-B ...

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... CBR Cell Delay Variation (CDV 6-16 6.2.3.4 CBR Channel Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18 6.2.4 VBR Traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19 6.2.4.1 Mapping CN8236 VBR Service Categories to TM 4.1 VBR Service Categories . . 6-19 6.2.4.2 Rate-Shaping vs. Policing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19 6.2.4.3 Single Leaky Bucket . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19 28236-DSH-001-B Mindspeed Technologies ™ Table of Contents 11 ...

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... Schedule Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-44 6.5.2 CBR-Specific Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-44 6.5.2.1 CBR Traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-44 6.5.2.2 Tunnel Traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-44 6.5.2.3 SCH_STATE Fields For CBR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-45 6.5.3 VBR-Specific Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-46 6.5.3.1 VBR SCH_STATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-46 12 ATM ServiceSAR Plus with xBR Traffic Management Mindspeed Technologies ™ CN8236 28236-DSH-001-B ...

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... Reassembly of Forward Monitoring PM Cells . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14 7.4.3.3 Reassembly of Backward Reporting PM Cells . . . . . . . . . . . . . . . . . . . . . . . . . 7-14 7.4.3.4 Turnaround and Segmentation of Backward Reporting PM Cells . . . . . . . . . . . . 7-14 7.4.3.5 Turnaround of Backward Reporting PM Cells ONLY . . . . . . . . . . . . . . . . . . . . . 7-14 7.4.4 Error Conditions During PM Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14 7.4.5 PASS_OAM Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14 28236-DSH-001-B Mindspeed Technologies ™ Table of Contents 13 ...

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... Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.2 Unimplemented PCI Bus Interface Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 11.3 PCI Configuration Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 11.4 PCI Bus Master Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 11.5 Burst FIFO Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 14 ATM ServiceSAR Plus with xBR Traffic Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 10-1 Mindspeed Technologies ™ CN8236 28236-DSH-001-B ...

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... Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 14.1 System Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4 14.2 14.3 Segmentation Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9 Scheduler Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-12 14.4 14.4.1 0xc4—PCR Queue Interval 2 and 3 Register (PCR_QUE_INT23 14-18 14.5 Reassembly Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-19 28236-DSH-001 12-1 Mindspeed Technologies ™ Table of Contents 15 ...

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... A-1 A.1 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3 BYPASS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4 A.2 A.3 Boundary Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4 Boundary Scan Register Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5 A.4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-13 A.5 16 ATM ServiceSAR Plus with xBR Traffic Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 16-1 Mindspeed Technologies ™ CN8236 28236-DSH-001-B ...

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... CN8236 ATM ServiceSAR Plus with xBR Traffic Management A.6 Boundary Scan Description Language (BSDL) File A-15 Appendix B: List of Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31 28236-DSH-001-B Mindspeed Technologies ™ Table of Contents 17 ...

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... Table of Contents 18 ATM ServiceSAR Plus with xBR Traffic Management Mindspeed Technologies ™ CN8236 28236-DSH-001-B ...

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... AAL5 Processing—CRC and PDU Length Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 Figure 5-10. AAL3/4 CPCS—PDU Reassembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 Figure 5-11. AAL0 PTI PDU Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 Figure 5-12. Host and SAR-Shared Memory Data Structures for Scatter Method . . . . . . . . . . . . . . . . . 5-19 Figure 5-13. Free Buffer Queue Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20 28236-DSH-001-B Mindspeed Technologies ™ List of Figures 19 ...

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... Figure 10-5. Local Processor Single Write with One Wait State by_16 SRAM 10-9 Figure 10-6. Local Processor Quad Write, No Wait States 10-10 Figure 10-7. i960CA/CF to the CN8236 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12 20 ATM ServiceSAR Plus with xBR Traffic Management Mindspeed Technologies ™ CN8236 28236-DSH-001-B ...

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... Local Processor Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-17 Figure 16-14. Local Processor Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-18 Figure 16-15. 388-Pin Ball Grid Array Package (BGA 16-23 Figure 16-16. CN8236 Pinout Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-24 Figure A-1. Test Circuitry Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2 Figure A-2. Timing Diagram A-14 28236-DSH-001-B Mindspeed Technologies ™ List of Figures 21 ...

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... List of Figures 22 ATM ServiceSAR Plus with xBR Traffic Management Mindspeed Technologies ™ CN8236 28236-DSH-001-B ...

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... VPI Index Table Entry Format with EN_PROG_BLK_SX(RSM_CTRL1) Enabled . . . . . . . . . 5-37 Table 5-6. VPI Index Table Entry Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-38 Table 5-7. Normal VCI Index Table Format 5-38 Table 5-8. VCI Index Table Format with EN_PROG_BLK_SZ (RSM_CTRL1) Enabled . . . . . . . . . . . . . 5-38 Table 5-9. VCI Index Table Descriptions 5-38 28236-DSH-001-B Mindspeed Technologies ™ List of Tables 23 ...

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... SCH_STATE for SCH_MODE = GFR 6-49 Table 6-17. SCH_STATE Field Descriptions for SCH_MODE = GFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-49 Table 6-18. GFR MCR Limit Bucket Table Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-50 Table 6-19. GFR MCR Bucket Table Entry Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-50 24 ATM ServiceSAR Plus with xBR Traffic Management Mindspeed Technologies ™ CN8236 28236-DSH-001-B ...

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... Processor Interrupt Status Register 1 (HOST_ISTAT1 14-31 Table 14-5. 0x1d0—Host Interrupt Mask Register 0 (HOST_IMASK0 14-32 Table 14-6. 0x1d4—Host Interrupt Mask Register 1 (HOST_IMASK1 14-33 Table 14-7. 0x1e0—Local Processor Interrupt Status Register 0 (LP_ISTAT0 14-35 28236-DSH-001-B Mindspeed Technologies ™ List of Tables 25 ...

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... Table 16-15. Spare Pins Reserved for Inputs 16-32 Table A-1. Boundary Scan Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 Table A-2. IEEE Std. 1149.1 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3 Table A-3. Boundary Scan Register Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5 Table A-4. Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-13 26 ATM ServiceSAR Plus with xBR Traffic Management Mindspeed Technologies ™ CN8236 28236-DSH-001-B ...

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... This architecture lessens the control burden on the host system and minimizes Peripheral Component Interconnect (PCI) bus utilization by eliminating reads across the PCI bus from host control activities. 28236-DSH-001-B 1 (MCR) on UBR Virtual Channel Connections (VCCs) Mindspeed Technologies ™ 1-1 ...

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... The CN8236’s on-chip coprocessor blocks are surrounded by high performance PCI and UTOPIA ports for glueless interface to a variety of system components with full line rate throughput and low bus occupancy. illustrates these functional blocks. 1-2 ATM ServiceSAR Plus with xBR Traffic Management Mindspeed Technologies ™ CN8236 Figure 1-1 28236-DSH-001-B ...

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... Scheduler / Domain) ABR Flow Control Mgr. Local Bus xBR Traffic Interface Manager Clock/ Memory Timer and Arbiter (32 bit) 60 Local Bus Mindspeed Technologies ™ 1.0 CN8236 Product Overview 1.1 Introduction Rx Physical 26 FIFO Rx (Depth = Port ATM 256 bytes) Physical Receive Interface Tx FIFO ...

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... Receive FIFO buffer full condition/threshold. • Various AAL3/4 Management Information Base (MIB) errors. 1-4 ATM ServiceSAR Plus with xBR Traffic Management 2.0, and are fully described in succeeding chapters. and the channel exceeding a user-defined priority threshold. data frames on ELAN channels. Mindspeed Technologies ™ CN8236 28236-DSH-001-B ...

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... VCC whose rate has dropped below the Schedule table minimum rate. segmentation status queue for the host monitoring functions. (This is the mode recommended by the Internet Engineering Task Force [IETF] as the most convenient model for IP over ATM interworking.) Mindspeed Technologies ™ 1.0 CN8236 Product Overview 1-5 ...

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... The HLED* output open drain capable of driving an LED directly. A logic low illuminates the LED. The HENUM* output open drain in compliance with the ENUM# signal defined in the CompactPCI specification. 1-6 ATM ServiceSAR Plus with xBR Traffic Management Mindspeed Technologies ™ CN8236 28236-DSH-001-B ...

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... CN8236. This software is written in C, and Source code is available under license agreement. The evaluation environment also includes a full set of design schematics, and artwork for the CN8236EVM PCI card. 28236-DSH-001-B Mindspeed Technologies ™ 1.0 CN8236 Product Overview 1.3 Designer Toolkit 1-7 ...

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... CN8236 Product Overview 1.3 Designer Toolkit 1-8 ATM ServiceSAR Plus with xBR Traffic Management Mindspeed Technologies ™ CN8236 28236-DSH-001-B ...

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... Traffic Manager. The remaining sections cover Operation and Maintenance and Performance Monitoring (OAM/PM), the various device inputs and outputs, and the logic diagram with pin descriptions. This architectural overview serves as a solid foundation for understanding the complete functionality of the CN8236. 28236-DSH-001-B 2 Mindspeed Technologies ™ 2-1 ...

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... ATM services. shows that clients can be multiple applications in a shared memory, or separate PHY entities. All communicate directly with the CN8236. 2-2 ATM ServiceSAR Plus with xBR Traffic Management Figure 2-1 illustrates this client/server model. It Mindspeed Technologies ™ CN8236 28236-DSH-001-B ...

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... SAR that the host cannot read or write. 28236-DSH-001-B 2.2 High Performance Host Architecture with Buffer Isolation CN8236 Subsystem ATM Server LEGEND: buffer queue. illustrates the location of each queue. Mindspeed Technologies ™ 2.0 Architecture Overview ATM User-Network Interface Host Data Path Host Control/Status Flow ...

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... Status queues may be optionally placed in SAR-shared memory. 2-4 ATM ServiceSAR Plus with xBR Traffic Management segmentation status queue reassembly status queue Segmentation Function RSM/SEG Queue CN8236 Reassembly Function Mindspeed Technologies ™ CN8236 SAR-Shared Memory Area Transmit Queues (32) Free Buffer Queues Global OAM (32) ...

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... High Performance Host Architecture with Buffer Isolation CN8236 Reassembly Block Segmentation Block Free Buffer Queues RSM/SEG Queue Global OAM Free Buffer Queue Mindspeed Technologies ™ 2.0 Architecture Overview Figure 2-3 illustrates LEGEND: Write Read xBR Scheduler Local Memory Interface ...

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... PDU. Host (or optionally Local) Memory RSM Buffer Descriptors (Write (SAR 3 Links Buffer Descriptors for the PDU.) Mindspeed Technologies ™ CN8236 PCI CN8236 RSM Coprocessor RSM Memory (Write) (Read) Free Buffer (Write) Queues (32) 8236_004 28236-DSH-001-B ...

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... The transmit queue acts as a FIFO buffer for segmentation task pointers. PCI (Read) SEG Buffer Descriptors (Write) Mindspeed Technologies ™ 2.0 Architecture Overview CN8236 SEG Coprocessor SEG Memory (Read) (Read) Transmit Queues 8236_005 ...

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... ATM ServiceSAR Plus with xBR Traffic Management illustrates the association between the segmentation status queues PCI Transmit Queues Host Writes Transmit Queue Entry Host Writes SBD SAR Writes SEG Status Queue Entry Mindspeed Technologies ™ CN8236 SEG Buffer Descriptors (Buffer Descriptors Linked by Host) SAR-Shared Memory 8236_006 28236-DSH-001-B ...

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... High Performance Host Architecture with Buffer Isolation illustrates the association between the reassembly status queues PCI Host WritesFree Buffer Queue Entry RSM Status Queues SAR Writes RSM Status Queue Entry Mindspeed Technologies ™ 2.0 Architecture Overview Free Buffer Queues SAR-Shared Memory 8236_007 2-9 ...

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... ATM ServiceSAR Plus with xBR Traffic Management illustrates the CN8236’s write-only PCI control architecture. The host PCI Control RSM Data (Writes) Status SEG Data (Read Multiples) as reads take many more clock cycles. Mindspeed Technologies ™ CN8236 CN8236 8236_008 28236-DSH-001-B ...

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... This has value when the SAR resides in an environment in which the host is not dedicated to data communications processing. 28236-DSH-001-B 2.2 High Performance Host Architecture with Buffer Isolation Mindspeed Technologies ™ 2.0 Architecture Overview 2-11 ...

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... ATM cell headers, but generates no other overhead fields. segmentation, where the segmentation coprocessor reads the entire 52-octet ATM cell from the segmentation buffer and does not generate the ATM headers for the cells. PHY interface for transmission. Mindspeed Technologies ™ CN8236 28236-DSH-001-B ...

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... The CN8236 writes segmentation status queue entries on either PDU boundaries or buffer boundaries, selectable on a per-VCC basis. PDU boundary status reporting is called Message Mode, while buffer status reporting is called Streaming Mode. 28236-DSH-001-B Mindspeed Technologies ™ 2.0 Architecture Overview 2.3 Automated Segmentation Engine 2-13 ...

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... Payload Type Identifier (PTI) termination, where the PTI bit in the cell header is monitored for the End of Message (EOM) cell indication. Cell Count termination, where the CN8236 terminates the PDU when a user-defined number of cells have been received on that channel. Mindspeed Technologies ™ CN8236 28236-DSH-001-B ...

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... Type error), SN_ERR (Sequence Number error), and LI_ERR (SAR-PDU Length error). Mindspeed Technologies ™ 2.0 Architecture Overview 2.4 Automated Reassembly Engine 2-15 ...

Page 50

... Each virtual channel is prioritized according to its assigned scheduling priority. CBR channels are given pre-assigned segmentation bandwidth, and channels for the remaining service categories scheduled according to their priority number (priority 0 being the lowest priority and priority 15 being highest). Mindspeed Technologies ™ CN8236 Figure 2-9. ...

Page 51

... Tx FIFO buffer empties. (2) SAR Segmentation Coprocessor (5) Start (3) Next Tx VCC ID # xBR Traffic Manager Conforming VCC ID # Schedule Table ABR Templates 16 UBR/VBR/ABR Priority Queues Mindspeed Technologies ™ 2.0 Architecture Overview 2.5 Advanced xBR Traffic Management Tx FIFO Buffer To PHY Full/Empty UBR/VBR/ABR VCC ID # CBR (4) 8236_009 2-17 ...

Page 52

... VBR1 controls PCR and CDVT. VBR2 controls PCR and CDVT, as well as Sustained Cell Rate (SCR) and Burst Tolerance (BT). VBRC (also called VBR3) controls PCR and CDVT on all cells, but controls SCR on only CLP = 0 (high priority) cells. 2-18 ATM ServiceSAR Plus with xBR Traffic Management Mindspeed Technologies ™ CN8236 28236-DSH-001-B ...

Page 53

... The CN8236 implements GFR by scheduling/shaping the connections using both the VBR1 scheduling procedure (for the MCR rate value) and a UBR priority queue, thereby providing fair sharing for all GFR connections to excess bandwidth. 28236-DSH-001-B Mindspeed Technologies ™ 2.0 Architecture Overview 2.5 Advanced xBR Traffic Management 2-19 ...

Page 54

... ATM ServiceSAR Plus with xBR Traffic Management Per-VCC rate control guarantees conformance to GCRA UPC/policing Dynamic reallocation of link bandwidth to active channels Dynamic, fair sharing of bandwidth on oversubscribed lines Multiple scheduling priorities Fine-grained rate control Rate based on a user-supplied reference clock Mindspeed Technologies ™ CN8236 28236-DSH-001-B ...

Page 55

... The programmability of the templates insulates the hardware from changes in TM 4.1 specification. Mindspeed provides the initial templates, which can be customized by the user later, shortening developmen t t Mindspeed Technologies ™ 2.0 Architecture Overview 2.5 Advanced xBR Traffic Management ime. 2-21 ...

Page 56

... CONFIG1 bit 1). words cells) . See Section 4.2.4. coprocessor (64 words). illustrates the data FIFO buffer. 16 Segmentation Controller Transmit PHY Interface FIFO 512 Reassembly Controller Receive PHY Interface FIFO PCI Slave 8 64 Mindspeed Technologies ™ CN8236 Cells PHY Interface 64 8236_097 28236-DSH-001-B ...

Page 57

... UTOPIA Level 1 and Level 2 standards for ATM Layer devices. Slave UTOPIA mode reverses the control direction for use in place of a PHY on switch fabrics. 28236-DSH-001 Interface module that allows the Mindspeed Technologies ™ 2.0 Architecture Overview 2.7 Implementation of OAM-PM Protocols 2-23 ...

Page 58

... The CN8236 includes five pins for Joint Test Action Group (JTAG) Boundary Scan, for board-level testing. The CN8236 incorporates an internal loopback from the segmentation coprocessor to the reassembly coprocessor to facilitate system diagnostics. 2-24 ATM ServiceSAR Plus with xBR Traffic Management Mindspeed Technologies ™ CN8236 28236-DSH-001-B ...

Page 59

... Any I/O (except PCI) that requires a pullup must be tied through a resistor to 3.3 V and not 5 V. 2.10 Logic Diagram and Pin Descriptions A functionally partitioned logic diagram of the CN8236 is illustrated in Figure Table 28236-DSH-001-B 2-11. Pin descriptions, names, and input/output assignments are detailed in 2-1. Mindspeed Technologies ™ 2.0 Architecture Overview 2.9 Electrical/Mechanical 2-25 ...

Page 60

... HFIFORD5 HFIFOWR5 Interworking A25 HFIFORD4 HFIFOWR4 Signals D23 HFIFORD3 HFIFOWR3 C24 HFIFORD2 HFIFOWR2 B26 HFIFORD1 HFIFOWR1 C25 HFIFORD0 HFIFOWR0 Mindspeed Technologies CN8236 Y26 O Arbiter Bus Request AA25 OD Interrupt Request L23 OD System Error L4 OD LED Power B23 OD ENUM AALx FIFO Write Strobes E3 ...

Page 61

... PRST* PBE0* PINT* PCS* (PHYCS1*) PAS* PBLAST* (PHYCS2*) PWAIT* PWNR PFAIL Input Output Open Drain Output The symbol (*) Indicates Active Low Mindspeed Technologies ™ 2.0 Architecture Overview 2.10 Logic Diagram and Pin Descriptions AC16 O Transmit Data AF17 AE17 AD17 AC17 AE18 ...

Page 62

... STAT1 STAT0 TRST* Boundary Scan TCLK TDO Test Signals TMS TDI SCL SDA Serial EEPROM EEPWR I = Input Output Open Drain Output The symbol (*) Indicates Active Low Mindspeed Technologies ™ CN8236 J2 Memory Bank Chip Selects Memory Read Enable O G3 Memory Write Enables O ...

Page 63

... HFRAME*, HIRDY*, and HTRDY*; all deasserted simultaneously). OD Signals an interrupt request to the PCI host, and is tied to the INTA_ line on the PCI bus. Mindspeed Technologies ™ 2.0 Architecture Overview 2.10 Logic Diagram and Pin Descriptions Definition 2-29 ...

Page 64

... Outputs the 8-bit odd parity computed over the TxData[15:0] lines in all framer modes (8 mA drive). I/O In both UTOPIA and slave UTOPIA modes, the TxSOC line is asserted by the CN8236 when the starting byte of a 53-byte cell is being output. (aka TxMark) Mindspeed Technologies ™ CN8236 Definition 28236-DSH-001-B ...

Page 65

... UTOPIA mode, and maintain the specified setup and hold times with reference to its rising edge. When MULTI_CLK is set the CONFIG1 register, the Tx side of the UTOPIA interface is synchronized to the TxClk. Mindspeed Technologies ™ 2.0 Architecture Overview 2.10 Logic Diagram and Pin Descriptions Definition ...

Page 66

... During standalone mode, this output is a second chip select, PHYCS2*. O Signals that the memory or control register has accepted the data on a write, or that data is available to latch by the local processor on a read cycle. Mindspeed Technologies ™ CN8236 Definition 28236-DSH-001-B ...

Page 67

... CLK2X; it can be used for the UTOPIA interface clock (22 MHz maximum). O CN8236 internal status outputs. Internal status controlled by the STAT_MODE[4:0] field in the CONFIG0 Register. I External Scheduler Reference Clock. Mindspeed Technologies ™ 2.0 Architecture Overview 2.10 Logic Diagram and Pin Descriptions Definition 2-33 ...

Page 68

... Provides Electrostatic Discharge (ESD) protection and over voltage protection. When the device is used with 5 V devices on the board, tie this pin for 5 V signal tolerance. Otherwise, tie to 3.3 V. The 5 V supply must be applied concurrent to the 3.3 NOTE: V supply. Mindspeed Technologies ™ CN8236 Definition 28236-DSH-001-B ...

Page 69

... The CN8236 provides a flexible, high-performance, host interface architecture. With this interface, the CN8236 facilitates a scalable, distributed host system. The interface also minimizes the impact of an ATM port on the host system’s PCI bus. 28236-DSH-001-B 3 Mindspeed Technologies ™ 3-1 ...

Page 70

... ATM services. 3-2 ATM ServiceSAR Plus with xBR Traffic Management CN8236 Subsystem PCI Interface LEGEND: Figure 3-1, the clients do not need to be physically distinct PCI Mindspeed Technologies ™ CN8236 Figure 3-1 illustrates this ATM Server ATM User-Network Interface ...

Page 71

... Thus, peer-to-peer transfers reduce the use of the PCI bus. 28236-DSH-001-B shows the difference between these two options. Centralized Mindspeed Technologies ™ 3.0 Host Interface 3.2 Multiple Client Architecture 3-3 ...

Page 72

... Local Processor Port System 3-4 ATM ServiceSAR Plus with xBR Traffic Management 1 PCI BUS 2 1 PCI Host LEGEND: Centralized Memory PCI Motherboard shows an out-of-band control architecture. CN8236 Subsystem LEGEND: Mindspeed Technologies ™ CN8236 CN8236 PCI Transaction Peer-to-Peer Transaction # # Centralized Memory Transaction ...

Page 73

... CN8236 control and status queues. Type Segmentation Transmit queue Control Segmentation status queue Status Mindspeed Technologies ™ 3.0 Host Interface 3.3 Write-only Control and Status Reassembly Free buffer queue Reassembly status queue 3-5 ...

Page 74

... Definition Host variable Host word aligned variable SAR Base table SAR register SAR Base table SAR Base table illustrates the control queue management algorithm. The host Table Mindspeed Technologies ™ CN8236 Location Initialization Host defined 0 &READ_UD 3-2 ...

Page 75

... SAR initiates EPD on all channels assigned to this queue. describes SAR handling of free buffer queue underflow in detail. 28236-DSH-001-B VLD bit Update Host Y UPDATE= UPDATE=0 INTERVAL READ_UD_PNTR= READ N Mindspeed Technologies ™ 3.0 Host Interface 3.3 Write-only Control and Status Base Register READ++ UPDATE++ (Base Table) 8236_101 Chapter 5.0 3-7 ...

Page 76

... Definition sar base table SAR Base table Host Variable Host Variable Host Variable Host Variable illustrates the status queue management algorithm. The host initializes Table 3-3. Mindspeed Technologies ™ CN8236 Location Initialization Host defined 0 &READ_UD ...

Page 77

... VLD bit Update SAR Y UPDATE= UPDATE=0 INTERVAL READ_UD_PNTR= READ N PCI Bus Boundary Mindspeed Technologies 3.0 Host Interface 3.3 Write-only Control and Status READ_UD_PNTR READ_UD (Base Table) WRITE++ (Base Table WRITE = Signal READ_UD - 1 Overflow Chapter 4.0 and Chapter 5.0 ™ ...

Page 78

... STAT_CNT, the interrupt window is opened, which allows the interrupt to propagate to the output pin. The counter is reset when the status registers are read and the interrupt output goes inactive. 3-10 ATM ServiceSAR Plus with xBR Traffic Management Mindspeed Technologies ™ CN8236 28236-DSH-001-B ...

Page 79

... AAL0. The CN8236 also generates the ATM cell header, as defined by the host, for each VCC. Furthermore, the segmentation coprocessor and xBR Traffic Manager together provide service-specific features to enhance the performance of Frame Relay internetworking and LAN Emulation. 28236-DSH-001-B 4 Mindspeed Technologies ™ 4-1 ...

Page 80

... VCCs allowed by the SAR is limited by the amount of SAR-shared memory available in which to allocate and create segmentation VCC tables, transmit queues, etc. 4-2 ATM ServiceSAR Plus with xBR Traffic Management shows a VCC table with a CBR VCC at VCC_INDEX 3, an ABR Mindspeed Technologies ™ CN8236 28236-DSH-001-B ...

Page 81

... Words = 1 Descriptor } (CBR VCC) 7 Words VCC Table Entry } 3 Words SCH_STATE } VCC Table Entry 7 Words } SCH_STATE 13 Words VCC Table Entry SCH_STATE Section 4.3.1, for full details of the structure of a Mindspeed Technologies ™ 4.0 Segmentation Coprocessor 4.2 Segmentation Functional Description } 1 Descriptor } 2 Descriptors 8236_095 4-3 ...

Page 82

... Buffer contains complete message. Restart/terminate CPCS-PDU. 4-4 ATM ServiceSAR Plus with xBR Traffic Management SAR-shared memory data buffer segmentation should be limited to low bandwidth applications, such as Signalling, OAM, and ILMI. Buffer to Message Adaptation Mindspeed Technologies ™ CN8236 Table 4-1 describes 28236-DSH-001-B ...

Page 83

... SBD chaining. The host has formed a Host (or SAR Shared) Memory Section 3.3.1. The host processor writes a Mindspeed Technologies ™ 4.0 Segmentation Coprocessor 4.2 Segmentation Functional Description ...

Page 84

... SBDs to a VCC table entry. As the new buffers are submitted, the VCC is processing a single buffer PDU (BOM/EOM). The CN8236 accepts new PDUs while it is processing outstanding buffers. BUFF_PNTR = &A BUFF_PNTR = &B BUFF_PNTR = &C BUFF_PNTR = &Z Mindspeed Technologies ™ CN8236 SBDs VCC_INDEX = 4 CONTROL <BOM> NEXT ...

Page 85

... VCC_INDEX (that is, the same VCI) for the length of the PDU. This allows the CN8236 to multiplex VCI messages at the PDU level. For AAL5 segmentation, the host must guarantee that SBDs are linked with PDU multiplexing to preserve CPCS-PDU integrity. 28236-DSH-001-B BD_PNTR Mindspeed Technologies ™ 4.0 Segmentation Coprocessor 4.2 Segmentation Functional Description VCC_INDEX = 4 CONTROL < ...

Page 86

... ATM ServiceSAR Plus with xBR Traffic Management illustrates the CN8236’s AAL5 PDU generation scheme. The SAR USER DATA BUFFER(S) H (Set PTI[ ATM_HEADER Internal CRC Accumulator Circuits SEG VCC Table Entry Mindspeed Technologies CN8236 Chapter 7.0, covers H PAD UU CPI LEN CRC-32 UU PDU_LEN CRC_REM ™ ...

Page 87

... Buffer Allocation Size; read from SEG Buffer Descriptor entry. 8 Alignment Filler, aligns the trailer to fit a 32-bit word. 8 Ending Tag; read from SEG VCC table entry. 16 CPCS-PDU Length; the calculated size of the PDU’s payload. Mindspeed Technologies ™ 4.0 Segmentation Coprocessor 4.2 Segmentation Functional Description Table 4-2. Function ...

Page 88

... CRC-10 generator before transmission by setting the CRC_10 option in the SEG buffer descriptor. shows the settings for the ST (Segment Type) field. Segment Type Encoding BOM 10 COM 00 EOM 01 SSM 11 Mindspeed Technologies CN8236 Table 4-3. Function Usage Beginning of Message Continuation of Message End of Message Single Segment Message ™ 28236-DSH-001-B ...

Page 89

... CN8236’s AAL3/4 PDU generation scheme. <64 K Payload MID LI CRC Internal Byte Length Counter CRC Accumulator Circuits SEG VCC Table Entry Mindspeed Technologies ™ 4.0 Segmentation Coprocessor 4.2 Segmentation Functional Description PAD AL Etag Length Trailer MID Pad LI CRC ...

Page 90

... For specific DSL applications with variable rate PHY devices, a value between 50 and 100 is suggested. 4-12 ATM ServiceSAR Plus with xBR Traffic Management 6.0, discusses this trade-off in greater depth. Once sent to the transmit The cell discard does not disable the port. Mindspeed Technologies ™ CN8236 Section 6.2.3.3, in the 28236-DSH-001-B ...

Page 91

... ATM_HEADER value in the VCC table entry. The host does not use the transmit queue for Virtual FIFO buffers. The CN8236 transmits cell payloads from this location indefinitely, with no status reporting. 28236-DSH-001-B Section Mindspeed Technologies ™ 4.0 Segmentation Coprocessor 4.2 Segmentation Functional Description 3.2. The CN8236 reports status Section 3 ...

Page 92

... ATM ServiceSAR Plus with xBR Traffic Management describe the format of AAL3/4, AAL5, and AAL0 VCC table = Written by host at VCC setup = May be dynamically modified during active segmentation LAST_PNTR BOM_PNTR ATM_HEADER CRC_REM BETAG Rsvd SN CURR_PNTR SCH_STATE Mindspeed Technologies ™ CN8236 Table 4-5 BUFFER_LEN MID NEXT_VCC 28236-DSH-001-B ...

Page 93

... PM_EN bit, and is copied by the SAR from the current buffer descriptor. The bit is used to select the correct VBR bucket for certain VBR VCCs. 28236-DSH-001-B 4.3 Segmentation Control and Data Structures Description Chapter 7.0.) Mindspeed Technologies ™ 4.0 Segmentation Coprocessor 4-15 ...

Page 94

... Specific scheduling state information. The contents of this field depend on the setting of the SCH_MODE field not used when SCH_MODE is set to UBR. (The contents of this field are detailed in Chapter 6.0.) 4-16 ATM ServiceSAR Plus with xBR Traffic Management Description Chapter 6.0, for details.) Mindspeed Technologies ™ CN8236 28236-DSH-001-B ...

Page 95

... Pointer to the PCI space data FIFO buffer for CBR_FIFO scheduling mode. 28236-DSH-001-B 4.3 Segmentation Control and Data Structures shows the format for Virtual FIFO buffer VCC table entries, Table 4-8 LAST_PNTR BOM_PNTR ATM_HEADER FIFO_PNTR CRC_REM CURR_PNTR= 0x00000 SCH_STATE Description Mindspeed Technologies ™ 4.0 Segmentation Coprocessor describes the field that Reserved 4-17 ...

Page 96

... NOTE(S): = AAL3/4; used when generating OAM cells. 4-18 ATM ServiceSAR Plus with xBR Traffic Management through 4-13 describe the entry formats and field definitions for NEXT_PNTR NEXT_PNTR USER_PNTR BUFFER_PNTR Reserved Mindspeed Technologies ™ CN8236 Rsvd Rsvd LENGTH SEG_VCC_INDEX PTI_DATA VCI_DATA 28236-DSH-001-B 16 ...

Page 97

... This definition of bits 31:16, MISC_DATA field, applies when the AAL_MODE field = AAL3/4 and RPL_VCI = 0. In order to NOTE(S): activate GFC override, the HEADER_MOD bit must be set to a logic high. 28236-DSH-001 NEW_VCI Reserved Mindspeed Technologies ™ 4.0 Segmentation Coprocessor 4.3 Segmentation Control and Data Structures BASIZE_L 16 16 4-19 ...

Page 98

... AAL_MODE Controls AAL segmentation mode AAL5 01 = AAL0 Read 48-octet ATM cell payload from segmentation buffer. Only formatting is to set PTI[0] on last cell of an EOM buffer AAL3 Reserved 4-20 ATM ServiceSAR Plus with xBR Traffic Management Description Mindspeed Technologies ™ CN8236 28236-DSH-001-B ...

Page 99

... Data for the RPL_VCI. The CN8236 overwrites the VCC table entry ATM_HEADER VCI field with this data. Therefore, the effect is permanent until the next buffer descriptor with RPL_VCI is processed. 28236-DSH-001-B 4.3 Segmentation Control and Data Structures Description Table 4-1.) Table 4-1.) Chapter 7.0.) Mindspeed Technologies ™ 4.0 Segmentation Coprocessor Chapter 7.0.) 4-21 ...

Page 100

... The low order bits used for the BASIZE field in the AAL3/4 header when the GEN_PDU option is selected. SEG_VCC_INDEX Identifies the VCC entry in the VCC table. The CN8236 links this buffer descriptor to the identified VCC. 4-22 ATM ServiceSAR Plus with xBR Traffic Management Description Mindspeed Technologies ™ CN8236 28236-DSH-001-B ...

Page 101

... Points to the first buffer descriptor in the new buffer descriptor chain. Bits 22:2 of the address are specified; the two least significant bits of the pointer are assumed (word-aligned). 28236-DSH-001-B 4.3 Segmentation Control and Data Structures Table 4-14 and Table 4-15 SEG_BD_PNTR Description Mindspeed Technologies ™ 4.0 Segmentation Coprocessor describe the format of these Rsvd 4-23 ...

Page 102

... ATM ServiceSAR Plus with xBR Traffic Management Table 4-16 (SEG_TXBASE(SEG_TXB) 128) <decoded TQ_SIZE value + <entry number> 4 Chapter 3.0 describes the runtime management of a write-only control READ_UD_PNTR UPDATE Reserved Description Chapter 2.0, for details.) Mindspeed Technologies ™ CN8236 and Table 4-17 below describe + <transmit queue number> READ 28236-DSH-001-B ...

Page 103

... Segmentation Control and Data Structures is a cross-reference between the routing tag table and the The maximum TxFIFO size becomes reduced when using routing tags. TxFIFO (maximum number of cells Mindspeed Technologies ™ 4.0 Segmentation Coprocessor Figures 4-7 through 4-9 show the h = atm header 8236_017 4-25 ...

Page 104

... TXFIFO Figure 4-9. Route Tag Table for tag_size = 9 through 11 SEG_TAGBASE(SEG_TAGB) SEG_VCC_INDEX TXFIFO 4-26 ATM ServiceSAR Plus with xBR Traffic Management 0x0 0x4 atm header 0x0 0x4 b8 b9 b10 b11 0x8 b10 b11 Mindspeed Technologies ™ CN8236 8236_018 h = atm header 8236_019 28236-DSH-001-B ...

Page 105

... CN8236 ATM ServiceSAR Plus with xBR Traffic Management Table 4-19. Routing Tag Cross-Reference Tag Size 28236-DSH-001-B 4.3 Segmentation Control and Data Structures Mindspeed Technologies ™ 4.0 Segmentation Coprocessor b10 b11 t10 t8 t9 t10 t11 4-27 ...

Page 106

... Segmentation VCC index on which the SAR transmitted the buffer or PDU. 4-28 ATM ServiceSAR Plus with xBR Traffic Management Tables 4-20 for a description of the trigger mechanism for posting special USER_PNTR Reserved Description 6.0.) Chapter 6.0.) Mindspeed Technologies ™ CN8236 and 4-21 describe the format Tables 4-22 and 4-23. Refer to SEG_VCC_INDEX 28236-DSH-001-B ...

Page 107

... A logic high indicates latest NCR threshold crossed was NCR_HI, a logic low indicates NCR_LO threshold was crossed last. OVFL Overflow: status entry is last entry available. SEG_VCC_INDEX Segmentation VCC index for buffer. 28236-DSH-001-B 4.3 Segmentation Control and Data Structures Reserved Description Mindspeed Technologies ™ 4.0 Segmentation Coprocessor ACR SEG_VCC_INDEX 4-29 ...

Page 108

... READ_UD pointer in the base table register, the CN8236 inhibits segmentation on all channels that report on the overflowed status queue. All other channels are unaffected. 4-30 ATM ServiceSAR Plus with xBR Traffic Management and 4-25 describe the format of these entries. BASE_PNTR WRITE Reserved Description Mindspeed Technologies ™ CN8236 READ_UD 28236-DSH-001-B ...

Page 109

... PCI address for AALx 0 connected to HFIFOWR0 PCI address for AALx 1 connected to HFIFOWR1 PCI address for AALx 2 connected to HFIFOWR2 PCI address for AALx 3 connected to HFIFOWR3 PCI address for AALx 4 connected to HFIFOWR4 PCI address for AALx 5 connected to HFIFOWR5 Mindspeed Technologies ™ 4.0 Segmentation Coprocessor 4-31 ...

Page 110

... Segmentation Coprocessor 4.3 Segmentation Control and Data Structures 4-32 ATM ServiceSAR Plus with xBR Traffic Management Mindspeed Technologies ™ CN8236 28236-DSH-001-B ...

Page 111

... This chapter provides information on the functions and data structures of the reassembly coprocessor. For detailed information on how the CN8236 handles PM cells, deals with OAM functions, and interacts with the segmentation coprocessor in handling traffic management and scheduling, refer to and Chapter 28236-DSH-001-B 5 7.0. Mindspeed Technologies ™ Chapter 6.0, 5-1 ...

Page 112

... SAR-shared memory available in which to allocate and create RSM VCC tables, free buffer queues, RSM status queues, etc. 5-2 ATM ServiceSAR Plus with xBR Traffic Management illustrates the basic reassembly process flow. Messages Reassembly Coprocessor Mindspeed Technologies ™ CN8236 Host (64 K) 8236_020 28236-DSH-001-B ...

Page 113

... VCC. 28236-DSH-001-B illustrates how entries in the RSM VCC table are indexed by Reassembly VCC Table VCC_INDEX = Words = 1 Descriptor VCC_INDEX = 4 VCC Table Entry VCC Table Entry VCC_INDEX = 0xFFFF (64 K VCCs) Mindspeed Technologies ™ 5.0 Reassembly Coprocessor 5.2 Reassembly Functional Description 8236_021 5-3 ...

Page 114

... ATM ServiceSAR Plus with xBR Traffic Management illustrates the direct index channel lookup mechanism. RSM_TBASE (RSM_VCCB) VCI Index Table (for one VPI) VCI [15:6] VCC_Block_Index (Max. 1024 entries for each VPI) Mindspeed Technologies ™ CN8236 VCC Table (Block of 64 VCC Table Entries) VCI [5:0] 8236_022 28236-DSH-001-B ...

Page 115

... VCI[15:0] 65536 VCI[15:1] 32768 VCI[15:2] 16384 VCI[15:3] 8192 VCI[15:4] 4096 VCI[15:5] 2048 VCI[15:6] 1024 Mindspeed Technologies ™ 5.0 Reassembly Coprocessor 5.2 Reassembly Functional Description Section 5.7.1. Reassembly VCC Table VCI [x-1:0] (For x=0, pointer is not applicable) Where x = value of VCI_IT_BLK_SZ 8236_103 Number of ...

Page 116

... VCC_BLOCK_INDEX value with the VCI[x-1:0] bits from the received cell header. Thus, VCI[x-1:0] from the received header points to the reassembly VCC State table entry for that VCC. 5-6 ATM ServiceSAR Plus with xBR Traffic Management Section 5.2.2.2 by setting EN_PROG_BLK_SZ(RSM_CTRL1) VCI_IT_PNTR 4 + VCI[15:x] 4 VCC_INDEX = VCC_BLOCK_INDEX Mindspeed Technologies ™ CN8236 + VCI[x-1:0] 28236-DSH-001-B ...

Page 117

... However, for AAL3/4 connections, Table 5-14). Figure 5-5. RSM_TBASE (RSM_VCCB) VCI Index Table (for one VPI) VCC_Block_Index VCI [15:x] VCI [x-1:0] Mindspeed Technologies ™ 5.0 Reassembly Coprocessor 5.2 Reassembly Functional Description Reassembly VCC Table (Block of AAL3/4 VCC Table entries for 1 VC) (Mid=0) MID (Block ...

Page 118

... ATM ServiceSAR Plus with xBR Traffic Management CONFIG1(NUM_PORTS), their 1024 entries PORT_ID = 0 (MAX_VPI = 1023) 512 entries PORT_ID = 1 (MAX_VPI = 511) PORT_ID = 2 (turned off) 1024 entries PORT_ID = 3 (MAX_VPI = 1023) 2048 entries PORT_ID = 4 (MAX_VPI = 2047) Mindspeed Technologies ™ CN8236 Figure 5-6 shows 8236_024 28236-DSH-001-B ...

Page 119

... CN8236 to perform specific functions as described throughout this chapter. 28236-DSH-001-B illustrates the basic process function. COM Cells . . . . . . (Hdr) (Payload) Mindspeed Technologies ™ 5.0 Reassembly Coprocessor 5.3 CPCS-PDU Processing EOM Cell (Hdr) (Payload 8236_025 ...

Page 120

... LENGTH field in the trailer of the AAL5 PDU. If the number of PAD bytes is less than 0 or greater than the 47 the reassembly coprocessor sets, the PAD_ERROR bit in the status queue entry to a logic high. status queue entry is set to a logic high. buffer(s) in memory. Mindspeed Technologies ™ CN8236 Status Queue ...

Page 121

... Section 5.6 min[RSM_CTRL0(MAX_LEN) 1024, 65568 TOT_PDU_LEN + 48 > MAX_LEN Section 5.4.8, for details on how this process is handled. TOT_PDU_LEN + 48 > MAX_LEN Mindspeed Technologies ™ 5.0 Reassembly Coprocessor 5.3 CPCS-PDU Processing RSM VCC Table Entry Status Queue Entry 8236_027 for full details. 1024 (or 65568) ...

Page 122

... CRC = A CRC check of the 48-byte ATM cell payload. 5-12 ATM ServiceSAR Plus with xBR Traffic Management illustrates an AAL3/4 CPCS-PDU reassembled from the received <64 K Payload MID LI CRC Mindspeed Technologies ™ CN8236 Section 5.4. The EOM PAD AL Etag Length Trailer MID PAD ...

Page 123

... BOM_SSM_ERR counter in the VCC Head table entry, and processes the current cell as a valid CPCS-PDU. – If the cell received is a COM, and the SAR was expecting a BOM or SSM, the SAR discards the cell. Mindspeed Technologies ™ 5.0 Reassembly Coprocessor 5.3 CPCS-PDU Processing ...

Page 124

... LEN_ERROR bit set and CPCS_LENGTH = 0. greater than (BASIZE + 7). If so, the CN8236 discards the cell, terminates the CPCS-PDU, and writes a status queue entry with the LEN_ERROR bit set high, CPCS_LENGTH set to 0, and BD_PNTR pointing to the partially reassembled PDU. Mindspeed Technologies ™ CN8236 28236-DSH-001-B ...

Page 125

... CPCS-PDU trailer. If not a match, it sets the BA_ERROR bit in the status queue entry. If BAT_EN is low, it checks if the Length field is > BASIZE; and if so, sets the BA_ERROR bit in the status queue entry. Mindspeed Technologies ™ 5.0 Reassembly Coprocessor 5.3 CPCS-PDU Processing ...

Page 126

... PTI[0] set to 1 indicates the end of the AAL0 message. The total maximum allowable length of an AAL0 PDU in this mode is (CCOUNT × 2) bytes. provides an illustration of this. (Hdr) (Payload) PTI[0]=0 Section TOT_PDU_LEN + 48 > CCOUNT TOT_PDU_LEN + 48 > CCOUNT Mindspeed Technologies ™ CN8236 (EOM Cell (Hdr) (Payload) PTI[0]= 8236_028 5.6. 2 Section 5.4.8, for ...

Page 127

... When RSM_CTRL0(PREPEND_INDEX logic high, the VCC_INDEX is appended to the BOM cell as follows: Table 5-3. Prepend Index Table Format Word Reserved 28236-DSH-001-B CPCS-PDU. Table 5-2. STAT[ Mindspeed Technologies ™ 5.0 Reassembly Coprocessor 5.3 CPCS-PDU Processing STAT[ VCC_INDEX 5-17 ...

Page 128

... Therefore, to speed up processing flow during reassembly, the CN8236 uses only control and status writes across the PCI bus between host and local systems. Mindspeed Technologies ™ CN8236 Figure 5-12: two in the ...

Page 129

... Free Buffer Queue Base Table (Inside the CN8236) FBQx_BASE + [(size of each free buffer queue) BFRx MOD 16] (index of first entry for the queue) (size of each free buffer queue entry)] Mindspeed Technologies ™ 5.0 Reassembly Coprocessor 5.4 Buffer Management 8236_029 + [(READ index pointer) 5-19 ...

Page 130

... BFR1) READ 5-20 ATM ServiceSAR Plus with xBR Traffic Management illustrates this structure. Refer to Free Buffer Queue Bank (SAR-Shared Memory) [BFRx x (Global size of FBQ)] (16 Free Buffer Queues in Each Bank) Mindspeed Technologies ™ CN8236 Chapter 3.0, for more FBQx_BASE 8236_030 28236-DSH-001-B ...

Page 131

... Only the data buffers are affected by big/little endian processing. The buffer control structures (that is, the buffer descriptors, free buffer queue base table, and free buffer queues) are the same in both big and little endian modes. Mindspeed Technologies ™ 5.0 Reassembly Coprocessor 5.4 Buffer Management ...

Page 132

... For each unallocated free buffer queue entry, write the VLD bit to a logic low. 5.4.5.4 Other The user can globally disable free buffer underflow protection by setting Initialization RSM_CTRL(RSM_FBQ_DIS logic high. 5-22 ATM ServiceSAR Plus with xBR Traffic Management Mindspeed Technologies ™ CN8236 28236-DSH-001-B ...

Page 133

... Once the host has written more free buffers on the queue with VLD bit set to a logic high, the reassembly coprocessor automatically recovers from the empty condition. 28236-DSH-001-B 5.4.7.) If the VLD bit is a logic high, the reassembly coprocessor uses the Mindspeed Technologies ™ 5.0 Reassembly Coprocessor 5.4 Buffer Management Section 5 ...

Page 134

... SERV_DIS counter in the VCC table. All cells on that channel up to the next BOM are discarded. entry for this channel is set to a logic high. The CNT_ROVR bit in the VCC table holds this flag information until a status is sent. Mindspeed Technologies ™ CN8236 28236-DSH-001-B ...

Page 135

... SERV_DIS counter in the VCC table. entry for this channel is set to a logic high. The CNT_ROVR bit in the VCC table holds this flag information until a status is sent. Mindspeed Technologies ™ 5.0 Reassembly Coprocessor 5.4 Buffer Management ...

Page 136

... Partially reassembled CPCS-PDUs is recovered for the following error conditions: • Non-EOM Max PDU Length exceeded • Free buffer queue underflow • Status queue overflow 5-26 ATM ServiceSAR Plus with xBR Traffic Management Status Queue entry. PDU. Mindspeed Technologies ™ CN8236 28236-DSH-001-B ...

Page 137

... In AAL5 and AAL0, PTI termination modes, the reception of a non-EOM cell resets the counter. 28236-DSH-001-B GTO_EN set to 0 resets the internal time-out interrupt counter. 5.4.9.4. Mindspeed Technologies ™ 5.0 Reassembly Coprocessor 5.4 Buffer Management 5-27 ...

Page 138

... FIFO buffer. External circuitry must also ensure that only complete cells are written into the host FIFO buffer. The beginning of a cell transfer can be detected by the PCI address being 64-byte aligned. 5-28 ATM ServiceSAR Plus with xBR Traffic Management = SYSCLK period RSM_TO_PER RSM_TO_CNT Mindspeed Technologies ™ CN8236 TERM_TOCNTx 28236-DSH-001-B ...

Page 139

... VCC table(s) still decrements each time the VCC receives a BOM cell. The RX_COUNTER should not be decremented when the FBQ is empty. There is no workaround for this problem. The user “must” avoid FBQ empty conditions when firewalling is enabled. channel. channel. Mindspeed Technologies ™ 5.0 Reassembly Coprocessor 5.4 Buffer Management 5-29 ...

Page 140

... Before the reassembly coprocessor is enabled, the host must initialize the FORWARD read pointer to the first entry where credit is returned. Typically, this is the first entry after the initial buffers placed on the queue. 5-30 ATM ServiceSAR Plus with xBR Traffic Management Mindspeed Technologies ™ CN8236 28236-DSH-001-B ...

Page 141

... This includes idle cells, since those channels is turned off. channel firewall, buffer queue underflow, FIFO buffer full packet discard, status queue overflow, or maximum CPCS-PDU length exceeded on non-EOM cells. Mindspeed Technologies ™ 5.0 Reassembly Coprocessor 5.5 Global Statistics 5-31 ...

Page 142

... ATM ServiceSAR Plus with xBR Traffic Management HOST SAR-Shared Status Queue Base Table (Internal in the CN8236) Mindspeed Technologies ™ CN8236 Figure 5-15, one in host 8236_031 28236-DSH-001-B ...

Page 143

... VLD bit to a logic low. Initialize the READ pointers to 0 for each status queue. 28236-DSH-001-B illustrates this structure. (32 Status Queues) BASE_PNTR field. otherwise set the bit to a logic low. Mindspeed Technologies ™ 5.0 Reassembly Coprocessor 5.6 Status Queue Operation 8236_032 5-33 ...

Page 144

... RSM_LF_EMPT bit in the LP_ISTAT1 register is set to a logic high. This status does not point to a linked list of buffer descriptors written a maximum of once per free buffer queue empty condition. 5-34 ATM ServiceSAR Plus with xBR Traffic Management Chapter 2.0, for detailed information on the operation of status Mindspeed Technologies ™ CN8236 28236-DSH-001-B ...

Page 145

... VLD bit set to logic low. Again, the host periodically writes the current READ index value into the READ_UD field of the status queue base table entry. 28236-DSH-001-B Only status queues 0 through 15 are reported in this register. Mindspeed Technologies ™ 5.0 Reassembly Coprocessor 5.6 Status Queue Operation 5-35 ...

Page 146

... EOM are discarded. Status queue overflow protection can be globally disabled by setting RSM_CTRL0(RSM_STAT_DIS logic high. NOTE: 5-36 ATM ServiceSAR Plus with xBR Traffic Management Avoid having the Status Queue Overflow (or Full Condition) and DMA FIFO Buffer Full conditions at the same time. Mindspeed Technologies ™ CN8236 28236-DSH-001-B ...

Page 147

... VPI Index table format (one word per entry) describes the VPI Index table format (two words per entry) with describes the field definitions for the VPI Index table fields. Mindspeed Technologies ™ 5.0 Reassembly Coprocessor 5.7 Reassembly Control and Data Structures ...

Page 148

... ATM ServiceSAR Plus with xBR Traffic Management Description/Function describes the VCI Index table format without the programmable describes the VCI Index table format with EN_PROG_BLK_SZ describes the VCI Index table Descriptions. VCC_BLOCK_INDEX Description/Function Mindspeed Technologies ™ CN8236 Reserved VCC_BLOCK_INDEX 28236-DSH-001-B ...

Page 149

... Figure 5-18 continuation from Figure 5-18. Reassembly VCC Table Entry Lookup Mechanism Base Register RSM_TBASE(RSM_VCCB) VCC_BLOCK_INDEX 28236-DSH-001-B 5.7 Reassembly Control and Data Structures illustrates the VCC table entry lookup mechanism as a Figure 5-17. VCI[5:0] Mindspeed Technologies ™ 5.0 Reassembly Coprocessor 8236_033 5-39 ...

Page 150

... AAL0 RSM VCC table entries. = Written by host at VCC setup. = May be dynamically modified during active reassembly. PM_INDEX Reserved Reserved CRCREM STAT CBUFF_PNTR BOM_BD_PNTR CURR_BD_PNTR ERS_INDEX D_NCR_HI_MANT Rsvd D_NCR_LO_EXP Mindspeed Technologies ™ CN8236 Table 5-12 AAL_EN ABR_CTRL TOT_PDU_LEN BFR1 BFR0 Rsvd SERV_DIS RX_COUNTER/VPC_INDEX EXP_TA_ER D_NCR_LO_MANT 28236-DSH-001-B ...

Page 151

... Reserved 10 Reserved CONG_ID 11 Rsvd D_NCR_HI_EXP 28236-DSH-001-B PM_INDEX Reserved Reserved STAT CBUFF_PNTR BOM_BD_PNTR CURR_BD_PNTR ERS_INDEX D_NCR_HI_MANT Rsvd D_NCR_LO_EXP Mindspeed Technologies ™ 5.0 Reassembly Coprocessor 5.7 Reassembly Control and Data Structures AAL_EN ABR_CTRL TOT_PDU_LEN TCOUNT BFR1 BFR0 Rsvd SERV_DIS RX_COUNTER/VPC_INDEX EXP_TA_ER D_NCR_LO_MANT 5-41 ...

Page 152

... CUR_TOCNT 2 PDU_FLAGS 3 BASIZE 4 Reserved SEG_VCC_INDEX 9 Reserved 10 Reserved 11 Reserved 5-42 ATM ServiceSAR Plus with xBR Traffic Management PM_INDEX Reserved Reserved Rsvd STAT CBUFF_PNTR BOM_BD_PNTR CURR_BD_PNTR RX_COUNTER/VPC_INDEX Mindspeed Technologies ™ CN8236 AAL_EN ABR_CTRL TOT_PDU_LEN NEXT_SN BTAG BFR1 BFR0 Rsvd SERV_DIS Reserved Reserved 28236-DSH-001-B ...

Page 153

... If set high, all 52 octets of the cell are written to a cell buffer. = Enable interrupt after BOM buffer filled in Message Mode. = Enable LANE-LECID echo suppression. Invalid in AAL3/4. = Enable frame relay DE (Discard Eligibility) mode. Invalid in AAL3/4. = Enable CLP discard mode. Invalid in AAL3/4. Mindspeed Technologies ™ 5.0 Reassembly Coprocessor 5.7 Reassembly Control and Data Structures 3 ...

Page 154

... SAR maintains this bit. = Active PDU. Indication that at least one buffer has been taken off of the free buffer queue for the current PDU being received. = BOM buffer flag. Set high when filling the first buffer of a PDU. Mindspeed Technologies ™ CN8236 3 ...

Page 155

... Destination ACR/ER upper threshold, exponent portion. D_NCR_HI_MANT Destination ACR/ER upper threshold, mantissa portion. D_NCR_LO_EXP Destination ACR/ER lower threshold, exponent portion. D_NCR_LO_MANT Destination ACR/ER lower threshold, mantissa portion. 28236-DSH-001-B 5.7 Reassembly Control and Data Structures Description/Function Mindspeed Technologies ™ 5.0 Reassembly Coprocessor 5-45 ...

Page 156

... ATM ServiceSAR Plus with xBR Traffic Management shows the AAL3/4 Head VCC table structure. Reserved PM_INDEX Reserved Reserved STAT ERS_INDEX D_NCR_HI_MANT Rsvd D_NCR_LO_EXP Description/Function Mindspeed Technologies ™ CN8236 Table 5-15 details the AAL_EN ABR_CTRL VCC_INDEX_BASE BFR1 BFR0 MID_ERR SN_ERR EOM_ERR ...

Page 157

... MID processing disabled 0001 0 / 1-1 0010 0 / 1-3 0011 0 / 1-7 0100 0 / 1-15 0101 0 / 1-31 0110 0 / 1-63 0111 0 / 1-127 1000 0 / 1-255 1001 0 / 1-511 1010 0 / 1-1023 1011 Reserved 1100 Reserved 1101 Reserved 1110 Reserved 1111 Reserved Mindspeed Technologies ™ 5.0 Reassembly Coprocessor 5-47 ...

Page 158

... Destination ACR/ER upper threshold, exponent portion. D_NCR_HI_MANT Destination ACR/ER upper threshold, mantissa portion. D_NCR_LO_EXP Destination ACR/ER lower threshold, exponent portion. D_NCR_LO_MANT Destination ACR/ER lower threshold, mantissa portion. 5-48 ATM ServiceSAR Plus with xBR Traffic Management Description/Function Mindspeed Technologies ™ CN8236 28236-DSH-001-B ...

Page 159

... The SAR does not access this word; the user can place it anywhere in the buffer and Table 5-19 describe the format of the free buffer queue base table UPDATE Rsvd Rsvd READ_UD_PNTR Reserved Mindspeed Technologies ™ 5.0 Reassembly Coprocessor READ FORWARD Rsvd 5-49 ...

Page 160

... Forward Valid. If logic high, word contains valid buffer return information. VCC_INDEX Channel of corresponding buffer return. 5-50 ATM ServiceSAR Plus with xBR Traffic Management Description/Function and Table 5-21 describe the format of the free buffer queue entries. BUFFER_PNTR BD_PNTR (not used) Description/Function Mindspeed Technologies ™ CN8236 VCC_INDEX 28236-DSH-001-B ...

Page 161

... Reassembly Control and Data Structures and Table 5-23 describe the format of the reassembly status queue through Table 5-31 describe the formats of the reassembly status BASE_PNTR WRITE Reserved Description/Function BD_PNTR CPI Reserved STATUS Mindspeed Technologies ™ 5.0 Reassembly Coprocessor READ_UD 00 CPCS_LENGTH VCC_INDEX OAM STM 5-51 ...

Page 162

... ATM ServiceSAR Plus with xBR Traffic Management BD_PNTR BIPV Table 5-31 under “Status.” BD_PNTR Reserved STATUS UNDF OVFL SFPD 3 2 EOM BOM Mindspeed Technologies CN8236 TRCC0+1 VCC_INDEX OAM STM CPCS_LENGTH VCC_INDEX OAM STM A3L2_ERR ABORT CNT_ROVR 1 0 STM_MODE BFR1 ™ ...

Page 163

... A3L2_ERR fields are active. This field is only active when FWD_PM = 0. NOTE(S): 28236-DSH-001-B Description/Function AAL3/4: BASIZE field error occurred. rolled over, based on these values MID_ERR 1 = CRC10_ERR 2 = SN_ERR 3 = LI_ERR 4 = EOM_ERR 5 = BOM_SSM_ERR Mindspeed Technologies ™ 5.0 Reassembly Coprocessor 5.7 Reassembly Control and Data Structures 5-53 ...

Page 164

... A3L2_ERR field is active in the PDU_CHECKS field and indicates which AAL3/4 MIB counter has rolled over EOM BOM STM_MODE an EOM. BOM. In Message Mode with BOM interrupt enabled, indicates that status entry points to only one buffer which contains a BOM. indicates COM(BFR1), logic low indicates BOM(BFR0). Mindspeed Technologies ™ CN8236 SFPD TO ABORT CNT_ROVR 0 ...

Page 165

... This implements echo suppression of superfluous multi-broadcast LANE traffic on the ATM network. 28236-DSH-001-B Figure 5-19 (Table holds 32 LECIDs) DPRI LECIDn+ LECIDn+ (etc.) Function/Description Mindspeed Technologies ™ 5.0 Reassembly Coprocessor 5.7 Reassembly Control and Data Structures includes unique identifiers Table 5-32 and Table 5-33 display LECIDn LECIDn+ (etc ...

Page 166

... Table 5-35. Global Time-Out Table Entry Descriptions Field Name TERM_TOCNTx Time-out expiration count. TO_VCC_INDEX Time-out VCC_INDEX tracking variable. 5-56 ATM ServiceSAR Plus with xBR Traffic Management Section 5.4.9. Tables 5-34 Description/Function Mindspeed Technologies ™ CN8236 and 5-35 display the entries and TERM_TOCNT0 TERM_TOCNT2 TERM_TOCNT4 TERM_TOCNT6 TO_VCC_INDEX 28236-DSH-001-B ...

Page 167

... Status Queue 0 Base Table Status Queue 1 Base Table Status Queue 31 Base Table Free Buffer Queue 0 Base Table Free Buffer Queue 1 Base Table Free Buffer Queue 31 Base Table Other Internal Reassembly Registers: Global Time-Out Table Mindspeed Technologies ™ 5.0 Reassembly Coprocessor 5-57 ...

Page 168

... Reassembly Coprocessor 5.7 Reassembly Control and Data Structures 5-58 ATM ServiceSAR Plus with xBR Traffic Management Mindspeed Technologies ™ CN8236 28236-DSH-001-B ...

Page 169

... The shaded areas do not indicate that the service category and attribute are undefined for the SAR—they simply indicate that the TM 4.1 Specification does not detail them. 28236-DSH-001-B 6 provides a list of ATM attributes detailed in the TM 4.1 Mindspeed Technologies ™ 6-1 ...

Page 170

... ATM ServiceSAR Plus with xBR Traffic Management ATM Layer Service Category (1) (2) CBR rt-VBR nrt-VBR Specified/Supported Supported Supported Supported Supported Supported (4) Supported (4) Supported Mindspeed Technologies ™ CN8236 (3) UBR ABR GFR Supported (4) Not Supported Not (4) Not Supported (4) (4) Supported Supported Supported ...

Page 171

... TM 4.1 ABR specification. The CN8236 supports the rate based flow control and service models specified for ABR in TM 4.1. The CN8236 also provides Generic Flow Control. This XON/XOFF protocol complements the GFC algorithm by allowing switches to significantly overallocate port bandwidth. 28236-DSH-001-B Mindspeed Technologies ™ 6.0 Traffic Management 6.1 Overview 6-3 ...

Page 172

... Table xBR System Cell Scheduler Clock Per-VCC Parameters and Priority 6-4 ATM ServiceSAR Plus with xBR Traffic Management shows a high-level block diagram of the Cell Scheduler control VCC_INDEX Segmentation Coprocessor Mindspeed Technologies ™ CN8236 CBR VBR UBR GFR ATM Network 8236_035 28236-DSH-001-B ...

Page 173

... Manager RATE UPDATE 28236-DSH-001-B Figure 6-2 shows a high level block diagram of the Dynamic Schedule Table VCC_INDEX Segmentation Coprocessor Per-VCC Parameters and Priority Reassembly Coprocessor Mindspeed Technologies ™ 6.0 Traffic Management 6.1 Overview ABR Cell Stream ATM Network RM Cell Feedback 8236_036 6-5 ...

Page 174

... Rate Decrease Factor (RDF However, a VCC traversing a network with switches doing CI/NI (binary) marking will desire an RIF and RDF be desired for these VCCs. 6-6 ATM ServiceSAR Plus with xBR Traffic Management 1. Thus, separate templates would Mindspeed Technologies ™ CN8236 28236-DSH-001-B ...

Page 175

... The scheduler clock is selected by bit 26 (USE_SCHREF) of the SCH_CTRL register, as shown in Table 6-2. Scheduler Clock Selection 28236-DSH-001-B Section 6.2.5. By configuring the number of slots and the duration Table 6-2. USE_SCHREF Scheduler Clock 0 SYSCLK 1 SCHREF Mindspeed Technologies ™ 6.0 Traffic Management 6.2 xBR Cell Scheduler Functional Description 6-7 ...

Page 176

... ATM ServiceSAR Plus with xBR Traffic Management represents an example of a schedule table. In this example, the Current Cell Scheduler Postion Increments Postition by One Entry Each SLOT_PER SCHEDULE TABLE Mindspeed Technologies ™ CN8236 Assigned VCC_INDEX(es) SLOT INDEX } Words ( Octets) 29 SCHEDULE SLOT 8236_037 28236-DSH-001-B ...

Page 177

... Mindspeed Technologies ™ 6.0 Traffic Management Available VBR/ABR Priority Levels (1) 0–15 (1) 1–15 VBR_OFFSET + 0–13 VBR_OFFSET + 1–13 VBR_OFFSET + 0–11 VBR_OFFSET + 1–11 VBR_OFFSET + 0–9 VBR_OFFSET + 1–9 VBR_OFFSET + 0–7 VBR_OFFSET + 1– ...

Page 178

... For example, if the system designer assigns VBR/ABR VCCs to three different scheduling priorities with the highest of those priorities being 5 (that is, PRI = 5), then 6-10 ATM ServiceSAR Plus with xBR Traffic Management VBR_OFFSET = Mindspeed Technologies ™ CN8236 Figure 6-4. The SAR can assign 28236-DSH-001-B ...

Page 179

... Cell Scheduler Functional Description illustrates how these priorities are assigned to the VBR fields. CBR_TUN = 0, DBL_SLOT = 0 VBR VCC_Index (PRI=VBR_OFFSET+0) CBR_TUN = 0, DBL_SLOT = 1 VBR VCC_Index (PRI=VBR_OFFSET+0) VBR VCC_Index (PRI=VBR_OFFSET+2) Mindspeed Technologies ™ 6.0 Traffic Management VBR VCC_Index (PRI=VBR_OFFSET+1) VBR VCC_Index (PRI=VBR_OFFSET+1) VBR VCC_Index (PRI=VBR_OFFSET+3) 8236_107 ...

Page 180

... ATM ServiceSAR Plus with xBR Traffic Management 6-5. VCC_Index SLOT_DEPTH = 000 (PRI=VBR_OFFSET+0) VCC_Index SLOT_DEPTH = 001 (PRI=VBR_OFFSET+2) VCC_Index SLOT_DEPTH = 010 (PRI=VBR_OFFSET+4) VCC_Index SLOT_DEPTH = 111 (1) Mindspeed Technologies ™ CN8236 CBR_TUN = 0 VBR/ABR VBR/ABR VCC_Index (PRI=VBR_OFFSET+1) VBR/ABR VBR/ABR VCC_Index (PRI=VBR_OFFSET+3) VBR/ABR VBR/ABR VCC_Index (PRI=VBR_OFFSET+5) ...

Page 181

... VBR2 (VBR/ABR Priority 2) ABR (VBR/ABR Priority 1) UBR2 UBR3 VBR_OFFSET + (# of VBR ABR priorities) Mindspeed Technologies ™ 6.0 Traffic Management Service/Application Voice — AAL1 on AAL0 VCCs (Scheduling Priorities 8 thru 15 are not used in the scheme.) Signalling, ILMI, PNNI Traffic Tunnel through public ATM Network Tunnel through private ATM Network rt-VBR — ...

Page 182

... To achieve the maximum rate, the user would assign one VCC to every cell slot in the Schedule Table. This would prevent any other VCC from being scheduled since this channel uses all of the available slots. 6-14 ATM ServiceSAR Plus with xBR Traffic Management clock frequency (SYSCLK or SCHREF) ------------------------------------------------------------------------------------------------ - SLOT_PER = Mindspeed Technologies ™ CN8236 is the maximum rate in max R max 28236-DSH-001-B ...

Page 183

... TBL_SIZE, R max max TBL_SIZE, ... ..., R TBL_SIZE max displays an example of a Schedule table with slots assigned to various SCHEDULE TABLE Mindspeed Technologies 6.0 Traffic Management 6.2 xBR Cell Scheduler Functional Description (TBL_SIZE 2) – max . R / TBL_SIZE max 09 VCC_INDEX = SCHEDULE SLOT ™ 8236_039 6-15 ...

Page 184

... ATM ServiceSAR Plus with xBR Traffic Management illustrates this interface. Segmentation Coprocessor PHY Interface Schedule Table Mindspeed Technologies ™ CN8236 Cells are added at CBR rate TX_FIFO (1-9 Cells) Cells are removed at (Line rate — Line overhead) 8236_040 Figure 6-9 illustrates an example ...

Page 185

... CDV = 1 (CBR rate in cells sec) + max 6.2.2.4). TX_FIFO_LEN > (worst case PCI latency) (line rate in cells sec) Mindspeed Technologies ™ 6.0 Traffic Management 6.2 xBR Cell Scheduler Functional Description 6-10, where the beginning and end TX_FIFO_LEN (line rate in cells sec) 8236_042 6-17 ...

Page 186

... The host must configure the CBR VCC rate slightly higher than the actual rate of the data source. Skipping cell transmission slots then compensates for the rate differential. 6-18 ATM ServiceSAR Plus with xBR Traffic Management Mindspeed Technologies ™ CN8236 28236-DSH-001-B ...

Page 187

... Table 6-4. TM 4.1 VBR (None) TM 4.1 does not employ single leaky bucket. VBR.1 Double leaky bucket. VBR.2 /VBR.3 TM 4.1 defines two conformance standards for CLP(0+1 PCR CDVT SCR SCR BT PCR CDVT Mindspeed Technologies ™ 6.0 Traffic Management Comments Table 6-14, 6-19 ...

Page 188

... Additionally, all priority levels used within a 6-20 ATM ServiceSAR Plus with xBR Traffic Management + Section 6.2.8. The format of a CBR tunnel schedule table slot is not backward- compatible with the CBR tunnel format used in the Bt8233 SAR. Mindspeed Technologies ™ CN8236 (TBL_SIZE – n), / max (TBL_SIZE –1). / ...

Page 189

... SLOT_DEPTH = 110. Highest VBR/ABR Scheduling priority is 15 (that is, PRI = 15). Thus, VBR_OFFSET = 3. 28236-DSH-001-B 6.2 xBR Cell Scheduler Functional Description shows priorities five and six used as CBR tunnels for UBR illustrates a different use of CBR tunnels. In this example, Mindspeed Technologies ™ 6.0 Traffic Management 6-21 ...

Page 190

... VCC table entry. MCRLIM_IDX is an 8-bit index into a table containing 256 6-22 ATM ServiceSAR Plus with xBR Traffic Management Example of Multi-Service Tunnels Tunnel B Tunnel C rt-VBR rt-VBR nrt-VBR nrt-VBR ABR ABR ABR UBR UBR UBR Mindspeed Technologies ™ CN8236 Tunnel D rt-VBR nrt-VBR ABR UBR 8236_043 28236-DSH-001-B ...

Page 191

... QPCR_INT2 are used, and so on. 28236-DSH-001-B 6.2 xBR Cell Scheduler Functional Description Table Set NONZERO bits to 1. Set MCR_EXP fields to decimal value of 31 (all-1s). Set MCR_MAN fields to decimal value of 511 (all-1s). Mindspeed Technologies ™ 6.0 Traffic Management 6-18), each containing MCR limit Section 6.2.8.) 6-23 ...

Page 192

... Figure 6-12. ABR Service Category Feedback Control Source Variable Rate Shaping BW_RM (Backward_RM) 6-24 ATM ServiceSAR Plus with xBR Traffic Management illustrates this basic concept. FW_RM (ForWard_RM) Switch Congestion Algorithms ATM Network ( 1 Switches) Mindspeed Technologies ™ CN8236 Destination TA_RM (TurnAround_RM) Internal Congestion Backpressure 8236_044 28236-DSH-001-B ...

Page 193

... SEG VCC Table Entry SCH_STATE Rate Cell Type Decision Decision Cell Segmentation Scheduler Coprocessor SAR Reassembly Coprocessor RSM VCC Table Entry Mindspeed Technologies ™ 6.0 Traffic Management 6.3 ABR Flow Control Manager UNI ATM Network + Destination ABR Cell Stream BACKWARD_RM 8236_045 6-25 ...

Page 194

... ATM ServiceSAR Plus with xBR Traffic Management Figure 6-14. (Backward RM Cell Formatting) Seg VCC Table Entry Segmentation Coprocessor SCH_STATE Turnaround Reassembly Information Coprocessor (Forward RM Cell Processing) Mindspeed Technologies ™ CN8236 Congestion Host Backpressure 8236_046 28236-DSH-001-B ...

Page 195

... Exponent table is indexed by the Explicit Rate exponent. This mapping function normalizes the ER field rate to the CI/NI state-based rate decision. Once normalized, a rate can be chosen based on the minimum of the two rates. 28236-DSH-001-B Mindspeed Technologies ™ 6.0 Traffic Management 6.3 ABR Flow Control Manager ...

Page 196

... First, the Source Nrm Data Cells FW_RM Figure 6-16 The ABR Flow Control Manager may choose to send no cell. This occurs when the VCC has no user data to segment. Mindspeed Technologies ™ CN8236 BW_RM 8236_047 shows a block diagram of the ...

Page 197

... The presence of a condition sets the vector bit 28236-DSH-001-B Data Cell Forward RM Backward RM None Cell Type Action ABR Cell Flow Decision Control Table Manager Mindspeed Technologies ™ 6.0 Traffic Management 6.3 ABR Flow Control Manager ABR-ER Cell Stream 8236_048 Table 6-5 shows the four 6-29 ...

Page 198

... Time since last forward RM transmitted >= TRM TA_PND TA_PND bit set in VCC table entry TA_XMIT TA_XMIT bit set in VCC table entry RUN RUN bit set in VCC table entry shows a typical Cell Decision table. The anchor of the Mindspeed Technologies ™ CN8236 Description 28236-DSH-001-B ...

Page 199

... Nrm = 32 28236-DSH-001-B CELL_INDEX(++) ABR CELL DECISION BLOCK 7-BRM 6-BRM 15-FRM 14-FRM ABR Cell Type Decision Vector (ACDV) [TRM_EXP, TA_PND, TA_XMIT, RUN] = 0001b Mindspeed Technologies ™ 6.0 Traffic Management 6.3 ABR Flow Control Manager 1-DATA 0-NONE 9-FRM 8-FRM 8236_049 6-31 ...

Page 200

... VCC. 6-32 ATM ServiceSAR Plus with xBR Traffic Management Both of these event types may occur in one cell slot. In this case, the CN8236 makes both decisions before updating ACR. Figure 6-18 illustrates a block diagram of Backward RM flow control. Mindspeed Technologies ™ CN8236 28236-DSH-001-B ...