CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet - Page 56

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CN8236EBGB

Manufacturer Part Number
CN8236EBGB
Description
ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
Manufacturer
Mindspeed Technologies
Datasheet

Specifications of CN8236EBGB

Package
388BGA
Traffic Class
ABR|CBR|GFR|UBR|VBR
Utopia Type
Level 1|Level 2
Host Interface
PCI
Maximum Data Rate
155 Mbps
Typical Operating Supply Voltage
3.3 V
Minimum Operating Supply Voltage
3 V

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2.0 Architecture Overview
2.6 Burst FIFO Buffers
Figure 2-10. Data FIFO Buffers
2-22
PCI
2.6 Burst FIFO Buffers
To conserve local memory bandwidth, the CN8236 does not use its local SRAM
as a buffer for incoming or outgoing data. Instead, the CN8236 uses six dedicated
internal FIFO buffers data as follows:
Figure 2-10
Burst FIFO Buffer
Data FIFO Buffer
DMA Slave Read
DMA Slave Write
DMA Master Read
DMA Master Write
Burst FIFO Buffer
Burst FIFO Buffer
• Two DMA master burst FIFO buffers (read =16 words; write, 512 or 2 K
• Two DMA slave burst FIFO buffers, (read = 8 words and write = 64
• One FIFO buffer between the PHY interface and the segmentation coprocessor
• One FIFO buffer between the PHY interface and the reassembly
Command +
PCI Master
PCI Slave
512 or 2 k
words, programmable via CONFIG1 bit 1).
words).
( 1 to 9 cells) . See
coprocessor (64 words).
64
8
16
Mindspeed Technologies
illustrates the data FIFO buffer.
Segmentation
Reassembly
Section
Controller
Controller
ATM ServiceSAR Plus with xBR Traffic Management
4.2.4.
Interface FIFO
Interface FIFO
Transmit PHY
Receive PHY
1 to 9 Cells
64
Interface
PHY
28236-DSH-001-B
CN8236
8236_097

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