CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet - Page 269

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CN8236EBGB

Manufacturer Part Number
CN8236EBGB
Description
ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
Manufacturer
Mindspeed Technologies
Datasheet

Specifications of CN8236EBGB

Package
388BGA
Traffic Class
ABR|CBR|GFR|UBR|VBR
Utopia Type
Level 1|Level 2
Host Interface
PCI
Maximum Data Rate
155 Mbps
Typical Operating Supply Voltage
3.3 V
Minimum Operating Supply Voltage
3 V

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CN8236
ATM ServiceSAR Plus with xBR Traffic Management
28236-DSH-001-B
10.4 Processor Interface Signals
Figure 10-7
i960CA/CF processor. The memory region decoded for PCS* should be set for
N
wait state SRAM), and N
enabled, and burst can be enabled or disabled at the system designer’s option.
Pulling up the i960 CLKMODE input to a logic 1 selects the divide-by-one clock
mode, making i960 PCLK synchronous to SYSCLK.
RAD
and N
Mindspeed Technologies
illustrates the signal interface between the CN8236 device and the
WAD
= 2, N
RDD
XDA
and N
= 1. In addition, external ready control must be
WDD
= 0 or 1 (depending on the use of 0 or 1
10.0 Local Processor Interface
10.4 Processor Interface Signals
10-11

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