CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet - Page 309

• Manufacturer Part Number: CN8236EBGB
• Description: ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8236EBGB

• Package: 388BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 155 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V

CN8236
ATM ServiceSAR Plus with xBR Traffic Management
28236-DSH-001-B
12.9 Receive Cell Synchronization Logic
The receive cell synchronization logic accepts a stream of octets (together with
error and cell boundary indications) from the receive ATM UTOPIA interface and
performs the following functions:
• Maintains a sequence counter that marks the various components of an
• Extracts and discards the HEC byte from each 53-byte ATM cell, leaving
• Formats consecutive 4-byte segments into 32-bit words; thus, the header
• Ensures that a complete cell (exactly 52 bytes) is always written to the
• Sets the RSM_OVFL bit in the HOST_ISTAT0/LP_ISTAT0 registers if an
ATM cell: the 5-byte ATM header, the 1-byte HEC field within the header,
and the 48-byte payload. The sequence counter is also used by the ATM
UTOPIA interface to check cell boundary synchronization.
52 bytes of cell data.
forms the first word, the first four bytes of the payload form the next word,
and so on. A total of thirteen 32-bit words are created from each 52-byte
cell after the HEC byte has been removed. The bytes within each word are
left-justified (big-endian format), that is, the first byte received is the MSB
of the word.
FIFO buffer. If a synchronization error occurs, the FR_SYNC_ERR bit in
the HOST_ISTAT0/LP_ISTAT0 registers is set. The ATM UTOPIA
interface attempts to re-synchronize with the data stream.
octet could not be transferred due to the receive FIFO buffer being full.
Mindspeed Technologies
™
12.9 Receive Cell Synchronization Logic
12.0 ATM UTOPIA Interface
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