CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet - Page 261

• Manufacturer Part Number: CN8236EBGB
• Description: ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8236EBGB

• Package: 388BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 155 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V

CN8236
ATM ServiceSAR Plus with xBR Traffic Management
Table 10-1. Processor Interface Pins (1 of 2)
28236-DSH-001-B
PROCMODE
PCS*
PAS*
PWNR
PADDR[1:0]
PBSEL[1:0]
Signal
Dir
I
I
I
I
I
I
(1)
10.2 Interface Pin Descriptions
The local processor bus interface consists of the control, address, and status
signals described in
information on these interface pins.
Processor interface mode select input—A logic low on this input enables the local
processor mode of operation.
Processor interface chip select—A logic low on this signal in conjunction with a logic low
on PAS* at the rising edge of SYSCLK initiates a memory request to the memory controller.
Processor address strobe— A logic low on this signal in conjunction with a logic low on
PCS* latches the value of PWNR, PBSEL[1:0], PADDR[1:0], and PBE[3:0]* at the rising
edge of SYSCLK.
Processor write/read select—A logic 1 on this input indicates a write cycle; a logic 0
indicates a read cycle. Latched at rising edge of SYSCLK when PAS* and PCS* are active.
Word select address inputs—Indicates the word address for a single cycle access, or the
first word for a multi-cycle burst access. Latched at rising edge of SYSCLK when PAS* and
PCS* are active.
Bank select inputs—Decode to select MCS[3:0]*. Latched at rising edge of SYSCLK when
PAS* and PCS* are active.
Mindspeed Technologies
Table
10-1. Refer to
Description
™
Table 2-1
and
10.0 Local Processor Interface
10.2 Interface Pin Descriptions
Figure 10-7
for further
10-3