CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet - Page 362

• Manufacturer Part Number: CN8236EBGB
• Description: ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8236EBGB

• Package: 388BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 155 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V

15.0 SAR Initialization—Example Tables
15.1 Segmentation Initialization
Table 15-1. Table of Values for Segmentation Control Register Initialization (2 of 2)
15.1.2 Segmentation Internal Memory Control Structures
15-2
Table 15-2. Table of Values for Segmentation Internal Memory Initialization
SEG_VBASE
(SEG Virtual Channel
Connection Base
Address Register)
SEG_PMBASE
(SEG PM Base Address
Register)
SEG_TXBASE
(Segmentation
Transmit Queue Base
Register)
SEG_SQ_BASE Table
Entry 0
(SEG Status Queue
Base Table Entry 0)
SEG_TQ_BASE Table
Entry 0
(SEG Transmit Queue
Base Table Entry 0)
Register
Table
SEG_SCHB
SEG_VCCB
SEG_BCKB
SEG_PMB
SEG_TXB
XMIT_INTERVAL
TX_EN
BASE_PNTR
LOCAL
SIZE
WRITE
READ_UD
Reserved
READ_UD_PNTR
LOCAL
UPDATE
READ
Reserved
Before segmentation is enabled, the host must allocate and initialize all of the
segmentation internal memory control structures.
values for each field.
Field
Field
Mindspeed Technologies
Initialized Value
Initialized Value
0x17D
0x1AD
0x13D
0x1A5
0x219
0x20
0x1C00
0x8
0x40
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0
0
ATM ServiceSAR Plus with xBR Traffic Management
Schedule table starts at 0xD280 in SAR-shared
memory.
SEG VCC table starts at 0xBE80 in SAR-shared
memory.
VBR bucket table starts at 0x10C80 in SAR-shared
memory.
PM table starts at 0xD680 in SAR-shared memory.
Transmit queues start at 0x9E80 in SAR-shared
memory.
Transmit queue update interval set to 32.
Transmit queues 0 through 8 are enabled.
Base address of status queue 0 is 0x1C00.
Status queue 0 resides in host memory.
Size of status queue 0 is 64 entries.
Must be initialized to 0.
Must be initialized to 0.
Must be initialized to 0.
READ_UD located in host memory.
Must be initialized to 0.
Must be initialized to 0.
Location of READ_UD is at 0x100.
Must be initialized to 0.
™
Table 15-2
Notes
Notes
lists the initialized
28236-DSH-001-B
CN8236