CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet - Page 44

• Manufacturer Part Number: CN8236EBGB
• Description: ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8236EBGB

• Package: 388BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 155 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V

2.0 Architecture Overview
2.2 High Performance Host Architecture with Buffer Isolation
2.2.5 Write-only Control/Status
Figure 2-8. Write-Only Control and Status Architecture
2.2.6 Scatter/Gather DMA
2-10
Host
Figure 2-8
manages the CN8236 ATM terminal using write-only control and status queues.
This architecture minimizes PCI bus utilization by eliminating reads from control
activities. PCI writes use the bus much more efficiently than PCI reads. During a
PCI write, the Bus Master can post the write data to an internal FIFO buffer in the
slave, terminate the transaction, and immediately release the bus. On the other
hand, during PCI reads, the Bus Master retrieves the data from the slave while
holding the bus. Since the data retrieval takes some time, reads increase the PCI
bus utilization time for each transaction. The CN8236 eliminates read operations
except for burst reads to gather segmentation data.
The CN8236’s Direct Memory Access (DMA) coprocessor works in close
conjunction with the segmentation and reassembly coprocessors to gain access to
the PCI bus, transfer the requested data, and notify the segmentation or
reassembly coprocessor that the transfer is complete. The DMA coprocessor
transfers all data using the read and write burst buffers in the PCI Bus Interface.
accesses for data, or 1- to 4-word accesses for control and status messages.
to the segmentation coprocessor using a gather DMA method. For incoming
messages, the DMA coprocessor moves data from the reassembly coprocessor to
host memory using a scatter DMA method.
not aligned on word boundaries. It also selectively transfers data to comply with
either a big endian or little endian host data structure.
Write-only architecture reduces PCI utilization dramatically,
In general, two types of transactions are processed: 12- or 14-word burst
For outgoing messages, the DMA coprocessor moves data from host memory
The DMA coprocessor can handle transfers from the PCI bus with data that is
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as reads take many more clock cycles.
illustrates the CN8236’s write-only PCI control architecture. The host
SEG Data (Read Multiples)
RSM Data (Writes)
Control
Status
PCI
ATM ServiceSAR Plus with xBR Traffic Management
™
CN8236
28236-DSH-001-B
CN8236
8236_008