CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet - Page 67

• Manufacturer Part Number: CN8236EBGB
• Description: ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8236EBGB

• Package: 388BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 155 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V

CN8236
ATM ServiceSAR Plus with xBR Traffic Management
Table 2-1. Hardware Signal Definitions (5 of 6)
28236-DSH-001-B
PDAEN*
PFAIL*
PINT*
PRST*
LDATA[31:0]
LADDR[18:2]
LADDR[1:0]
MCS[3:0]*
MOE*
MWE[3:0]*
MWR*
RAMMODE
CLK2X
SYSCLK
CLKD3
STAT[1,0]
SCHREF
Pin Label
Data/Address Enable
Self-Test Failed
Interrupt Output
Reset Output
Memory Data Bus
Memory Address Bus
Memory Address Bus
Memory Bank Chip
Selects
Memory Read Enable
Memory Byte Write
Enables
Write Enable
RAM Mode Select
2x Clock Input
System Clock Output
Divide by 3 Clock
Output
SAR Status
Scheduler Reference
Clock
Signal Name
Mindspeed Technologies
I/O
OD
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
I
I
I
I
Connected to the output enable input of the bidirectional
transceivers and buffers used to isolate the CN8236 data and
address bus from the local processor. In standalone mode,
this input is connected to the PHY device’s interrupt output(s).
The local processor can indicate a failure of its internal
self-test or initialization processes by asserting the PFAIL*
input to the CN8236.
Asserted by the CN8236 to the local processor to signal an
interrupt request in local processor mode.
Asserted by the CN8236 to the local processor whenever the
HRST* input is asserted, or when the LP_ENABLE bit in the
CONFIG0 register is a logic low.
Data I/O bus. Used for memory reads and writes, and control
and status register access by the local processor.
Address I/O bus. Used for memory reads and writes, and
control and status register access by the local processor.
The two least significant bits of address I/O bus. Used for
memory reads and writes, and control and status register
access by the local processor.
Selects one of four addressable banks of SRAM memory.
Indicates that a read cycle is proceeding and the memory
device output buffers should be enabled, driving data onto the
LDATA[31:0] lines.
Memory byte write enables for by_4 or by_8 SRAMs. For
by_16 devices, these outputs are byte enables that are active
on writes and reads.
Memory write enable for by_16 SRAMs.
Selects RAM chips supported.
1 = by_16 memory devices
0 = by_4 or by_8 memory devices
Double frequency (from SYSCLK) CMOS level input (66 MHz
maximum).
This divide by 2 of CLK2X is the internal system clock and the
external system clock (33 MHz maximum).
This output clock is a 50% duty cycle, one-third divide of
CLK2X; it can be used for the UTOPIA interface clock (22 MHz
maximum).
CN8236 internal status outputs. Internal status controlled by
the STAT_MODE[4:0] field in the CONFIG0 Register.
External Scheduler Reference Clock.
™
2.10 Logic Diagram and Pin Descriptions
Definition
2.0 Architecture Overview
2-33