CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet - Page 101

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CN8236EBGB

Manufacturer Part Number
CN8236EBGB
Description
ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
Manufacturer
Mindspeed Technologies
Datasheet

Specifications of CN8236EBGB

Package
388BGA
Traffic Class
ABR|CBR|GFR|UBR|VBR
Utopia Type
Level 1|Level 2
Host Interface
PCI
Maximum Data Rate
155 Mbps
Typical Operating Supply Voltage
3.3 V
Minimum Operating Supply Voltage
3 V

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CN8236
ATM ServiceSAR Plus with xBR Traffic Management
4.3.4 Transmit Queues
Table 4-15. Transmit Queue Entry Field Descriptions
28236-DSH-001-B
Table 4-14. Transmit Queue Entry Format
Word 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VLD
LINK_HEAD
FIND_CHAIN
SEG_BD_PNTR
0
4.3.4.1 Entry Format
Field Name
Reserved
0 = Entry invalid. Waiting for the host to submit new data for segmentation.
1 = Entry valid. The SAR processes the entry when its read pointer into the queue advances to this
Written to 1 by the host when submitting a new entry. The SAR clears this bit to 0 when it has
successfully linked the buffer descriptor chain to the VCC table.
0 = The CN8236 links the new descriptor chain at the end of the existing chain on the VCC.
1 = The CN8236 links the new descriptor chain at the head of the existing chain.
If this bit is set, the buffer must contain data for at least one cell. Only a single buffer descriptor can
be linked to a transmit queue entry when this bit is set.
This bit is intended for use with the buffer descriptor SINGLE option to send in-line management cells
with reduced latency.
NOTE(S):
with LINK_HEAD set. To do otherwise may result in corrupted segmentation data.
Indicates the SAR is searching for the end of the buffer descriptor chain.
The host always writes this bit to 0.
Points to the first buffer descriptor in the new buffer descriptor chain. Bits 22:2 of the address are
specified; the two least significant bits of the pointer are assumed to be 0 (word-aligned).
entry.
The host submits chains of SBDs to the CN8236 by writing a single word
transmit queue entry.
entries.
It is mandatory that the SINGLE option is set in the buffer descriptor for any Tx Queue entry
Mindspeed Technologies
Table 4-14
Description
and
SEG_BD_PNTR
Table 4-15
4.3 Segmentation Control and Data Structures
describe the format of these
4.0 Segmentation Coprocessor
Rsvd
4-23

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