CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet - Page 127

• Manufacturer Part Number: CN8236EBGB
• Description: ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8236EBGB

• Package: 388BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 155 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V

CN8236
ATM ServiceSAR Plus with xBR Traffic Management
5.3.4 ATM Header Processing
5.3.5 BOM Synchronization Signal
28236-DSH-001-B
Table 5-3. Prepend Index Table Format
Word 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
5.3.5.1 Prepend Index
0
Reserved
ATM level CI and CLP are mapped to the CPCS-PDU status queue entry in the
following manner:
The STAT[1:0] output pins can be programmed to provide an indication that a
BOM cell is being written across the PCI bus. Additional external circuitry could
snoop the BOM cell for a service level protocol header and perform appropriate
lookup as the CPCS-PDU is being reassembled. To configure the STAT pins, set
the STATMODE field in the CONFIG0 register to 0x00. The STAT output truth
table illustrated in
Table 5-2. STAT Output Pin Values for BOM Synchronization
External circuitry would detect a BOM cell transfer by detecting a logic high on
either STAT pin during a SAR PCI master write address cycle. External circuitry
can then snoop the subsequent data cycles of the BOM cell transfer to extract the
appropriate protocol overhead.
In order to allow protocol processing to start upon reception of the BOM cell, the
VCC_INDEX can be optionally prepended to the beginning of the BOM cell.
This, in conjuction with the BOM SYNC signals via the STAT pins, can be used
to eliminate the need for a host lookup process before starting protocol
processing. When RSM_CTRL0(PREPEND_INDEX) is a logic high, the
VCC_INDEX is appended to the BOM cell as follows:
NOT BOM
AAL5 BOM
AAL0 BOM
NOT USED
• LP: value of the ATM Header CLP bit ORed across all cells in a
• CI_LAST: value of ATM Header PTI[1] bit in last cell of CPCS-PDU.
• CI: value of ATM Header PTI[1] bit ORed across all cells in a CPCS-PDU.
The STAT output pins are valid during a SAR PCI master write address cycle.
CPCS-PDU.
Mindspeed Technologies
Table
5-2.
STAT[1]
0
0
1
1
™
VCC_INDEX
5.0 Reassembly Coprocessor
5.3 CPCS-PDU Processing
STAT[0]
0
1
0
1
5-17