CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet - Page 73

• Manufacturer Part Number: CN8236EBGB
• Description: ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8236EBGB

• Package: 388BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 155 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V

CN8236
ATM ServiceSAR Plus with xBR Traffic Management
3.3.1 Write-only Control Queues
28236-DSH-001-B
3.3 Write-only Control and Status
For host-based applications, the host manages the CN8236 SAR using write-only
control and status queues. This architecture minimizes PCI bus use by eliminating
reads from the control path. PCI writes use the bus much more efficiently than
PCI reads. During a PCI write, the target can post the write data in an internal
FIFO buffer, terminate the transaction, and immediately release the bus. On the
other hand, during reads, the target retrieves the data while holding the bus. Since
the data retrieval takes some time, reads increase the PCI bus utilization.
(PDU) fetches. All control and status transactions are writes. This section
describes the management of write-only queues. The purpose and entries of each
class of queue are described in later chapters.
Table 3-1. CN8236 Control and Status Queues
The host controls run-time segmentation and reassembly through write-only
control queues. There are two types of control queues—the segmentation transmit
queues and the reassembly free buffer queues. The host submits buffers of PDU
data for segmentation on the transmit queues and supplies empty buffers for
received data on the free buffer queues. Each type of queue is managed as a
write-only control queue.
register pointer. To allow multiple clients, the CN8236 supports 32 queues of
each type. The SAR and host manage each queue independently, through queue
management variables. The SAR stores its variables in internal registers called
base tables. The host maintains its own variables within its driver. Each queue
contains a programmable number of queue entries.
The CN8236’s write-only architecture uses reads only for segmentation data
Table 3-1
These queues reside in SAR-shared memory at a location defined by a base
Control
Status
Type
Mindspeed Technologies
defines the CN8236 control and status queues.
Segmentation status queue
Transmit queue
Segmentation
™
3.3 Write-only Control and Status
Reassembly status queue
Free buffer queue
Reassembly
3.0 Host Interface
3-5