CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet - Page 237

• Manufacturer Part Number: CN8236EBGB
• Description: ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8236EBGB

• Package: 388BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 155 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V

CN8236
ATM ServiceSAR Plus with xBR Traffic Management
7.2.1 Key OAM-Related Fields for OAM Segmentation
28236-DSH-001-B
7.2.1.1 Segmentation
7.2.1.3 Segmentation
7.2.1.2 Low Latency
Buffer Descriptors
7.2.1.4 F4 Flow
Transmission
Status Queue
7.2 Segmentation of OAM Cells
The host (or local processor) places OAM cells in a single buffer, and thus
allocates a single segmentation buffer descriptor (SBD) for the OAM cell data
buffer, not a linked list of SBDs.
available transmit queue entry, and sets the VLD bit to 1.
submits the OAM cell data buffer to the xBR Traffic Manager and the cell is thus
scheduled for transmission.
Several fields in the SBD entry are used to facilitate segmentation of OAM cells.
For low latency, the LINK_HEAD bit in the transmit queue entry should be set to
a logic high. This tells the CN8236 to link the buffer chain at the head of the
existing chain for the corresponding VCC. This bit is intended for use with the
SEG buffer descriptor’s SINGLE option, to send in-line OAM cells. Only a single
SEG buffer descriptor can be linked to a transmit queue entry when this bit is set.
a partial PDU, to ensure correct segmentation.
The SINGLE bit in the SEG status queue entry should be set to a logic high. This
bit is set if the SINGLE option in the AAL_OPT field of the SEG buffer
descriptor is set. This bit indicates a special buffer is in use, rather than the
normal system-assigned buffers for normal CPCS-PDUs.
For F4 flow operation, a separate VCC table entry must be configured.
The host (or local processor) then writes a pointer to that SBD in the next
When the segmentation coprocessor processes that transmit queue entry, it
• Set the 2-bit AAL_OPT field to SINGLE (value = 01). This enables
• Set the OAM_STAT bit to a logic high. The CN8236 now reports status to
• Set the single-bit HEADER_MOD field to a logic 1. This activates the
• The VCI_DATA field set to a value of three (segment cell) or four
• The PTI_DATA field set to a value of 100 (segment cell) or 101
• Set the AAL_MODE field to 01 (AAL0).
• Set both BOM and EOM bits to 0.
• Set the CRC10 bit to a logic high.
This bit must also be set if the OAM SBD is placed on the transmit queue after
reading 48 octets from a single buffer to form a single ATM cell.
the OAM-dedicated OAM_STAT_ID identified in the SEG_CTRL
register, instead of the STAT specified in the SEG VCC table entry.
WR_PTI and WR_VCI bits in the buffer descriptor, which signal the
CN8236 to overwrite the ATM header PTI and VCI fields for that cell with
the values from the PTI_DATA and VCI_DATA fields. In this way, F4 and
F5 flow OAM cells can be generated by the CN8236.
(end-to-end cell) generates an F4 flow OAM cell.
(end-to-end cell) generates an F5 flow OAM cell.
Mindspeed Technologies
™
7.2 Segmentation of OAM Cells
7.0 OAM Functions
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