CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet - Page 90

• Manufacturer Part Number: CN8236EBGB
• Description: ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8236EBGB

• Package: 388BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 155 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V

4.0 Segmentation Coprocessor
4.2 Segmentation Functional Description
4.2.4 ATM PHY Layer Interface
4-12
4.2.4.1 Head-of-Line
Flushing (HoLF)
Once the segmentation coprocessor has formed an ATM cell, the CN8236
transfers the cell to the transmit FIFO buffer. The user chooses the length of this
FIFO buffer, with possible sizes from one to nine cells. The FIFO buffer depth is
programmable, since there is a trade-off between absorbing PCI latency with a
longer FIFO buffer, and introducing greater jitter.
Chapter
FIFO buffer, the cell passes through the FIFO buffer to the PHY layer interface
circuits.
If the SAR is set up as a UTOPIA Master in multi-phy operations, cells are
transmitted to a PHY device after the PHY indicated that it can receive another
cell by asserting its UTOPIA CLAV signal. The UTOPIA Master waits until it
receives the CLAV signal from the PHY device, and therefore blocks the
transmission of all other cells in the transmit FIFO. If this PHY device stops
working, all other PHY devices are blocked. This is called head-of-line blocking.
flush the blocking cell out of the transmit FIFO is incorporated (Head-of-Line
Flushing). This mechanism is enabled by setting the TX_FIFO_FLUSH_EN bit
in the CONFIG1 register.
0 and increased based on the UTOPIA tx_clk. Once the counter reaches the
values TX_CNTR set by the user in the CSR register, the cell is discarded, and the
bit corresponding to the blocking PHY is set in the TX_PORT_STATUS register.
The counter is reset automatically. If any of the eight bits in the TX_STATUS
register is set, TX_DISCARD in HOST_ISTAT1 and LP_ISTAT1 are set. If the
corresponding mask bit EN_TX_DISCARD in HOST_IMASK1 or LP_IMASK1
is set, an interrupt is generated. The TX_DISCARD is cleared once the
TX_STATUS register is read by the host.
NOTE:
Then all cells belonging to this port are discarded or flushed. Ports are disabled by
setting the corresponding bit in the TX_PORT_CTRL register. If a port x is
disabled and a cell pertaining to port x is discarded, bit x in TX_STATUS is not
set, and therefore no interrupt is generated.
65,535 is recommended. For specific DSL applications with variable rate PHY
devices, a value between 50 and 100 is suggested.
In order to avoid head-of-line blocking in the transmit FIFO, a mechanism to
When the UTOPIA Master puts out the address of a PHY, a counter is reset to
The user might decide to disable a specific port on the UTOPIA interface.
For fault-tolerant multi-phy operations, a maximum TX_CNTR value of
The cell discard does not disable the port.
6.0, discusses this trade-off in greater depth. Once sent to the transmit
Mindspeed Technologies
ATM ServiceSAR Plus with xBR Traffic Management
™
Section
6.2.3.3, in the
28236-DSH-001-B
CN8236