MT8941BP Mitel, MT8941BP Datasheet
MT8941BP
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MT8941BP Summary of contents
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... Yo CMOS ST-BUS Advanced T1/CEPT Digital Trunk PLL DS5186 MT8941BE MT8941BP Description The MT8941B is a dual digital phase-locked loop providing the timing and synchronization signals for the T1 or CEPT transmission links and the ST-BUS. The first PLL provides the T1 clock (1.544 MHz) synchronized to the input frame pulse at 8 kHz ...
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MT8941B CMOS 1 24 ENVC 2 23 MS0 22 C12i 3 21 MS1 F0i 19 F0b 6 18 MS2 7 17 C16i 8 ENC4o 16 9 C8Kb 15 10 C4o VSS 12 24 PIN ...
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Pin Description (continued) Pin # Name DIP PLCC 13 15 C4b Clock 4.096 MHz- Bidirectional (TTL compatible input and Totem-pole output) - When the mode select bit MS3 (pin 17) is HIGH, it provides the 4.096 MHz clock output with ...
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... Figure 4. The maximum phase variation for DPLL #1 is 324 ns and for DPLL # However, this phase difference can be absorbed by the input jitter buffer of Mitel’s T1/CEPT devices. The no-correction window acts as a filter for low frequency jitter and wander since the DPLL does not track the reference signal inside it ...
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... The inputs MS0 to MS3 are used to select the operating mode of the MT8941B, see Tables All the outputs are controlled to the high impedance condition by their respective enable controls. The uncommitted NAND gate is available for use in applications involving Mitel’s MT8976/ MH89760 (T1 Interfaces) and MT8979/MH89790 Interfaces). ...
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MT8941B CMOS The operation of DPLL #2 in SINGLE CLOCK-1 mode is identical to SINGLE CLOCK-2 mode, providing the CEPT and ST-BUS compatible timing signals synchro-nized to the internal 8 kHz signal obtained from DPLL#1 in DIVIDE mode. SINGLE CLOCK-1 ...
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When MS3 is HIGH, DPLL #2 operates in any of the major modes selected by MS0 and MS1. When MS3 is LOW, it overrides the major mode selected and DPLL#2 accepts an external clock of 4.096 MHz on C4b (pin ...
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MT8941B CMOS Figure 5- The Spectrum of the Inherent Jitter for either PLL Figure 6 - The Jitter Transfer Function for PLL1 Figure 7 -The Jitter Transfer Function for PLL2 8 ...
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DPLL #1 and DPLL #2 to have maximum tolerances of 32ppm and respectively. However, if DPLL #1 and DPLL #2 are daisy-chained as shown in Figures 9 and 10, the output clock tolerance of DPLL #1 will be ...
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... The following figures illustrates how the MT8941B can be used in a minimum component count approach in providing the timing and synchro- In nization signals for the Mitel T1 or CEPT interfaces, of the and the ST-BUS. The hardware selectable modes and the independent control over each PLL adds fl ...
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... CEPT Transmission Link The MT8941B can be used to provide the timing and synchronization signals for the MH89790/790B, Mitel’s CEPT (30+2) Digital Trunk Interface Hybrid. Since the operational frequencies of the ST-BUS and the CEPT primary multiplex digital trunk are the same, only DPLL #2 is required. ...
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MT8941B CMOS MS0 MS1 MS2 MS3 F0i C12i EN CV C8Kb Crystal Clock C16i (16.384 MHz) EN C4o EN C2o V SS Figure 12 - Synchronization at the Slave End of the CEPT Digital Transmission Link Figures 11 and 12 ...
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Absolute Maximum Ratings* Parameter 1 Supply Voltage 2 Voltage on any pin 3 Input/Output Diode Current 4 Output Source or Sink Current 5 DC Supply or Ground Current 6 Storage Temperature 7 Package Power Dissipation * Exceeding these values may ...
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MT8941B CMOS AC Electrical Characteristics Characteristics 1 CVb output (1.544 MHz) rise time 2 CVb output (1.544 MHz) fall time D 3 CVb output (1.544 MHz) clock P period CVb output (1.544 MHz) clock width (HIGH) #1 ...
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V IH CVb ICHL C8HH V OH C8Kb F0b FPL t W4oH V OH C4b W4oL V OH C4o V OL ...
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MT8941B CMOS AC Electrical Characteristics Characteristics 1 C4b output clock period 2 C4b output clock width (HIGH) 3 C4b output clock width (LOW) 4 C4b output clock rise time 5 C4b clock output fall time 6 Frame pulse output delay ...
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AC Electrical Characteristics Characteristics 1 Master clocks input rise time 2 Master clocks input fall time 3 C Master clock period L (12.352MHz Master clock period C (16.384MHz Duty Cycle of master clocks 6 Lock-in ...
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MT8941B CMOS AC Electrical Characteristics Characteristics 1 Delay from Enable to Output (HIGH to THREE STATE Delay from Enable to Output U (LOW to THREE STATE Delay from Enable to Output U (THREE STATE to ...
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Package Outlines Dim D General- (lead coplanarity) A Notes Not ...
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Package Outlines Notes Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) Plastic Dual-In-Line Packages (PDIP Suffix 8-Pin DIM Plastic Min Max A 0.210 (5.33) A 0.115 (2.92) ...
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Notes Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) Plastic Dual-In-Line Packages (PDIP Suffix 22-Pin DIM Plastic Min Max A 0.210 (5.33) A 0.125 (3.18) 0.195 ...
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... Mitel. This publication is issued to provide information only and (unless agreed by Mitel in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Mitel without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specifi ...