DP5380V National Semiconductor, DP5380V Datasheet
DP5380V
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DP5380V Summary of contents
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... Data transfers can be performed by programmed-I O pseu- do-DMA or via a DMA controller The ASI easily interfaces Connection Diagram TRI-STATE is a registered trademark of National Semiconductor Corporation PAL is a registered trademark of and used under license from Monolithic Memories Inc C 1995 National Semiconductor Corporation TL F 9756 ...
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Functional Description 1 1 OVERVIEW The ASI is designed to be used as a peripheral device in a P-based application and appears as a number of read write registers Write registers are programmed to select de- sired functions ...
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Functional Description INTERFACE Figure 2 shows a block diagram of the ASI Key blocks with- in the ASI are Read Write registers with associated decode and control logic interrupt and DMA logic SCSI bus arbitra- ...
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Functional Description The ASI arbitration logic controls arbitration for use of the SCSI bus The P programs the SCSI device ID into the ASI then sets the ARBITRATE bit The INITIATOR COM- MAND REGISTER (ICR) is read to ...
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... VCC GND decoupling and power distribution is mandatory GND Connection Diagrams Function required Because of very large switching currents good a Order Number DP5380N See NS Package Number N40A TL F 9756 – 4 Order Number DP5380V See NS Package Number V44A TL F 9756 – ...
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Register Description 3 1 GENERAL The DP5380 ASI is a register-based device with eight ad- dressable locations Some addresses have dual functions depending upon whether they are being read from or written to Device operation is described in ...
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Register Description (Continued) ACK Assert Acknowledge 0 Deassert ACK 1 Assert SCSI ACK signal The MR2 TARGET MODE bit must also be false to assert the signal Reading the ICR reflects the state of this bit DIFF Differential ...
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Register Description (Continued) DMA transfers the SCSI phase lines (C D MSG I O) must match the contents of the TCR for transfers to occur A phase mismatch halts DMA transfers and generates an in- terrupt Bit 7 ...
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Register Description (Continued) START DMA SEND (SDS) 0 Bits HA 5 Write-Only This write-only register is used to start a DMA send opera- tion A write of don’t-care data should be the last thing done by the P ...
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Device Operation (Continued) device asserts SEL during arbitration If the LA bit is 0 the data bus is read via the CSD register The data is examined to resolve ID priorities If this device is the highest ID ...
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Device Operation (Continued) The interface to the DMA controller uses the DRQ DACK EOP lines in non-block mode Each byte is requested (DRQ) and ack’d (DACK) Representative timing for a DMA read is shown in Figure 4 8 ...
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Device Operation (Continued) Target Send *DATA IN PHASE* Program DMA Controller TCR 01h *phase* ICR 09h MR2 4Ah SDS 0 *Start DMA Send* while (NOT interrupt) idle if(NOT(BSR End of DMA) error else *DMA end* repeat while (CSB ...
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Device Operation (Continued) Resetting the bit disables all DMA logic and thus should only be reset at the True End of DMA condition Additionally all DMA logic is reset so this bit must be reset then set again ...
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Interrupts (Continued) If SCSI parity checking is enabled it will be checked and should be valid Following an interrupt the BSR and CSD should contain the values shown below Bit EDMA ...
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Application Guide (Continued) All the interface signal requirements are satisfied by a PAL device The memory interface is not shown only the rele- vant DMAC and P lines are included The ASI data and address lines connect directly ...
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Application Guide (Continued) CSASI IORQ*A7*A6*A5*A4*AEN ASI reg R W chip select ADACK IORQ*A7*A6*A5*A4*RD P pseudo-DMA cycle IORQ*A7*A6*A5*A4*WR IORQ*A7*A6*A5*A4*RD P pseudo-DMA with EOP IORQ*A7*A6*A5*A4*WR DDACK DMAC DMA cycle IF(AEN)AEOP I0RQ*A7*A6*A5*A4*RD IORQ*A7*A6*A5*A4*WR IF(DDACK*AREADY*INT)DEOP DDACK*AREADY*INT DMA cycle with error CSDMA I0RQ*A7*A6*A5*A4 ...
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... Absolute Maximum Ratings If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage ( Input Voltage ( Output Voltage ( OUT Electrical Characteristics ...
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AC Electrical Characteristics Symbol Parameter bfas BSY False to Arbitrate Start bfbc BSY False to Bus Clear rst RESET Pulse Width stbc SEL True to Bus Clear 10 1 ARBITRATION RESET all parameters are preliminary ...
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AC Electrical Characteristics all parameters are preliminary and subject to change without notice (Continued) Symbol Parameter ahr Address Hold from End of Read Enable (Note 1) ahw Address Hold from End of Write Enable (Note 2) as Address ...
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AC Electrical Characteristics 10 5 DMA WRITE (NON-BLOCK MODE) TARGET SEND Symbol Parameter afrt ACK False to REQ True (DACK or WR False) atdt ACK True to DRQ True (Target) atrf ACK True to REQ False (Target) dfdt ...
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AC Electrical Characteristics 10 6 DMA WRITE (NON-BLOCK MODE) INITIATOR SEND Symbol Parameter dfaf DACK False to ACK False (Non-Block Initiator Send) dfdt DACK False to DRQ True dhi SCSI Data Hold from Write Enable Initiator dhwr DMA ...
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AC Electrical Characteristics 10 7 DMA READ (NON-BLOCK MODE) TARGET RECEIVE Symbol Parameter afrt ACK False to REQ True (DACK or WR False) atdt ACK True to DRQ True (Target) atrf ACK True to REQ False (Target) ddv ...
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AC Electrical Characteristics 10 8 DMA READ (NON-BLOCK MODE) INITIATOR RECEIVE Symbol Parameter ddv DMA Data Valid from Read Enable (Note 1) dfaf DACK False to ACK False (REQ False Non-block In rx) dfdt DACK False to DRQ ...
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AC Electrical Characteristics 10 9 DMA WRITE (BLOCK MODE) TARGET SEND Symbol Parameter afrt ACK False to REQ True (DACK or WR False) atrf ACK True to REQ False (Target) atrt ACK True to READY True (Block Mode ...
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AC Electrical Characteristics 10 10 DMA WRITE (BLOCK MODE) INITIATOR SEND Symbol Parameter dhi SCSI Data Hold from Write Enable Initiator dhwr DMA Data Hold Time from End of WR dswd Data Setup to End of DMA Write ...
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AC Electrical Characteristics 10 11 DMA READ (BLOCK MODE) TARGET RECEIVE Symbol Parameter afrt ACK False to REQ True (DACK or WR False) atrf ACK True to REQ False atyt ACK True to READY True ddv DMA Data ...
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AC Electrical Characteristics 10 12 DMA READ (BLOCK MODE) INITIATOR RECEIVE Symbol Parameter ddv DMA Data Valid from Read Enable (Note 1) dhr Data Hold from End of Read Enable (Notes 1 2) dhra SCSI Data Hold from ...
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Appendix A1 Arbitration and (Re)Selection Only set ATN if Select with ATN is desired TL F 9756– 9756– 25 ...
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Appendix A1 (Continued) Command Transfer (Initiator) Command Transfer (Target 9756 – 9756 – 27 ...
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Appendix A2 READ Bit 7 Current SCSI Data (CSD) DB7 DB6 DB5 DB4 DB3 DB2 Bit 7 Initiator Command Register (ICR) RST AIP LA ACK BSY SEL Bit 7 Mode Register 2 (MR2) BLK TARG PCHK PINT EOP BSY Bit ...
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Physical Dimensions inches (millimeters) Molded Dual-In-Line Package (N) Order Number DP5380N NS Package Number N40A 31 ...
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... National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications Plastic Chip Carrier (V) Order Number DP5380V NS Package Number V44A 2 A critical component is any component of a life ...