ADL5310ACP-R2 Analog Devices Inc, ADL5310ACP-R2 Datasheet - Page 14

• Manufacturer Part Number: ADL5310ACP-R2
• Description: IC LOGARITHMIC CONV DUAL 24LFCSP
• Manufacturer: Analog Devices Inc
• Type: Logarithmic Converterr

Specifications of ADL5310ACP-R2

• Design Resources: Interfacing ADL5315 to Translinear Logarithmic Amplifier (CN0056) Interfacing ADL5317 High Side Current Mirror to a Translinear Logarithmic Amplifier in an Avalanche Photodiode Power Detector
• Applications: Fiber Optics
• Mounting Type: Surface Mount
• Package / Case: 24-LFCSP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ADL5310ACP-R2CT

ADL5310
The optional capacitor from LOG1 (LOG2) to ground forms a
single-pole, low-pass filter in combination with the 5 kΩ resis-
tance at this pin. For example, when using a C
3 dB corner frequency is 3.2 kHz. Such filtering is useful in
minimizing the output noise, particularly when I
Multipole filters are more effective in reducing the total noise;
examples are provided in the AD8304 data sheet.
Because the basic scaling at LOG1 (LOG2) is 0.2 V/decade,
and thus a 4 V swing at the buffer output would correspond to
20 decades, it is often useful to raise the slope to make better use
of the rail-to-rail voltage range. For illustrative purposes, both
channels in Figure 34 provide a 0.5 V/decade overall slope
(25 mV/dB). Thus, using I
I
0.5 V to 3.5 V, corresponding to a dynamic range of 120 dB
(electrical, that is, 60 dB optical power).
Further information on adjusting the slope and intercept, using
a negative supply, and additional operations can be found in the
AD8305 data sheet.
CALIBRATION
Each channel of the ADL5310 has a nominal slope and intercept
at LOG1 (LOG2) of 200 mV/decade and 300 pA, respectively,
when configured as shown in Figure 34. These values are
untrimmed and the slope alone may vary by as much as 7.5%
over temperature. For this reason, it is recommended that a
simple calibration be done to achieve increased accuracy. While
the ADL5310 offers improved slope and intercept matching
compared to a randomly selected pair of AD8305 log amps, the
specified accuracy can only be achieved by calibrating each
channel individually.
PD
Figure 35. Using 2-Point Calibration to Increase Measurement Accuracy
= 3 nA to 1.4 V at I
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1n
10n
MEASURED OUTPUT
100n
PD
IDEAL OUTPUT
= 3 mA; the buffer output runs from
UNCALIBRATED ERROR
REF
1µ
= 3 μA, V
I
PD
(A)
10µ
CALIBRATED ERROR
LOG
100µ
runs from 0.2 V at
FLT
1m
of 10 nF, the
PD
is small.
10m
4
3
2
1
0
–1
–2
–3
Rev. A | Page 14 of 20
Figure 35 shows the improvement in accuracy when using a 2-
point calibration method. To perform this calibration,
apply two known currents, I
range between 10 nA and 1 mA. Measure the resulting output,
V
intercept b:
The same calibration could be performed with two known
optical powers, P
entire measurement system while providing a simplified
relationship between the incident optical power and V
voltage:
The uncalibrated error line in Figure 35 was generated assum-
ing that the slope of the measured output was 200 mV/decade
when in fact it was actually 194 mV/decade. Correcting for this
discrepancy decreased measurement error up to 3 dB.
MINIMIZING CROSSTALK
Combining two high-dynamic-range logarithmic converters in
one IC carries potential pitfalls concerning channel-to-channel
isolation. Special care must be taken in several areas to ensure
acceptable crosstalk performance, particularly when one or both
channels may operate at very low input currents. Fastidious sup-
ply bypassing—also necessary for overall stability—and careful
board layout are important first steps for minimizing crosstalk.
While the shared bias circuitry improves channel-to-channel
matching and reduces power consumption, it is also a source of
crosstalk that must be mitigated. The VSUM pins, which are
internally shorted, should be bypassed with at least 1 nF to
ground, and 20 nF is recommended for operation at the lowest
currents (<30 nA). VSUM is of particular importance because it
acts as a reference voltage input for each input system, but
without the bandwidth limitation at low currents that the
primary inputs incur. Disturbances at the VSUM pin that are
well within the bandwidth of the input are tracked by the loop
and do not generate disturbances at the output (aside from the
generally minor perturbation in reference currents caused by
voltage variations at IRF1 and IRF2).
For this reason, the pole frequency at VSUM, which has a 16 kΩ
typical source resistance, should be set below the minimum
input system bandwidth for the lowest input current to be
encountered. Because the low frequency noise at VSUM is also
tracked by the loop within its available bandwidth, this is also a
criterion for reducing the noise contribution at the output from
the thermal noise of the 16 kΩ source resistance at VSUM.
1
and V
m = (V
b = V
m = (V
b = V
2
, respectively, and calculate the slope m and the
1
1
– m × log
– m × P1
1
1
– V
– V
2
1
2
)/[log
)/(P
and P
10
1
(I
– P
10
2
1
. This allows for calibration of the
(I
)
2
1
)
) – log
1
and I
10
2
(I
, in the linear operating
2
)]
LOG
(10)
(7)
(8)
(9)