CS5530 National Semiconductor, CS5530 Datasheet

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CS5530

Manufacturer Part Number
CS5530
Description
Manufacturer
National Semiconductor
Datasheet
© 2000 National Semiconductor Corporation
Geode™ CS5530 I/O Companion
Multi-Function South Bridge
General Description
The CS5530 I/O companion is designed to work in con-
junction with the GXLV and GXm series processors; all
members of the National Semiconductor
of products. Together the Geode processor and CS5530
provide a system-level solution well suited for the high
performance needs of a host of devices such as digital
set-top boxes and thin client devices. Due to the low
power consumption of a GXLV processor, this solution
satisfies the needs of battery powered devices such as
National’s WebPAD™ system, a Geode GXLV proces-
sor/CS5530 based design. Also, thermal design is eased
allowing for fanless system design.
The CS5530 I/O companion is a PCI-to-ISA bridge (South
Bridge), ACPI-compliant chipset that provides AT/ISA
style functionality. To those familiar with PC architecture
this enables a quicker understanding of the CS5530’s
architecture. The device contains state-of-the-art power
management that enables systems, especially battery
powered systems, to significantly reduce power consump-
tion.
Geode™ CS5530 Internal Block Diagram
National Semiconductor and Virtual System Architecture are registered trademarks of National Semiconductor Corporation.
Geode, VSA, and WebPAD are trademarks of National Semiconductor Corporation.
For a complete listing of National Semiconductor trademarks, please visit www.national.com/trademarks.
Graphics Companion
and Video
from CPU
Graphics
Geode™ CS9210
Display
GPIOs
GPCS
USB
Joystick
MPEG, DOT Clock
Display Interface
RGB/FP Interface
PCI to USB Macro
Events, and Timers
CSC and SCL
Pwr Mgmt, Traps,
Joystick / Game Port
®
Geode™ family
AT Ports, ISA Megacells
PCI to X-Bus / X-Bus to PCI Bridge
ISA Bus Interface
PC97317 SIO
AT Compatibility Logic
ISA Bus
PCI Bus
Audio is supported through PCI bus master engines which
connect to an AC97 compatible codec such as the
National Semiconductor LM4548. If industry standard
audio is required, a combination of hardware and software
called Virtual System Architecture
provided.
The GXLV processor’s graphics/video output is connected
to the CS5530. The CS5530 graphics/video support
includes a PLL that generates the DOT clock for the GXLV
processor (where the graphics controller is located), video
acceleration hardware, gamma RAM plus three DACs for
RGB output to CRT, and digital RGB that can be directly
connected to TFT panels or NTSC/PAL encoders. The
digital RGB output can also be connected to the National
Semiconductor CS9210 Graphics Companion (a DSTN
Controller) for DSTN panel support. The CS9210 is also a
member of the Geode product family.
X-Bus
Ultra DMA/33
Interface
IDE
IDE
Audio/Codec/MPU
PCI Configuration
CS5530 Support
Address Mapper
(e.g., LM4548)
®
Active Decode
AC97 Codec
X-Bus Arbiter
(VSA™) technology is
Interface
Registers
www.national.com
April 2000

Related parts for CS5530

CS5530 Summary of contents

Page 1

... Geode™ CS5530 I/O Companion Multi-Function South Bridge General Description The CS5530 I/O companion is designed to work in con- junction with the GXLV and GXm series processors; all members of the National Semiconductor of products. Together the Geode processor and CS5530 provide a system-level solution well suited for the high performance needs of a host of devices such as digital set-top boxes and thin client devices ...

Page 2

... If additional functions are required, such as real-time clock, floppy disk, PS2 keyboard, and PS2 mouse, a SuperI/O (e.g., National PC97317) can be easily con- nected to the CS5530. Features General Features Designed for use with the GXLV and GXm Geode ...

Page 3

Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Table of Contents (Continued) 3.3 RESETS AND CLOCKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Table of Contents (Continued) 3.8 DISPLAY SUBSYSTEM EXTENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 6

... Joystick / Game Port www.national.com 1.1 PCI BUS INTERFACE The CS5530 provides a PCI bus interface that is both a slave for PCI cycles initiated by the CPU or other PCI master devices, and a non-preemptable master for DMA transfer cycles. The chip also is a standard PCI master for the IDE controllers and audio I/O logic ...

Page 7

... ISA BUS INTERFACE The CS5530 provides an ISA bus interface for unclaimed memory and I/O cycles on PCI. The CS5530 is the default subtractive decoding agent and forwards all unclaimed memory and I/O cycles to the ISA interface; however, the CS5530 may be configured to ignore either I/O, memory or all unclaimed cycles (subtractive decode disabled) ...

Page 8

... Any AC97 codec which supports an independent input and output sample rate conversion interface (e.g., National Semiconductor LM4548) can be used with the CS5530. This type of codec will allow for a design which meets the require- ments for PC97 and PC98-compliant audio as defined by Microsoft Corporation ...

Page 9

... Architecture Overview (Continued) 1.7 DISPLAY SUBSYSTEM EXTENSIONS The CS5530 incorporates extensions to the GXLV proces- sor’s display subsystem. These include: • Video Accelerator - Buffers and formats input YUV video data from processor - 8-bit interface to the GXLV processor - X & Y scaler with bilinear filter - Color space converter (YUV to RGB) • ...

Page 10

... Figure 1-4. CS5530 Clock Generation www.national.com 1.9 UNIVERSAL SERIAL BUS The CS5530 provides two complete, independent USB ports. Each port has a Data "–" and a Data "+" pin. The USB controller is a compliant Open Host Controller Interface (OpenHCI). The OpenHCI specification provides ...

Page 11

... PROCESSOR SUPPORT The traditional south bridge functionality included in the CS5530 I/O companion chip has been designed to sup- port the GXLV processor. When combined with the GXLV processor, the CS5530 provides a bridge which supports a standard ISA bus and system ROM. As part of the video ...

Page 12

... Signal Definitions This section defines the signals and describes the exter- nal interface of the Geode CS5530. Figure 2-1 shows the INTR SMI# IRQ13 PSERIAL CPU Interface SUSP# SUSPA# SUSP_3V HOLD_REQ# AD[31:0] C/BE[3:0]# INTA#-INTD# REQ# GNT# FRAME# IRDY# PCI Bus TRDY# STOP# LOCK# DEVSEL# ...

Page 13

... PIN ASSIGNMENTS The tables in this section use several common abbrevia- tions. Table 2-1 lists the mnemonics and their meanings. Figure 2-2 shows the pin assignment for the CS5530 with Tables 2-2 and 2-3 listing the pin assignments sorted by terminal number and alphabetically by signal name, respectively. ...

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... PIX18 VDRDY PIX22 VDAT6 VDAT2 INTD# AD3 AD5 PIX21 PIX23 VDAT3 VDAT7 VDAT1 PRST# INTC# AD2 VSS PIX20 VDD VDAT4 VSS VSS AD1 INTB# VSS Geode™ CS5530 I/O Companion Top View VSS VDD IOW# VSS VSS IRQ3 MCS16# VSS SA2 SA19 SA16 DRQ1 DRQ3 IRQ7 ...

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Signal Definitions (Continued) Table 2-2. 352 TBGA Pin Assignments - Sorted by Pin Number Signal Name Pin Limited ISA Master No. ISA Mode Mode A1 PIXEL0 A2 PIXEL1 A3 PIXEL2 A4 PIXEL7 A5 PIXEL10 A6 VID_CLK A7 PIXEL12 A8 PIXEL16 ...

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Signal Definitions (Continued) Table 2-2. 352 TBGA Pin Assignments - Sorted by Pin Number (Continued) Signal Name Pin Limited ISA Master No. ISA Mode Mode L2 FP_ENA_VDD No Function L3 FP_CLK_EVEN No Function L4 VDD L23 VDD L24 SUSP_3V L25 ...

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Signal Definitions (Continued) Table 2-2. 352 TBGA Pin Assignments - Sorted by Pin Number (Continued) Signal Name Pin Limited ISA Master No. ISA Mode Mode AE7 DACK5# AE8 AEN AE9 SA0/SD0 SD0 AE10 DRQ2 AE11 SA18 AE12 IOR# AE13 IRQ5 ...

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Signal Definitions (Continued) Table 2-3. 352 TBGA Pin Assignments - Sorted Alphabetically by Signal Name Signal Name Limited ISA ISA Master Pin Type Mode Mode (Note 1) AD0 I/O, t/s, 5VT AD1 I/O, t/s, 5VT AD2 I/O, t/s, 5VT AD3 ...

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Signal Definitions (Continued) Table 2-3. 352 TBGA Pin Assignments - Sorted Alphabetically by Signal Name (Continued) Signal Name Limited ISA ISA Master Pin Type Mode Mode (Note 1) GNT# I, 5VT GPCS# GPIO0 I/O, 5VT GPIO1/SDATA_IN2 I/O, 5VT GPIO2 I/O, ...

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Signal Definitions (Continued) Table 2-3. 352 TBGA Pin Assignments - Sorted Alphabetically by Signal Name (Continued) Signal Name Limited ISA ISA Master Pin Type Mode Mode (Note 1) PCLK PERR# I/O, t/s, 5VT PIXEL0 PIXEL1 PIXEL2 PIXEL3 PIXEL4 PIXEL5 PIXEL6 ...

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Signal Definitions (Continued) Table 2-3. 352 TBGA Pin Assignments - Sorted Alphabetically by Signal Name (Continued) Signal Name Limited ISA ISA Master Pin Type Mode Mode (Note 1) VID_DATA7 VID_RDY VID_VAL VREF I, Analog VSS VSS VSS VSS VSS VSS ...

Page 22

... This is only used if interfacing to a compatible digital NTSC/PAL encoder device. O DOT Clock DOT clock is generated by the CS5530 and typically connects to the pro- cessor to create the video pixel clock. The minimum frequency of DCLK is 10 MHz and the maximum is 200 MHz. O ISA Bus Clock ISACLK is derived from PCICLK and is typically programmed for approxi- mately 8 MHz ...

Page 23

... INTR should be asserted. I Power Management Serial Interface PSERIAL is the unidirectional serial data link between the GXLV proces- sor and the CS5530. An 8-bit serial data packet carries status on power management events within the CPU. Data is clocked synchronous to the PCICLK input clock. O ...

Page 24

... O PCI Bus Request 5VT The CS5530 asserts REQ# in response to a DMA request or ISA master request to gain ownership of the PCI bus. The REQ# and GNT# signals are used to arbitrate for the PCI bus. REQ# should connect to the REQ0# of the GXLV processor and function as the highest-priority PCI master ...

Page 25

... TRDY input that indicates a PCI slave has driven valid data on a read or a PCI slave is ready to accept data from the CS5530 on a write. TRDY output that indicates the CS5530 has placed valid data on AD[31:0] during a read or is ready to accept the data from a PCI master on a write ...

Page 26

... If a parity error was detected, PERR# is asserted by a PCI slave during a write data phase and by a PCI master during a read data phase. When the CS5530 is a PCI master, PERR output during read trans- fers and an input during write transfers. When the CS5530 is a PCI slave, PERR input during read transfers and an output during write trans- fers ...

Page 27

... ISA Master Mode: System Address Direction Controls the direction of the external 5.0V tolerant transceiver on bits [15:0] of the SA bus. When low, the SA bus is driven out. When high, the SA bus is driven into the CS5530 by the external transceiver. O Limited ISA Mode: Flat Panel Data Port Line 16 Refer to Section 2.2.11 “ ...

Page 28

... RTCALE. I/O System Bus High Enable PU The CS5530 or ISA master asserts SBHE# to indicate that SD[15:8] will 5VT be used to transfer a byte at an odd address. SBHE output during non-ISA master DMA operations driven as the inversion of AD0 during 8-bit DMA cycles forced low for all 16- bit DMA cycles ...

Page 29

... I/O Channel Ready OD IOCHRDY deasserted indicates that an ISA slave requires additional wait 5VT states. When the CS5530 is an ISA slave, IOCHRDY is an output indicating addi- tional wait states are required. I Zero Wait States 5VT ZEROWS# asserted indicates that an ISA 8- or 16-bit memory slave can shorten the current cycle ...

Page 30

Signal Definitions (Continued) 2.2.5 ISA Bus Interface (Continued) Pin Signal Name No. DRQ[7:5], Refer DRQ[3:0] to Table 2-3 DACK[7:5]#, Refer DACK[3:0]# to Table 2-3 TC AF15 2.2.6 ROM Interface Pin Signal Name No. KBROMCS# AE4 www.national.com Type Description I DMA ...

Page 31

... When in Ultra DMA/33 mode, these signals are redefined: Read Cycle — STROBE0 and STROBE1 Write Cycle — DMARDY0# and DMARDY1# I DMA Request Channels 0 and 1 5VT The DREQ is used to request a DMA transfer from the CS5530. The direction of the transfers are determined by the IDE_IOR/IOW signals. I 5VT O DMA Acknowledge Channels 0 and 1 The DACK# acknowledges the DREQ request to initiate DMA transfers ...

Page 32

Signal Definitions (Continued) 2.2.8 USB Interface Pin Signal Name No. POWER_EN V4 OVER_CUR# W3 D+_PORT1 Y2 D–_PORT1 Y1 D+_PORT2 AA2 D–_PORT2 AA1 2.2.9 Game Port and General Purpose I/O Interface Pin Signal Name No. GPORT_CS# AD21 GPCS# AF26 GPIO7/SA23 AF23 ...

Page 33

... This output transmits audio serial data to the codec. I Serial Data Input 5VT This input receives serial data from the codec. O Serial Bus Synchronization This bit is asserted to synchronize the transfer of data between the CS5530 and the AC97 codec O PC Beep Legacy PC/AT speaker output. 33 www.national.com ...

Page 34

Signal Definitions (Continued) 2.2.11 Display Interface Pin Signal Name No. Pixel Port PCLK A13 PIXEL[23:0] Refer to Table 2-3 ENA_DISP B1 Display CRT HSYNC C6 HSYNC_OUT N1 VSYNC B5 VSYNC_OUT N2 DDC_SCL M2 www.national.com Type Description I Pixel Clock This ...

Page 35

Signal Definitions (Continued) 2.2.11 Display Interface (Continued) Pin Signal Name No. DDC_SDA M4 IREF R3 (Video DAC) Analog VREF T1 (Video DAC) Analog EXTVREFIN T2 (Video DAC) Analog AVDD1 (DAC) U1 Analog AVDD2 (VREF) T3 AVDD3 (DAC) N4 AVSS1 (DAC) ...

Page 36

... CRT. -- ISA Master Mode: No Function In the ISA Master mode of operation, the CS5530 can not support TFT flat panels or TV controllers. O Limited ISA Mode: Flat Panel Horizontal Sync Output This is the horizontal sync for an attached active matrix TFT flat panel ...

Page 37

... This is the enable signal for the backlight power supply to an attached flat panel under control of the power sequence control logic. -- ISA Master Mode: No Function In the ISA Master mode of operation, the CS5530 can not support TFT flat panels or TV controllers. I Video Data Port This is the input data for a video (MPEG) or graphics overlay in its native form ...

Page 38

... VID_DATA input port. If the VID_RDY signal is also asserted, the data will advance. O Video Ready This signal indicates that the CS5530 is ready to receive the next piece of video data on the VID_DATA port. If the VID_VAL signal is also asserted, the data will advance. Type Description ...

Page 39

Signal Definitions (Continued) 2.2.13 Power, Ground, and Reserved Pin Signal Name No. VDD Refer to Table 2-3 (Total of 19) VSS Refer to Table 2-3 (Total of 39) NC Refer to Table 2-3 (Total of 17) 2.2.14 Internal Test and ...

Page 40

... Note that this Functional Description section of the data book describes many of the registers used for configura- tion of the CS5530; however, not all registers are reported in detail. Some tables in the following subsections show only the bits (not the entire register) associated with a specific function being discussed ...

Page 41

... Functional Description (Continued) 3.1 PROCESSOR INTERFACE The CS5530 interface to the GXLV processor consists of seven miscellaneous connections, the PCI bus interface signals, plus the display controller connections. Figure 3-1 shows the interface requirements. Note that the PC/AT legacy pins NMI, WM_RST, and A20M are all virtual func- tions executed in SMM (System Management Mode) by the BIOS ...

Page 42

... PIXEL[5:0] PIXEL[7:2]* Geode™ GXLV Processor Note: *Connect PIXEL[17:16] PIXEL[9:8], and PIXEL[1:0] on the CS5530 to ground. See Figure 3-3. Figure 3-2. Portable/Desktop Display Subsystem Configurations www.national.com The CS5530 also supports both portable and desktop configurations. Figure 3-2 shows the signal connections for both types of systems. ...

Page 43

... PIXEL13 PIXEL12 PIXEL11 PIXEL10 PIXEL9 PIXEL8 PIXEL7 PIXEL6 PIXEL5 PIXEL4 PIXEL3 PIXEL2 PIXEL1 PIXEL0 Figure 3-3. PIXEL Signal Connections 43 PIXEL23 PIXEL22 Geode™ CS5530 PIXEL21 I/O Companion PIXEL20 PIXEL19 PIXEL18 PIXEL17 PIXEL16 PIXEL15 PIXEL14 PIXEL13 PIXEL12 PIXEL11 PIXEL10 PIXEL9 PIXEL8 PIXEL7 PIXEL6 PIXEL5 ...

Page 44

... For more information on the Serial Packet Register refer- enced in Table 3-1, refer to the GXLV processor data book. www.national.com The CS5530 decodes the serial packet after each trans- mission and performs the power management tasks related to video retrace. Table 3-1. GXLV Processor Serial Packet ...

Page 45

... Wait Cycle Control (Read Only): This function is not supported in the CS5530 always disabled (always reads 0). 6 Parity Error: Allow the CS5530 to check for parity errors on PCI cycles for which target, and to assert PERR# when a parity error is detected Disable (Default Enable. 5 VGA Palette Snoop Enable (Read Only): This function is not supported in the CS5530 ...

Page 46

... Subtractive Decode: These bits determine the point at which the CS5530 accepts cycles that are not claimed by another device. The CS5530 defaults to taking subtractive decode cycles in the default cycle clock, but can be moved up to the Slow Decode cycle point if all other PCI devices decode in the fast or medium clocks. Disabling subtractive decode must be done with care, as all ISA and ROM cycles are decoded subtractively ...

Page 47

... Bit Description F0 Index 04h-05h 6 Parity Error: Allow the CS5530 to check for parity errors on PCI cycles for which target, and to assert PERR# when a parity error is detected Disable (Default Enable. F0 Index 06h-07h 15 Detected Parity Error: This bit is set whenever a parity error is detected. ...

Page 48

... F0 Index 43h 1 PCI Retry Cycles: When the CS5530 is a PCI target and the PCI buffer is not empty, allow PCI bus to retry cycles Disable Enable. This bit works in conjunction with PCI bus delayed transactions bit. F0 Index 42h[5] must = 1 for this bit to be valid. ...

Page 49

... If PCI clock = 25 MHz, use setting of 010 (divide by 3). If PCI clock = MHz, use a setting of 011 (divide by 4). 100 µs POR# CPU_RST PCI_RST# POR# minimum pulse width for CS5530 only (i.e., not a system specification) = 100 µs and 14 MHz must be running. Revision 4.1 At any state, Power-on/Resume/Reset, the 14.31818 MHz oscillator must be active for the resets to function. 3.3.2 ...

Page 50

... DCLK provides a video clock for the GXLV processor. For applications that do not use the GXLV processor’s video, this is an available clock for general purpose use. The system clock distribution for a CS5530/GXLV proces- sor based system is shown in Figure 3-6. Geode™ CS5530 ...

Page 51

Funcitonal Description (Continued) 3.3.3.1 DCLK Programming The PLL contains an input divider (ID), feedback divider (FD) and a post divider (PD). The programming of the dividers is through F4BAR+Memory Offset 24h (see Table 3-9). The maximum output frequency is 300 ...

Page 52

Functional Description (Continued) Bit Description F4BAR+Memory Offset 24h-27h 31 Reset: Reset the PLL Normal operation Reset 30 Half Clock Enable Disable. For odd post divisors, half clock enables the falling edge of ...

Page 53

Funcitonal Description (Continued) Table 3-10. F4BAR+Memory Offset 24h[22:12] Decode (Value of “N”) Reg. Reg. N Value N Value N 400 33A 350 11 300 399 674 349 23 299 398 4E8 348 47 298 397 1D0 347 8F 297 396 ...

Page 54

... Idle calls. • APM does not help with Suspend determination or peripheral power management. The CS5530 provides two entry points for APM support: • Software CPU Suspend control via the CPU Suspend Command Register (F0 Index AEh) • Software SMI entry via the Software SMI Register (F0 Index D0h) ...

Page 55

... IRQ pins that can be used as a Resume event. If GPIO2, GPIO1, and GPIO0 are enabled as an external SMI source (F0 Index 92h[2:0]), they too can be used as a Resume event. No other CS5530 pins can be used to wake-up the system from Suspend when the clocks are stopped. As long as the 32 KHz clock remains active, internal SMI events are also Resume events ...

Page 56

Functional Description (Continued) Configuring Suspend Modulation Control of the Suspend Modulation feature is accom- plished using the Suspend Modulation OFF Count Regis- ter, the Suspend Modulation ON Count Register, and the Suspend Configuration Register (F0 Index 94h, 95h, and 96h, ...

Page 57

... IRQ Speedup Timer Count Register (F0 Index 8Ch have the SMI disable Suspend Modulation until the SMI handler reads the SMI Speedup Disable Register (F1BAR+Memory Offset 08h). The latter is the preferred method. The IRQ speedup method is provided for software compatibility with earlier revisions of the CS5530. This bit has no effect if the Suspend Modulation feature is disabled (bit 0 = 0). ...

Page 58

... CPU Clock Stop Normal SUSP#/ SUSPA# handshake Full system Suspend. Notes: This register configures the CS5530 to support a 3 Volt Suspend. Setting bit 0 causes the SUSP_3V pin to assert after the appropriate conditions, stopping the system clocks. A delay programmable (bits 7:4) to allow for a delay for the clock chip and CPU PLL to stabilize when an event Resumes the system ...

Page 59

... It is provided here to assist in a Save-to-Disk operation. Revision 4.1 The PC/AT compatible floppy port is not part of the CS5530. However expected that one will be attached on the ISA bus in a SuperI some other means. Some of the FDC registers are shadowed because they cannot be safely read ...

Page 60

... Functional Description (Continued) 3.4.3 Peripheral Power Management The CS5530 provides peripheral power management using a combination of device idle timers, address traps, and general purpose I/O pins. Idle timers are used in con- junction with traps to support powering down peripheral devices. Eight programmable GPIO (general purpose I/O) pins are included for external device power control as well as other functions ...

Page 61

Functional Description (Continued) Table 3-17. Keyboard/Mouse Idle Timer and Trap Related Registers Bit Description F0 Index 81h 3 Keyboard/Mouse Idle Timer Enable: Turn on Keyboard/Mouse Idle Timer Count Register (F0 Index 9Eh) and generate an SMI when the timer expires: ...

Page 62

Functional Description (Continued) Table 3-18. Parallel/Serial Idle Timer and Trap Related Registers Bit Description F0 Index 81h 2 Parallel/Serial Idle Timer Enable: Turn on Parallel/Serial Port Idle Timer Count Register (F0 Index 9Ch) and generate an SMI when the timer ...

Page 63

Functional Description (Continued) Table 3-19. Floppy Disk Idle Timer and Trap Related Registers Bit Description F0 Index 81h 1 Floppy Disk Idle Timer Enable: Turn on Floppy Disk Idle Timer Count Register (F0 Index 9Ah) and generate an SMI when ...

Page 64

Functional Description (Continued) Table 3-20. Primary Hard Disk Idle Timer and Trap Related Registers Bit Description F0 Index 81h 0 Primary Hard Disk Idle Timer Enable: Turn on Primary Hard Disk Idle Timer Count Register (F0 Index 98h) and gener- ...

Page 65

Functional Description (Continued) Table 3-21. Secondary Hard Disk Idle Timer and Trap Related Registers Bit Description F0 Index 83h 7 Secondary Hard Disk Idle Timer Enable: Turn on Secondary Hard Disk Idle Timer Count Register (F0 Index ACh) and generate ...

Page 66

Functional Description (Continued) Table 3-22. User Defined Device 1 (UDEF1) Idle Timer and Trap Related Registers Bit Description F0 Index 81h 4 User Defined Device 1 (UDEF1) Idle Timer Enable: Turn on UDEF1 Idle Timer Count Register (F0 Index A0h) ...

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Functional Description (Continued) Table 3-23. User Defined Device 2 (UDEF2) Idle Timer and Trap Related Registers Bit Description F0 Index 81h 5 User Defined Device 2 (UDEF2) Idle Timer Enable: Turn on UDEF2 Idle Timer Count Register (F0 Index A2h) ...

Page 68

Functional Description (Continued) Table 3-24. User Defined Device 3 (UDEF3) Idle Timer and Trap Related Registers Bit Description F0 Index 81h 6 User Defined Device 3 (UDEF3) Idle Timer Enable: Turn on UDEF3 Idle Timer Count Register (F0 Index A4h) ...

Page 69

... In a GXLV processor based system the graphics controller is embedded in the CPU, so video activity is communicated to the CS5530 via the serial connection (PSERIAL register, bit 0) from the processor. The CS5530 also detects accesses to standard VGA space on PCI (3Bxh, 3h, 3Dxh and A000h-B7FFh) in the event an external VGA controller is being used. ...

Page 70

... Functional Description (Continued) 3.4.3.2 General Purpose Timers The CS5530 contains two general purpose idle timers, General Purpose Timer 1 (F0 Index 88h) and General Purpose Timer 2 (F0 Index 8Ah). These two timers are similar to the Device Idle Timers in that they count down to zero unless re-triggered, and generate an SMI when they reach zero ...

Page 71

Functional Description (Continued) Table 3-27. General Purpose Timers and Control Registers (Continued) Bit Description F0 Index 8Ah 7:0 General Purpose Timer 2 Count: This field represents the load value for GP Timer 2. This value can represent either an 8-bit ...

Page 72

... ACPI Timer SMI enable bit. V-ACPI I/O Register Space The register space designated as V-ACPI (Virtualized ACPI) I/O does not physically exist in the CS5530. ACPI is supported in the CS5530 by virtualizing this register space. In order for ACPI to be supported, the V-ACPI module must be included in the BIOS. The register descriptions that follow, are supplied here for reference only ...

Page 73

... Functional Description (Continued) 3.4.3.4 General Purpose I/O Pins The CS5530 provides up to eight GPIO (general purpose I/O) pins. Five of the pins (GPIO[7:4] and GPIO1) have alternate functions. Table 3-30 shows the bits used for GPIO pin function selection. Each GPIO pin can be configured as an input or output. ...

Page 74

Functional Description (Continued) Table 3-31. GPIO Pin Configuration/Control Registers (Continued) Bit Description F0 Index 92h 7 GPIO7 Edge Sense for Reload of General Purpose Timer 2: Selects which edge transition of GPIO7 causes GP Timer 2 to reload ...

Page 75

... SMI status registers. For information regarding the location of the corresponding mirror register, refer to the note in the footer of the register description. Keep in mind, all SMI sources in the CS5530 are reported into the Top Level SMI Status Registers (F1BAR+Memory Offset 00h/02h); however, this discussion is regarding power management SMIs. For details regarding audio SMI events/reporting, refer to Section 3.7.2.2 “ ...

Page 76

... Functional Description (Continued) SMI# Asserted If Bit Geode™ (External SMI) GXLV Processor Geode™ CS5530 F1BAR+Memory Offset 02h Read to Clear to determine top-level source of SMI Bits [15:10] Other_SMI Bit 9 GTMR_TRP_SMI Bits [8:0] Other_SMI Top Level Figure 3-7. General Purpose Timer and UDEF Trap SMI Tree Example www ...

Page 77

Functional Description (Continued) Table 3-32. Top Level SMI Status Register (Read to Clear) Bit Description F1BAR+Memory Offset 02h-03h 15 Suspend Modulation Enable Mirror (Read to Clear): This bit mirrors the Suspend Modulation Feature Enable bit (F0 Index 96h[0]). It is ...

Page 78

Functional Description (Continued) Table 3-33. Second Level Pwr Mgmnt SMI Status Reporting Registers (Read to Clear) Bit Description F1BAR+Memory Offset 06h-07h 15:6 Reserved (Read to Clear) 5 PCI Function Trap (Read to Clear): SMI was caused by a trapped configuration ...

Page 79

Functional Description (Continued) Table 3-33. Second Level Pwr Mgmnt SMI Status Reporting Registers (Read to Clear) (Continued) Bit Description F0 Index F4h Second Level Power Management Status Register 1 (RC) 7:5 Reserved 4 Game Port SMI Status (Read to Clear): ...

Page 80

Functional Description (Continued) Table 3-33. Second Level Pwr Mgmnt SMI Status Reporting Registers (Read to Clear) (Continued) Bit Description F0 Index F5h Second Level Power Management Status Register 2 (RC) 7 Video Idle Timer SMI Status (Read to Clear): SMI ...

Page 81

Functional Description (Continued) Table 3-33. Second Level Pwr Mgmnt SMI Status Reporting Registers (Read to Clear) (Continued) Bit Description F0 Index F6h Second Level Power Management Status Register 3 (RC) 7 Video Access Trap SMI Status (Read to Clear): SMI ...

Page 82

Functional Description (Continued) Table 3-33. Second Level Pwr Mgmnt SMI Status Reporting Registers (Read to Clear) (Continued) Bit Description F0 Index F7h Second Level Power Management Status Register 4 (RO/RC) 7 GPIO2 SMI Status (Read to Clear): SMI was caused ...

Page 83

Functional Description (Continued) Table 3-34. Device Power Management Programming Summary Device Power Management Resource Global Timer Enable 80h[1] Keyboard / Mouse Idle Timer 81h[3] Parallel / Serial Idle Timer 81h[2] Floppy Disk Idle Timer 81h[1] Video Idle Timer (Note 1) ...

Page 84

... Subtractive Decode: These bits determine the point at which the CS5530 accepts cycles that are not claimed by another device. The CS5530 defaults to taking subtractive decode cycles in the default cycle clock, but can be moved up to the Slow Decode cycle point if all other PCI devices decode in the fast or medium clocks. Disabling subtractive decode must be done with care, as all ISA and ROM cycles are decoded subtractively ...

Page 85

Functional Description (Continued) 3.5.2 ISA Bus Interface The ISA bus controller issues multiple ISA cycles to sat- isfy PCI transactions that are larger than 16 bits. A full 32- bit read or write results in two 16-bit ISA transactions or ...

Page 86

Functional Description (Continued) 3.5.2.1 Delayed PCI Transactions If PCI delayed transactions are enabled (F0 Index 42h[ multiple PCI cycles occur for every slower ISA cycle. Figure 3-9 shows the relationship of PCI cycles to an ISA cycle with ...

Page 87

... ISA mode selected. Writing to this bit is not recom- mended due to the actual strapping done on the board. ISA memory and ISA refresh cycles are not supported by the CS5530. Although, the refresh toggle bit in I/O Port 061h still exists for software compatibility reasons. Revision 4.1 Table 3-36 ...

Page 88

... SA[19:16] FP_DATA[15:0]/SA[15:0] FP_DATA16/SA_OE# SA_LATCH/SA_DIR Geode™ CS5530 SA[15:0]_SD[15:0]/SD[15:0] Notes: 1. When strapped for ISA Master mode, GPIO[7:4]/SA[23:20] are set to SA[23:20] and the settings in F0 Index 43h[2] are invalid. 2. These signals are: MEMW#, MEMR#, IOR#, IOW#, TC, AEN, DREQ[7:5, 3:0], DACK[7:5, 3:0]#, MEMCS16#, ZEROWS#, SBHE#, IOCS16#, IOCHRDY, ISACLK. ...

Page 89

... I/O data bus. Either the PCI bus master or the DMA controllers can become the bus owner. When the PCI bus master is the bus owner, the CS5530 data steering logic provides data conversion necessary for 8/16/32-bit transfers to and from 8/16-bit devices on either the ISA bus or the 8-bit registers on the on-chip I/O data bus ...

Page 90

... DMA cycle. Figures 3-12 and 3-13 are examples of DMA memory read and memory write cycles. Upon detection of the DMA controller’s MEMR# or MEMW# active, the CS5530 starts the PCI cycle, asserts FRAME#, and negates an internal IOCHRDY. This assures the DMA cycle does not complete before the PCI cycle has provided or accepted the data ...

Page 91

... The CS5530 positively decodes memory addresses 000F0000h-000FFFFFh (64 KB) FFFFFFFFh (256 KB) at reset. These memory cycles cause the CS5530 to claim the cycle, and generate an ISA bus memory cycle with KBROMCS# asserted. The CS5530 can also be configured to respond to memory addresses FF000000h-FFFFFFFFh 000E0000h-000FFFFFh (128 KB). ...

Page 92

... In this mode, the DMA controller continues to execute transfer cycles until the I/O device drops DRQ to indicate its inability to continue providing data. For this case, the PCI bus is held by the CS5530 until a break in the transfers occurs. In cascade mode, the channel is connected to another DMA controller ISA bus master, rather than to an I/O device ...

Page 93

... DRQ signal active high and the DACK# signal active low. DMA Shadow Registers The CS5530 contains a shadow register located at F0 Index B8h (Table 3-39) for reading the configuration of the DMA controllers. This read-only register can sequence to read through all of the DMA registers ...

Page 94

... IOW# IOR# www.national.com 3.5.4.2 Programmable Interval Timer The CS5530 contains an 8254-equivalent Programmable Interval Timer (PIT) configured as shown in Figure 3-14. The PIT has three timers/counters, each with an input fre- quency of 1.19318 MHz (OSC divided by 12), and individ- ually programmable to different modes. The gates of Counter 0 and 1 are usually enabled, how- ever, they can be controlled via F0 Index 50h (see Table 3- 40) ...

Page 95

... Suspend to save/restore the PIT state by reading the PITs counter and write-only registers. The read sequence for the shadow register is listed in F0 Index BAh, Table 3-41. 3.5.4.3 Programmable Interrupt Controller The CS5530 includes an AT-compatible Programmable Interrupt Controller (PIC) configuration with two 8259- equivalent interrupt controllers in a master/slave configu- ration (Figure 3-15). Bit ...

Page 96

... Table 3-43. PCI INTA Cycle Disable/Enable Bit Bit Description F0 Index 40h 7 PCI Interrupt Acknowledge Cycle Response: The CS5530 responds to PCI interrupt acknowledge cycles Disable Enable. www.national.com rupt acknowledge (INTA) cycles from the CPU. On the first INTA cycle the cascading priority is resolved to determine which of the two 8259 controllers output the interrupt vec- tor onto the data bus ...

Page 97

Functional Description (Continued) PIC Shadow Register The PIC registers are shadowed to allow for Zero Volt Suspend to save/restore the PIC state by reading the PICs write-only registers. A write to this register resets the Bit Description F0 Index B9h ...

Page 98

... Functional Description (Continued) 3.5.4.4 PCI Compatible Interrupts The CS5530 allows the PCI interrupt signals INTA#, INTB#, INTC#, and INTD# (also known in industry terms as PIRQx mapped internally to any IRQ signal with the PCI Interrupt Steering Registers 1 and 2, F0 Index 5Ch and 5Dh (Table 3-45). ...

Page 99

Functional Description (Continued) Table 3-46. Interrupt Edge/Level Select Registers Bit Description I/O Port 4D0h 7 IRQ7 Edge or Level Select: Selects PIC IRQ7 sensitivity configuration Edge Level. (Notes 1 and 2) 6 IRQ6 Edge or Level ...

Page 100

... This bit can only be set if ERR_EN is set 0. This bit is set 0 after a write to ERR_EN with after reset. 6 IOCHK# Status (Read Only I/O device reporting an error to the CS5530 No Yes. This bit can only be set if IOCHK_EN is set 0. This bit is set 0 after a write to IOCHK_EN with after reset. ...

Page 101

... The assertion of a fast keyboard reset (WM_RST SMI) is controlled by bit 0 in I/O Port 092h or by monitoring for the keyboard command sequence. If bit 0 is changed from the CS5530 generates a reset to the processor by generating a WM_RST SMI. When the WM_RST SMI Table 3-48. I/O Port 092h Decode Enable Bit ...

Page 102

... Keyboard Controller Positive Decode: Selects positive or subtractive decoding for accesses to I/O Port 060h and 064h (and 062h/066h if enabled Subtractive Positive. Note: Positive decoding by the CS5530 speeds up the I/O cycle time. These I/O Ports do not exist in the CS5530 assumed that if positive decode is enabled, the port exists on the ISA bus. ...

Page 103

... The fast keyboard A20M# and CPU reset can be disabled through F0 Index 52h[7]. By default, bit 7 is cleared, and the fast keyboard A20M# and CPU reset monitor logic is active. If bit 7 is clear, the CS5530 forwards the com- mands to the keyboard controller. By default, the CS5530 forces the deassertion of A20M# during a warm reset ...

Page 104

... RTC Register Index: A write of this register sends the data out on the ISA bus and also causes RTCALE to be triggered. Note: This register is shadowed within the CS5530 and is read through the RTC Shadow Register (F0 Index BBh). I/O Port 071h A read of this register returns the value of the register indexed by the RTC Address Register plus initiates a RTCCS#. ...

Page 105

... The CS5530 also provides a software-accessible buffered reset signal to the IDE drive, F0 Index 44h[3:2] (Table 3- 53). The IDE_RST# signal is driven low during reset to the CS5530 and can be driven low or high as needed for device-power-off conditions. 3.6.1 IDE Interface Signals The CS5530 has two completely separate IDE control sig- nals, however, the IDE_RST#, IDE_ADDR[2:0] and IDE_DATA[15:0] are shared ...

Page 106

... Function 2. F2BAR sets the base address for the IDE Controllers Configuration Registers as shown in Table 3-54. For complete bit information, refer to Section 4.3.3 “IDE Controller Registers - Function 2” on page 184. The following subsections discuss CS5530 opera- tional/programming details concerning PIO, Bus Master, and Ultra DMA/33 modes. 3.6.2.1 ...

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Functional Description (Continued) Bit Description F2BAR+I/O Offset 20h-23h If Offset 24h[31 Format 0: Selects slowest PIOMODE per channel for commands. Format 0 settings for: PIO Mode 0 = 00009172h PIO Mode 1 = 00012171h PIO Mode 2 = ...

Page 108

... Bus Master Mode Two IDE bus masters are provided to perform the data transfers for the primary and secondary channels. The CS5530 off-loads the CPU and improves system perfor- mance in multitasking environments. The bus master mode programming interface is an exten- sion of the standard IDE programming model. This means ...

Page 109

Functional Description (Continued) Table 3-57. IDE Bus Master Command and Status Registers Bit Description F2BAR+I/O Offset 00h IDE Bus Master 0 Command Register — Primary (R/W) 7:4 Reserved: Set to 0. Must return 0 on reads. 3 Read or Write ...

Page 110

Functional Description (Continued) Physical Region Descriptor Format Each physical memory region to be transferred is described by a Physical Region Descriptor (PRD) as illus- trated in Table 3-58. When the bus master is enabled (Command Register bit 0 = 1), ...

Page 111

... IDE_DREQ and the CS5530 acknowledges by STOP asserting STOP. The transmitter then drives the STROBE STROBE signal to a high level. The CS5530 then puts the result of DMARDY# the CRC calculation onto the IDE_DATA[15:0] while deas- serting IDE_DACK#. The IDE device latches the CRC value on the rising edge of IDE_DACK# ...

Page 112

Functional Description (Continued) Table 3-60. MDMA/UDMA Control Registers Bit Description F2BAR+I/O Offset 24h-27h If bit Multiword DMA Settings for: Multiword DMA Mode 0 = 00077771h Multiword DMA Mode 1 = 00012121h Multiword DMA Mode 2 = 00002020h ...

Page 113

... The CS5530 audio hardware includes six PCI bus mas- ters (three for input and three for output) for transferring digitized audio between memory and the external codec. With these bus master engines, the CS5530 off-loads the CPU and improves system performance. The programming interface defines a simple scat- ter/gather mechanism allowing large transfer blocks to be scattered to or gathered from memory ...

Page 114

Functional Description (Continued) The six bus masters that directly drive specific slots on the AC97 interface: • Audio Bus Master 0 - Output to codec - PCI read - 32-Bit - Left and right channels - Slots 3 and 4 ...

Page 115

Functional Description (Continued) For example, Audio Bus Master 0 is defined as an output only, so bit 3 of Audio Bus Master 0 Command Register (F3BAR+Memory Offset 20h[3]) must always be set to 1. Table 3-63. Audio Bus Master Configuration ...

Page 116

Functional Description (Continued) 3.7.1.2 Physical Region Descriptor Table Address Before the bus master starts a master transfer it must be programmed with a pointer (PRD Table Address Register Physical Region Descriptor Table. This pointer sets the starting memory ...

Page 117

Functional Description (Continued) 3.7.1.4 Programming Model The following discussion explains, in steps, how to initiate and maintain a bus master transfer between memory and an audio slave device. In the steps listed below, the reference to “Example” refers to Figure ...

Page 118

... The CS5530 provides an AC97 Specification Revision 1.3, 2.0, and 2.1 compatible interface. Any AC97 codec which supports sample rate conversion (SRC) can be used with the CS5530. This type of codec allows for a design which meets the requirements for PC97 and PC98-compliant audio as defined by Microsoft Corpora- tion ...

Page 119

... Codec Command Address: Address of the codec control register for which the command is being sent. This address goes in slot 1 bits [19:12] on SDATA_OUT. 23:22 CS5530 Codec Communication: Selects which codec to communicate with Primary codec 01 = Secondary codec Note: 00 and 01 are the only valid settings for these bits. ...

Page 120

... Fast Path Write - If enabled, the CS5530 captures cer- tain writes to several I/O locations. This feature prevents two SMIs from being asserted for write operations that are known to take two accesses (the first access is an index and the second is data) ...

Page 121

... AUDIO_SMI Bit 0 Other_SMI Top Level Revision 4.1 In Fast Path Write, the CS5530 responds to writes to the following addresses: 388h, 38Ah and 38B 2x0h, 2x2h, and 2x8h Table 3-66 and Table 3-67 show the bit formats of the sec- ond and third level SMI status reporting registers, respec- tively ...

Page 122

Functional Description (Continued) Table 3-66. Second Level SMI Status Reporting Registers Bit Description F3BAR+Memory Offset 10h-11h 15:8 Reserved: Set Audio Bus Master 5 SMI Status (Read to Clear): SMI was caused by an event occurring on Audio ...

Page 123

Functional Description (Continued) Table 3-66. Second Level SMI Status Reporting Registers (Continued) Bit Description F3BAR+Memory Offset 12h-13h 15:8 Reserved: Set Audio Bus Master 5 SMI Status (Read Only): SMI was caused by an event occurring on Audio ...

Page 124

Functional Description (Continued) Table 3-67. Third Level SMI Status Reporting Registers Bit Description F3BAR+Memory Offset 14h-17h 31:24 Fast Path Write Even Access Data (Read Only): These bits contain the data from the last Fast Path Write Even access. These bits ...

Page 125

... Fast Path Read Enable/SMI Disable: Read Fast Path (an SMI is not generated on reads from specified addresses Disable Enable. In Fast Path Read the CS5530 responds to reads of the following addresses: 388h-38Bh; 2x0h, 2x1, 2x2h, 2x3, 2x8 and 2x9h. Note that if neither sound card nor FM I/O mapping is enabled, then status read trapping is not possible. ...

Page 126

... Functional Description (Continued) 3.7.2.3 IRQ Configuration Registers The CS5530 provides the ability to set and clear IRQs internally through software control. If the IRQs are config- ured for software control, they will not respond to external hardware. There are three registers provided for this fea- ture: • ...

Page 127

Functional Description (Continued) Table 3-69. IRQ Configuration Registers (Continued) Bit Description F3BAR+Memory Offset 1Eh-1Fh 15 Mask Internal IRQ15 Disable Enable. 14 Mask Internal IRQ14 Disable Enable. 13 Reserved: Set ...

Page 128

... Functional Description (Continued) 3.8 DISPLAY SUBSYSTEM EXTENSIONS The CS5530 incorporates extensions to the GXLV proces- sor’s display subsystem. These include: • Video Accelerator - Buffers and formats input YUV video data from GXLV processor - Supports 8-bit interface to GXLV processor - X & Y scaler with bilinear filter - Color space converter (YUV to RGB) • ...

Page 129

... When both VID_VAL and advances. The VID_RDY signal is driven by the CS5530 one clock early to the processor while the VID_VAL signal is driven by the processor coincident with valid data on VID_DATA. A sample timing diagram is shown in Figure 3-24. 8 CLKs 8 CLKs Figure 3-24 ...

Page 130

Functional Description (Continued) 3.8.2.3 Video Format The video input data can be in interleaved YUV 4:2:2 or RGB 5:6:5 format. The sequence of the individual YUV components is selectable to one of four formats via bits Bit Description F4BAR+Memory Offset ...

Page 131

... Functional Description (Continued) 3.8.2.4 X and Y Scaler / Filter The CS5530 supports horizontal and vertical scaling of the video stream up to eight times the source resolution. The scaler uses a Digital-Differential-Analyzer (DDA) based upon the values programmed in the Video Scale Register (F4BAR+Memory Offset 10h, see Table 3-72) ...

Page 132

... Tables 3-73 and 3-74 show the bit formats for these regis- ters The CS5530 accepts graphics data over the PIXEL[23:0] interface from the GXLV processor at the screen DOT clock rate. The CS5530 is capable of displaying graphics resolutions up to 1600x1200 at color depths bits per pixel (bpp) while simultaneously overlaying a video window. ...

Page 133

Functional Description (Continued) 3.8.4 Gamma RAM Either the graphics or video stream may be routed through an on-chip gamma RAM (3x256x8-bit) which can be used for gamma-correction of either data stream, or contrast/brightness adjustments in the case of video data. ...

Page 134

... In addition, the CS5530 incorporates power sequencing logic to simplify the design of a portable system. The flat panel port of the CS5530 may optionally drive the CS9210 DSTN Controller device for color dual-scan dis- play (DSTN) support. If flat panel support is not required, ...

Page 135

... PCI configuration registers or to its internal PCI memory mapped I/O registers. The USB core is implemented as a unique PCI device in the CS5530. It has its own PCI Header and Configuration space and is mapped through PCI Configuration Mecha- nism #1 as: Bus #0, Device #0 (AD28 = 1 or AD26 = 1), Function #0 (referred to as PCIUSB) ...

Page 136

Functional Description (Continued) 3.9.2 USB Host Controller In the USB core is the operational control block responsible for the host controllers operational states (Suspend, Disable, Enable), special USB signals (Reset, Resume), status, interrupt control, and host controller configuration. ...

Page 137

... Register Descriptions The Geode CS5530 is a multi-function device. Its register space can be broadly divided into four categories in which specific types of registers are located: 1) Chipset Register Space (F0-F4) 2) USB Controller Register Space (PCIUSB) 3) ISA Legacy I/O Register Space (I/O Port) 4) V-ACPI I/O Register Space (I/O Port) The Chipset and the USB Controller Register Spaces are accessed through the PCI interface using the PCI Type One Configuration Mechanism ...

Page 138

... The second location (0CFCh) references the Configura- tion Data Register. To access PCI configuration space, write the Configura- tion Address (0CF8h) Register with data that specifies the CS5530 as the device on PCI being accessed, along with the configuration register offset. On the following cycle, a Table 4-1. PCI Configuration Address Register (0CF8h) 31 ...

Page 139

... Register Descriptions (Continued) 4.2 REGISTER SUMMARY The tables in this subsection summarize all the registers of the CS5530. Included in the tables are the register’s Table 4-2. Function 0: PCI Header and Bridge Configuration Registers Summary Width F0 Index (Bits) Type 00h-01h 16 RO 02h-03h 16 RO 04h-05h 16 R/W 06h-07h ...

Page 140

Register Descriptions (Continued) Table 4-2. Function 0: PCI Header and Bridge Configuration Registers Summary (Continued) Width F0 Index (Bits) Type 8Eh 8 R/W 8Fh -- -- 90h 8 R/W 91h 8 R/W 92h 8 R/W 93h 8 R/W 94h 8 ...

Page 141

Register Descriptions (Continued) Table 4-2. Function 0: PCI Header and Bridge Configuration Registers Summary (Continued) Width F0 Index (Bits) Type F7h 8 RO/RC F8h-FFh -- -- Table 4-3. Function 1: PCI Header Registers for SMI Status and ACPI Timer Summary ...

Page 142

Register Descriptions (Continued) Table 4-5. Function 2: PCI Header Registers for IDE Controller Summary Width F2 Index (Bits) Type 00h-01h 16 RO 02h-03h 16 RO 04h-05h 16 R/W 06h-07h 16 RO 08h 8 RO 09h-0Bh 24 RO 0Ch 8 RO ...

Page 143

Register Descriptions (Continued) Table 4-7. Function 3: PCI Header Registers for XpressAUDIO Subsystem Summary Width F3 Index (Bits) Type 00h-01h 16 RO 02h-03h 16 RO 04h-05h 16 R/W 06h-07h 16 RO 08h 8 RO 09h-0Bh 24 RO 0Ch 8 RO ...

Page 144

Register Descriptions (Continued) Table 4-8. F3BAR: XpressAUDIO Subsystem Configuration Registers Summary (Continued) F3BAR+ Memory Width Offset (Bits) Type 40h 8 R/W 41h 8 RC 42h-43h -- -- 44h-47h 32 R/W 48h 8 R/W 49h 8 RC 4Ah-4Bh -- -- 4Ch-4Fh ...

Page 145

Register Descriptions (Continued) Table 4-11. PCIUSB 00h-FFh Register Summary PCIUSB Width Index (Bits) Type 00h-01h 16 RO 02h-03h 16 RO 04h-05h 16 R/W 06h-07h 16 R/W 08h 8 RO 09h-0Bh 24 RO 0Ch 8 R/W 0Dh 8 R/W 0Eh 8 ...

Page 146

Register Descriptions (Continued) Table 4-12. ISA Legacy I/O Register Summary I/O Port Type Name DMA Channel Control Registers (Table 4-25) 000h R/W DMA Channel 0 Address Register 001h R/W DMA Channel 0 Transfer Count Register 002h R/W DMA Channel 1 ...

Page 147

Register Descriptions (Continued) Table 4-12. ISA Legacy I/O Register Summary (Continued) I/O Port Type Name 489h R/W DMA Channel 6 High Page Register 48Ah R/W DMA Channel 7 High Page Register 48Bh R/W DMA Channel 5 High Page Register Programmable ...

Page 148

Register Descriptions (Continued) Table 4-13. V-ACPI I/O Register Space Summary ACPI_ BASE Type Align Length 00h-03h R 04h 05h -- 1 1 06h R 07h -- 1 1 08h-09h R 0Ah-0Bh ...

Page 149

... Wait Cycle Control (Read Only): This function is not supported in the CS5530 always disabled (always reads 0). 6 Parity Error: Allow the CS5530 to check for parity errors on PCI cycles for which target, and to assert PERR# when a parity error is detected Disable (Default Enable. 5 VGA Palette Snoop Enable (Read Only): This function is not supported in the CS5530 ...

Page 150

... DEVSEL# timing Fast Medium Slow Reserved 8 Data Parity Detected: This bit is set when: 1) The CS5530 asserted PERR# or observed PERR# asserted. 2) The CS5530 is the master for the cycle in which a parity error occurred and the Parity Error bit is set (F0 Index 04h[6] = 1). Write 1 to clear. 7 Fast Back-to-Back Capable target, the CS5530 is capable of accepting fast back-to-back transactions Disable ...

Page 151

... Subtractive Decode: These bits determine the point at which the CS5530 accepts cycles that are not claimed by another device. The CS5530 defaults to taking subtractive decode cycles in the default cycle clock, but can be moved up to the Slow Decode cycle point if all other PCI devices decode in the fast or medium clocks. Disabling subtractive decode must be done with care, as all ISA and ROM cycles are decoded subtractively ...

Page 152

... If F0 Index 43h bit 6 or bit 2 is set to 1, then pin AD22 = SA20. 1 PCI Retry Cycles: When the CS5530 is a PCI target and the PCI buffer is not empty, allow PCI bus to retry cycles Disable Enable. This bit works in conjunction with PCI bus delayed transactions bit. F0 Index 42h[5] must = 1 for this bit to be valid. ...

Page 153

Register Descriptions (Continued) Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description Index 45h-4Fh Index 50h 7 PIT Software Reset Disable Enable. 6 PIT Counter Forces Counter 1 ...

Page 154

... Real Time Clock Positive Decode: Selects PCI positive or subtractive decoding for accesses to I/O Port 070h and 071h Subtractive Positive. Note: Positive decoding by the CS5530 speeds up the I/O cycle time. These I/O Ports do not exist in the CS5530 assumed that if positive decode is enabled, the port exists on the ISA bus. ...

Page 155

... LPT1 Positive Decode: Selects PCI positive or subtractive decoding for accesses to I/O Port 378h-37Fh and 778h-77Ah Subtractive Positive. Note: Positive decoding by the CS5530 speeds up the I/O cycle time. The keyboard, LPT3, LPT2, and LPT1 I/O Ports do not exist in the CS5530 assumed that if positive decode is enabled, the port exists on the ISA bus. ...

Page 156

Register Descriptions (Continued) Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description Index 5Eh-6Fh Index 70h-71h General Purpose Chip Select Base Address Register (R/W) 15:0 General Purpose Chip Select I/O Base Address: This 16-bit value ...

Page 157

Register Descriptions (Continued) Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description Index 81h 7 Video Access Idle Timer Enable: Turn on Video Idle Timer Count Register (F0 Index A6h) and generate an SMI when ...

Page 158

Register Descriptions (Continued) Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description Index 82h 7 Video Access Trap Disable Enable. If this bit is enabled and an access occurs in the ...

Page 159

Register Descriptions (Continued) Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description Index 83h 7 Secondary Hard Disk Idle Timer Enable: Turn on Secondary Hard Disk Idle Timer Count Register (F0 Index ACh) and generate ...

Page 160

Register Descriptions (Continued) Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description Index 84h Second Level Power Management Status Mirror Register 1 (RO) 7:5 Reserved 4 Game Port SMI Status (Read Only): SMI was caused ...

Page 161

Register Descriptions (Continued) Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description Index 85h Second Level Power Management Status Mirror Register 2 (RO) 7 Video Idle Timer SMI Status (Read Only): SMI was caused by ...

Page 162

Register Descriptions (Continued) Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description Index 86h Second Level Power Management Status Mirror Register 3 (RO) 7 Video Access Trap SMI Status (Read Only): SMI was caused by ...

Page 163

Register Descriptions (Continued) Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description Index 87h Second Level Power Management Status Mirror Register 4 (RO) 7 GPIO2 SMI Status (Read Only): SMI was caused by transition on ...

Page 164

Register Descriptions (Continued) Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description Index 88h 7:0 General Purpose Timer 1 Count: This field represents the load value for GP Timer 1. This value can represent either ...

Page 165

Register Descriptions (Continued) Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description Index 8Ah 7:0 General Purpose Timer 2 Count: This field represents the load value for GP Timer 2. This value can represent either ...

Page 166

Register Descriptions (Continued) Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description Index 8Fh Index 90h 7 GPIO7 Direction: Selects if GPIO7 is an input or output Input Output. 6 GPIO6 ...

Page 167

Register Descriptions (Continued) Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description Index 92h 7 GPIO7 Edge Sense for Reload of General Purpose Timer 2: Selects which edge transition of GPIO7 causes GP Timer 2 ...

Page 168

... SMI handler reads the SMI Speedup Disable Register (F1BAR+Memory Offset 08h). The latter is the preferred method. The IRQ speedup method is provided for software compatibility with earlier revisions of the CS5530. This bit has no effect if the Suspend Modulation feature is disabled (bit 0 = 0). ...

Page 169

Register Descriptions (Continued) Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description Index 97h 7 GPIO7 Edge Sense for SMI: Selects which edge transition of the GPIO7 pin generates an SMI Rising; 1 ...

Page 170

Register Descriptions (Continued) Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description Index 9Ch-9Dh 15:0 Parallel / Serial Idle Timer Count: This idle timer is used to determine when the parallel and serial ports are ...

Page 171

... IRQ pins that can be used as a Resume event. If GPIO2, GPIO1, and GPIO0 are enabled as an external SMI source (F0 Index 92h[2:0]), they too can be used as a Resume event. No other CS5530 pins can be used to wake-up the system from Suspend when the clocks are stopped. ...

Page 172

Register Descriptions (Continued) Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description Index B4h 7:0 Floppy Port 3F2h Shadow (Read Only): Last written value of I/O Port 3F2h. Required for support of FDC power ON/OFF ...

Page 173

... CPU Clock Stop Normal SUSP#/ SUSPA# handshake Full system Suspend. Note: This register configures the CS5530 to support a 3 Volt Suspend. Setting bit 0 causes the SUSP_3V pin to assert after the appropriate conditions, stopping the system clocks. A delay programmable (bits 7:4) to allow for a delay for the clock chip and CPU PLL to stabilize when an event Resumes the system ...

Page 174

Register Descriptions (Continued) Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description Index CCh 7 Memory or I/O Mapped: User Defined Device Memory. 6:0 Mask: If bit 7 ...

Page 175

Register Descriptions (Continued) Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description Index F4h Second Level Power Management Status Register 1 (RC) 7:5 Reserved 4 Game Port SMI Status (Read to Clear): SMI was caused ...

Page 176

Register Descriptions (Continued) Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description Index F5h Second Level Power Management Status Register 2 (RC) 7 Video Idle Timer SMI Status (Read to Clear): SMI was caused by ...

Page 177

Register Descriptions (Continued) Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description Index F6h Second Level Power Management Status Register 3 (RC) 7 Video Access Trap SMI Status (Read to Clear): SMI was caused by ...

Page 178

Register Descriptions (Continued) Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description Index F7h Second Level Power Management Status Register 4 (RO/RC) 7 GPIO2 SMI Status (Read to Clear): SMI was caused by transition on ...

Page 179

... Index 00h-01h Index 02h-03h Index 04h-05h 15:2 Reserved (Read Only) 1 Memory Space: Allow CS5530 to respond to memory cycles from the PCI bus Disable Enable. This bit must be enabled to access memory offsets through F1BAR (F1 Index 10h). 0 Reserved (Read Only) Index 06h-07h Index 08h Index 09h-0Bh ...

Page 180

Register Descriptions (Continued) Table 4-16. F1BAR+Memory Offset xxh: SMI Status and ACPI Timer Registers Bit Description Offset 00h-01h 15 Suspend Modulation Enable Mirror (Read Only): This bit mirrors the Suspend Mode Configuration bit (F0 Index 96h[0]). It is used by ...

Page 181

Register Descriptions (Continued) Table 4-16. F1BAR+Memory Offset xxh: SMI Status and ACPI Timer Registers (Continued) Bit Description Offset 02h-03h 15 Suspend Modulation Enable Mirror (Read to Clear): This bit mirrors the Suspend Mode Configuration bit (F0 Index 96h[0]). It is ...

Page 182

Register Descriptions (Continued) Table 4-16. F1BAR+Memory Offset xxh: SMI Status and ACPI Timer Registers (Continued) Bit Description Offset 04h-05h Second Level General Traps & Timers SMI Status Mirror Register (RO) 15:6 Reserved (Read Only) 5 PCI Function Trap (Read Only): ...

Page 183

Register Descriptions (Continued) Table 4-16. F1BAR+Memory Offset xxh: SMI Status and ACPI Timer Registers (Continued) Bit Description Offset 06h-07h Second Level General Traps & Timers SMI Status Register (RC) 15:6 Reserved (Read to Clear) 5 PCI Function Trap (Read to ...

Page 184

... Reserved (Read Only) 2 Enable Mastering Disable Enable 1 Reserved (Read Only) 0 I/O Space: Allow CS5530 to respond to I/O cycles from the PCI bus Disable Enable. This bit must be enabled to access I/O offsets through F2BAR (F2 Index 20h). Index 06h-07h Index 08h Index 09h-0Bh Index 0Ch Index 0Dh ...

Page 185

Register Descriptions (Continued) Table 4-18. F2BAR+I/O Offset xxh: IDE Configuration Registers Bit Description Offset 00h IDE Bus Master 0 Command Register — Primary (R/W) 7:4 Reserved: Set to 0. Must return 0 on reads. 3 Read or Write Control: Sets ...

Page 186

Register Descriptions (Continued) Table 4-18. F2BAR+I/O Offset xxh: IDE Configuration Registers (Continued) Bit Description Offset 0Ah IDE Bus Master 1 Status Register — Secondary (R/W) 7 Simplex Mode (Read Only): Can both the primary and secondary channel operate independently? 0 ...

Page 187

Register Descriptions (Continued) Table 4-18. F2BAR+I/O Offset xxh: IDE Configuration Registers (Continued) Bit Description Offset 24h-27h If bit Multiword DMA Settings for: Multiword DMA Mode 0 = 00077771h Multiword DMA Mode 1 = 00012121h Multiword DMA Mode ...

Page 188

... Index 04h-05h 15:3 Reserved (Read Only) 2 Enable Mastering Disable Enable 1 Memory Space: Allow CS5530 to respond to memory cycles from the PCI bus Disable Enable. This bit must be enabled to access memory offsets through F3BAR (F3 Index 10h). 0 Reserved (Read Only) Index 06h-07h Index 08h Index 09h-0Bh ...

Page 189

... Codec Command Address: Address of the codec control register for which the command is being sent. This address goes in slot 1 bits [19:12] on SDATA_OUT. 23:22 CS5530 Codec Communication: Selects which codec to communicate with Primary codec 01 = Secondary codec Note: 00 and 01 are the only valid settings for these bits. ...

Page 190

Register Descriptions (Continued) Table 4-20. F3BAR+Memory Offset xxh: XpressAUDIO Configuration Registers (Continued) Bit Description Offset 10h-11h 15:8 Reserved: Set Audio Bus Master 5 SMI Status (Read to Clear): SMI was caused by an event occurring on Audio ...

Page 191

Register Descriptions (Continued) Table 4-20. F3BAR+Memory Offset xxh: XpressAUDIO Configuration Registers (Continued) Bit Description Offset 12h-13h 15:8 Reserved: Set Audio Bus Master 5 SMI Status (Read Only): SMI was caused by an event occurring on Audio Bus ...

Page 192

Register Descriptions (Continued) Table 4-20. F3BAR+Memory Offset xxh: XpressAUDIO Configuration Registers (Continued) Bit Description Offset 14h-17h 31:24 Fast Path Write Even Access Data (Read Only): These bits contain the data from the last Fast Path Write Even access. These bits ...

Page 193

... Fast Path Read Enable/SMI Disable: Read Fast Path (an SMI is not generated on reads from specified addresses Disable Enable. In Fast Path Read the CS5530 responds to reads of the following addresses: 388h-38Bh; 2x0h, 2x1, 2x2h, 2x3, 2x8 and 2x9h. Note that if neither sound card nor FM I/O mapping is enabled, then status read trapping is not possible. ...

Page 194

Register Descriptions (Continued) Table 4-20. F3BAR+Memory Offset xxh: XpressAUDIO Configuration Registers (Continued) Bit Description Offset 1Ah-1Bh Note: Must be R WORD. 15 IRQ15 Internal: Configure IRQ15 for internal (software) or external (hardware) use External ...

Page 195

Register Descriptions (Continued) Table 4-20. F3BAR+Memory Offset xxh: XpressAUDIO Configuration Registers (Continued) Bit Description Offset 20h Audio Bus Master 0: Output to Codec; 32-Bit; Left and Right Channels; Slots 3 and 4. 7:4 Reserved: Set to 0. Must return 0 ...

Page 196

Register Descriptions (Continued) Table 4-20. F3BAR+Memory Offset xxh: XpressAUDIO Configuration Registers (Continued) Bit Description Offset 29h Audio Bus Master 1: Input from Codec; 32-Bit; Left and Right Channels; Slots 3 and 4. 7:2 Reserved (Read to Clear) 1 Bus Master ...

Page 197

Register Descriptions (Continued) Table 4-20. F3BAR+Memory Offset xxh: XpressAUDIO Configuration Registers (Continued) Bit Description Offset 38h Audio Bus Master 3: Input from Codec; 16-Bit; Slot 5. 7:4 Reserved: Set to 0. Must return 0 on reads. 3 Read or Write ...

Page 198

Register Descriptions (Continued) Table 4-20. F3BAR+Memory Offset xxh: XpressAUDIO Configuration Registers (Continued) Bit Description Offset 41h Audio Bus Master 4: Output to Codec; 16-Bit; Slot (F3BAR+Memory Offset 08h[19] selects slot). 7:4 Reserved (Read to Clear) 1 Bus ...

Page 199

... Index 00h-01h Index 02h-03h Index 04h-05h 15:2 Reserved (Read Only) 1 Memory Space: Allow CS5530 to respond to memory cycles from the PCI bus Disable Enable. This bit must be enabled to access memory offsets through F4BAR (F4 Index 10h). 0 Reserved (Read Only) Index 06h-07h Index 08h Index 09h-0Bh ...

Page 200

Register Descriptions (Continued) Table 4-22. F4BAR+Memory Offset xxh: Video Controller Configuration Registers Bit Description Offset 00h-03h 31 Reserved: Set High Speed Timing for Video Interface: High speed timings for the video interface Disable; 1= Enable. ...

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