CY62128L-70ZI Cypress Semiconductor Corporation., CY62128L-70ZI Datasheet

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CY62128L-70ZI

Manufacturer Part Number
CY62128L-70ZI
Description
128K x 8 Static RAM
Manufacturer
Cypress Semiconductor Corporation.
Datasheet
1.CY62128-70ZAI.pdf (10 pages)
Features
Functional Description
The CY62128 is a high-performance CMOS static RAM orga-
nized as 131,072 words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE
chip enable (CE
three-state drivers. This device has an automatic power-down
Cypress Semiconductor Corporation
• 4.5V
• CMOS for optimum speed/power
• Low active power (70 ns, LL version)
• Low standby power (70 ns, LL version)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE
Logic Block Diagram
WE
CE
CE
OE
— 330 mW (max.) (60 mA)
— 110 W (max.) (20 A)
1
2
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
V
CE
A
A
A
A
WE
A
A
NC
CC
A
A
A
A
A
A
5.5V operation
12
14
16
15
13
11
4
5
6
7
2
8
9
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
2
), an active LOW output enable (OE), and
INPUT BUFFER
512x 256x 8
DECODER
ARRAY
COLUMN
Reverse Pinout
(not to scale)
Top View
TSOP I
POWER
DOWN
1
, CE
2
•
1
, and OE options
), an active HIGH
3901 North First Street
62128-2
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
62128-1
A
A
A
A
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
CE
A
OE
3
2
1
0
10
0
1
2
3
4
5
6
7
1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
CE
V
feature that reduces power consumption by more than 75%
when deselected.
Writing to the device is accomplished by taking chip enable
one (CE
two (CE
I/O
pins (A
Reading from the device is accomplished by taking chip en-
able one (CE
write enable (WE) and chip enable two (CE
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the I/O pins.
The eight input/output pins (I/O
high-impedance state when the device is deselected (CE
HIGH or CE
during a write operation (CE
The CY62128 is available in a standard 450-mil-wide SOIC,
32-pin TSOP type I and STSOP packages.
WE
A
A
A
A
A
A
NC
A
A
CC
A
A
A
A
11
13
15
16
14
12
9
8
2
7
6
5
4
7
) is then written into the location specified on the address
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
0
•
2
1
through A
) input HIGH. Data on the eight I/O pins (I/O
) and write enable (WE) inputs LOW and chip enable
San Jose
2
1
LOW), the outputs are disabled (OE HIGH), or
) and output enable (OE) LOW while forcing
TSOP I/ STSOP
(not to scale)
16
Top View
128K x 8 Static RAM
).
Pin Configurations
•
GND
I/O
I/O
I/O
A
A
A
July 1996 - Revised June 18, 1998
NC
A
A
A
A
A
A
A
A
1
16
14
12
6
5
4
3
2
1
0
0
1
2
7
CA 95134
LOW, CE
Top View
0
13
14
15
16
1
2
3
4
5
6
7
8
9
10
11
12
through I/O
SOIC
2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
62128-2
HIGH, and WE LOW).
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
CE
A
CE
I/O
I/O
I/O
I/O
I/O
V
A
WE
A
A
A
A
OE
•
10
CC
15
13
8
9
11
7
7
6
5
4
3
2
1
OE
A
CE
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
A
A
A
A
) are placed in a
CY62128
2
10
0
1
2
3
fax id: 1072
) HIGH. Under
1
7
6
5
4
3
2
1
0
408-943-2600
0
through
1

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CY62128L-70ZI Summary of contents

Page 1

Features • 4.5V 5.5V operation • CMOS for optimum speed/power • Low active power (70 ns, LL version) — 330 mW (max.) (60 mA) • Low standby power (70 ns, LL version) — 110 W (max.) (20 A) • Automatic ...

Page 2

Selection Guide Maximum Access Time (ns) Maximum Operating Current Maximum CMOS Standby Current Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature ................................. – +150 C Ambient Temperature with ...

Page 3

Electrical Characteristics Over the Operating Range Parameter Description V Output HIGH Voltage OH V Output LOW Voltage OL V Input HIGH Voltage IH [1] V Input LOW Voltage IL I Input Load Current IX I Output Leakage Cur- OZ rent ...

Page 4

AC Test Loads and Waveforms R1 1800 5V OUTPUT OUTPUT R2 100 pF 990 INCLUDING JIG AND SCOPE (a) Equivalent to: THÉVENIN EQUIVALENT 639 OUTPUT [6] Switching Characteristics Over the Operating Range Parameter READ CYCLE t Read Cycle Time RC ...

Page 5

Data Retention Characteristics Parameter Description V VCC for Data Retention DR I Data Retention Current Coml. CCDR [3] t Chip Deselect to Data Retention Time CDR [3] t Operation Recovery Time R Switching Waveforms [11,12] Read Cycle No.1 ADDRESS DATA ...

Page 6

Switching Waveforms (continued) Write Cycle No Controlled ADDRESS DATA I/O Write Cycle No. 2 (WE Controlled, OE HIGH During Write) ADDRESS ...

Page 7

Switching Waveforms (continued) Write Cycle No.3 (WE Controlled, OE LOW) ADDRESS NOTE 16 DATAI/O t Truth Table I/O – I High ...

Page 8

... CY62128-70ZRC CY62128–70SI CY62128 70ZI CY62128-70ZAI CY62128-70ZRI CY62128L 70SC CY62128L 70ZC CY62128L-70ZAC CY62128L-70ZRC CY62128L 70SI CY62128L 70ZI CY62128L-70ZAI CY62128L-70ZRI CY62128LL 70SC CY62128LL 70ZC CY62128LL-70ZAC CY62128LL-70ZRC CY62128LL 70SI CY62128LL-70ZI CY62128LL-70ZAI CY62128LL-70ZRI Document #: 38–00524–B Name Package Type S34 32-Lead 450-Mil SOIC Z32 ...

Page 9

Package Diagrams 32-Lead (450 MIL) Molded SOIC S34 32-Lead Thin Small Outline Package Z32 9 CY62128 51-85081-A 51-85056-B ...

Page 10

Package Diagrams (continued) 32-Lead Shrunk Thin Small Outline Package ZA32 32-Lead Reverse Thin Small Outline Package ZR32 © Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the ...

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