MT4LC4M4E9DJ-6

Manufacturer Part NumberMT4LC4M4E9DJ-6
Description4Meg x 4 banks, EDO DRAM, 3.3V, standard refresh, 60ns
ManufacturerMicron Semiconductor Products
MT4LC4M4E9DJ-6 datasheets

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TECHNOLOGY, INC.
NOTES
1. All voltages referenced to V
.
SS
2. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range (0˚C
T
A
3. An initial pause of 100 s is required after power-up,
followed by eight RAS# refresh cycles (RAS#-ONLY
or CBR with WE# HIGH), before proper device
operation is ensured. The eight RAS# cycle wake-ups
should be repeated any time the
requirement is exceeded.
4. NC pins are assumed to be left floating and are not
tested for leakage.
5. I
is dependent on output loading and cycle rates.
CC
Specified values are obtained with minimum cycle
time and the outputs open.
6. Column address changed once each cycle.
7. Enables on-chip refresh and address counters.
8. This parameter is sampled. V
CC
t
9. AC characteristics assume
T = 2.5ns.
10. V
(MIN) and V
(MAX) are reference levels for
IH
IL
measuring timing of input signals. Transition times
are measured between V
and V
IH
and V
).
IH
11. In addition to meeting the transition rate specifica-
tion, all input signals must transit between V
V
(or between V
and V
) in a monotonic manner.
IL
IL
IH
12. Measured with a load equivalent to two TTL gates
and 100pF; and V
= 0.8V and V
OL
t
t
t
t
13.
WCS,
RWD,
AWD and
CWD are not restrictive
t
operating parameters.
WCS applies to EARLY
t
t
WRITE cycles.
RWD,
AWD and
READ-MODIFY-WRITE cycles. If
(MIN), the cycle is an EARLY WRITE cycle and the
data output will remain an open circuit throughout
t
t
the entire cycle. If
WCS <
WCS (MIN) and
t
t
t
RWD (MIN),
AWD
AWD (MIN) and
t
CWD (MIN), the cycle is a READ-MODIFY-WRITE
and the data output will contain data read from the
selected cell. If neither of the above conditions is met,
the state of data-out is indeterminate. OE# held HIGH
and WE# taken LOW after CAS# goes LOW results in
a LATE WRITE (OE#-controlled) cycle.
t
t
CWD and
AWD are not applicable in a LATE
WRITE cycle.
t
t
14. Requires that
AA and
RAC are not violated.
15. If CAS# is LOW at the falling edge of RAS#, Q will be
maintained from the previous cycle. To initiate a new
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
cycle and clear the data-out buffer, CAS# must be
pulsed HIGH for
16. These parameters are referenced to CAS# leading
70˚C) is ensured.
edge in EARLY WRITE cycles and WE# leading edge
in LATE WRITE or READ-MODIFY-WRITE cycles.
17. If OE# is tied permanently LOW, LATE WRITE or
READ-MODIFY-WRITE operations are not permis-
sible and should not be attempted. Additionally, WE#
t
REF refresh
must be pulsed during CAS# HIGH time in order to
place I/O buffers in High-Z.
18. LATE WRITE and READ-MODIFY-WRITE cycles
must have both
during WRITE cycle) in order to ensure that the
output buffers will be open during the WRITE cycle.
The DQs will provide the previously read data if
CAS# remains LOW and OE# is taken back LOW
after
= V
; f = 1 MHz.
going back LOW, the DQs will remain open.
CC
MIN
19. Requires that
t
20.
OFF (MAX) defines the time at which the output
achieves the open circuit condition and is not
(or between V
referenced to V
IL
IL
rising edge of RAS# or CAS#, whichever occurs last.
21. The
and
(MAX) was specified as a reference point only. If
IH
t
RAD was greater than the specified
limit, then access time was controlled exclusively by
t
= 2V.
AA (
OH
without the
must always be met.
t
CWD apply to
22. The
t
t
WCS
WCS
(MAX) was specified as a reference point only. If
t
RCD was greater than the specified
limit, then access time was controlled exclusively by
t
t
RWD
CAC (
t
CWD
without the
be met.
23. Either
cycle.
24. A HIDDEN REFRESH may also be performed after
a WRITE cycle. In this case, WE# is LOW and
t
t
WCS,
RWD,
OE# is HIGH.
25.
The refresh period is extended from 32ms (2K refresh)
or 64ms (4K refresh) to 128ms (both 2K and 4K
refreshes). For 4K refresh,
4,096 rows = 31.25 s) and for 2K refresh,
(128ms/2,048 rows = 62.5 s).
10
4 MEG x 4
EDO DRAM
t
CP.
t
t
OD and
OEH met (OE# HIGH
t
OEH is met. If CAS# goes HIGH prior to OE#
t
t
AA and
CAC are not violated.
or V
. It is referenced from the
OH
OL
t
RAD (MAX) limit is no longer specified.
t
RAD (MAX)
t
t
RAC and
CAC no longer applied). With or
t
t
t
RAD (MAX) limit,
AA,
RAC and
t
RCD (MAX) limit is no longer specified.
t
RCD (MAX)
t
RAC [MIN] no longer applied). With or
t
t
t
RCD limit,
AA and
CAC must always
t
t
RCH or
RRH must be satisfied for a READ
t
RC = 31.25 s (128ms/
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RAD
t
CAC
t
RCD
t
RC = 62.5 s
1997, Micron Technology, Inc.

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