MFC2000 Conexant Systems, Inc., MFC2000 Datasheet
MFC2000
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... MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Doc. No. 100723A June 21, 2000 ...
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... Ordering Information Marketing Name MFC2000 Revision History Revision Date A 04/07/00 A 06/21/00 © 2000, Conexant Systems, Inc. All Rights Reserved. Information in this document is provided in connection with Conexant Systems, Inc. ("Conexant") products. These materials are provided by Conexant as a service to its customers and may be used for informational purposes only. Conexant assumes no responsibility for errors or omissions in these materials ...
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... INTRODUCTION .............................................................................................................................................. 1-1 1.1 SCOPE ...................................................................................................................................................... 1-1 1.2 SYSTEM OVERVIEW ................................................................................................................................ 1-1 1.3 REFERENCE DOCUMENTATION............................................................................................................ 1-5 2. MFC2000 SUMMARY ...................................................................................................................................... 2-1 2.1 MFC2000 DEVICE FAMILY....................................................................................................................... 2-1 2.2 MFC2000 SYSTEM BLOCK DIAGRAM .................................................................................................... 2-1 3. HARDWARE INTERFACE............................................................................................................................... 3-1 3.1 PIN DESCRIPTION ................................................................................................................................... 3-1 3.2 MAXIMUM RATINGS................................................................................................................................. 3-7 3.3 ELECTRICAL CHARACTERISTICS.......................................................................................................... 3-8 3.4 PIN LAYOUT............................................................................................................................................ 3-10 4. CPU AND BUS INTERFACE ........................................................................................................................... 4-1 4.1 MEMORY MAP AND CHIP SELECT DESCRIPTION ............................................................................... 4-1 4.2 CACHE MEMORY CONTROLLER.......................................................................................................... 4-19 4.3 SIU………. ............................................................................................................................................... 4-24 4 ...
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... BI-LEVEL RESOLUTION CONVERSION ....................................................................................................... 9-1 9.1 FUNCTIONAL DESCRIPTION .................................................................................................................. 9-1 9.2 REGISTER DESCRIPTION ....................................................................................................................... 9-6 9.3 RESOLUTION CONVERSION PROGRAMMING EXAMPLES............................................................... 9-15 10. EXTERNAL PRINT ASIC INTERFACE ......................................................................................................... 10-1 10.1 INTERFACE BETWEEN THE MFC2000 AND EXTERNAL PRINT ASIC .......................................... 10-1 11. BIT ROTATION LOGIC.................................................................................................................................. 11-1 11.1 FUNCTIONAL DESCRIPTION ............................................................................................................ 11-1 11.2 BLOCK DIAGRAM............................................................................................................................... 11-3 11.3 REGISTER DESCRIPTION................................................................................................................. 11-6 11.4 FIRMWARE OPERATION................................................................................................................. 11-10 12. PRINTER AND SCANNER STEPPER MOTOR INTERFACE ...................................................................... 12-1 12 ...
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REAL-TIME CLOCK ...................................................................................................................................... 18-1 18.1 DESCRIPTION .................................................................................................................................... 18-1 18.2 REAL-TIME CLOCK (RTC) REGISTERS ........................................................................................... 18-2 18.3 RTC OPERATIONS............................................................................................................................. 18-3 19. SYNCHRONOUS SERIAL INTERFACE (SSIF)............................................................................................ 19-1 19.1 INTRODUCTION AND FEATURES .................................................................................................... 19-1 19.2 REGISTER DESCRIPTION................................................................................................................. 19-2 19.3 SSIF TIMING ....................................................................................................................................... ...
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... Figure 1-1. MFP System Diagram Using MFC2000 .............................................................................................................. 1-1 Figure 1-2: MFC2000 Function Diagram ............................................................................................................................... 1-4 Figure 2-1. MFC2000 Organization ....................................................................................................................................... 2-2 Figure 3-1. MFC2000 BGA Bottom View ............................................................................................................................. 3-10 Figure 4-1. MFC2000 Memory Map....................................................................................................................................... 4-6 Figure 4-2. MFC2000 Internal Memory Map.......................................................................................................................... 4-7 Figure 4-3. MFC2000 Cache Organization .......................................................................................................................... 4-19 Figure 4-4. 2-Way Interleave ROM Connection................................................................................................................... 4-26 Figure 4-5. Zero Wait State, Single Access, Normal Read, Normal Write ........................................................................... 4-36 Figure 4-6 ...
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... Figure 5-7. Voltage Divider Circuit....................................................................................................................................... 5-11 Figure 5-8. Watchdog Timer Block Diagram........................................................................................................................ 5-12 Figure 5-9. Watchdog Time-Out Timing Diagram ................................................................................................................ 5-13 Figure 6-1. Fax Timing Control Logic Block Diagram ............................................................................................................ 6-2 Figure 6-2. MFC2000 Timing Chain ...................................................................................................................................... 6-3 Figure 6-3. Scan Control Timing............................................................................................................................................ 6-4 Figure 7-1. Video/Scanner Controller Block Diagram ............................................................................................................ 7-1 Figure 7-2. Untitled Timing Diagram .................................................................................................................................... 7-19 Figure 7-3. Untitled Timing Diagram .................................................................................................................................... 7-20 Figure 7-4 ...
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... Figure 11-1. Nozzle Diagram of a Typical Programmable Inkjet Head ................................................................................ 11-1 Figure 11-2. Examples of Nozzle Head Configurations ....................................................................................................... 11-2 Figure 11-3. Nozzle Configuration by Bit Rotation Block (Regardless of Physical Nozzle Configuration) ........................... 11-2 Figure 11-4. MFC2000 Bit Rotation Block Diagram............................................................................................................. 11-3 Figure 11-5. Fetcher DMA Channel Fetch Order................................................................................................................. 11-4 Figure 11-6. CPU Background Print Data Preparation ...................................................................................................... 11-12 Figure 11-7 ...
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Figure 22-1: CPC Signal...................................................................................................................................................... 22-1 Figure 22-2. CPC Operation Flowchart ............................................................................................................................... 22-2 Figure 22-3: CPC Operation (with CPCThreshold = 4)........................................................................................................ 22-3 Figure 22-4: CPC Block Diagram ........................................................................................................................................ 22-4 Figure 23-1. System Configuration One .............................................................................................................................. 23-1 Figure 23-2. System Configuration Two ...
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... Table 4-6. Read Operation (Internal Peripheral Gets Data From Memory) ......................................................................... 4-29 Table 4-7. Write Operation (Internal Peripheral Puts Data Into Memory) ............................................................................ 4-29 Table 4-8. Read/Write with Wait States Timing Parameters................................................................................................ 4-45 Table 4-9. MFC2000 Interrupt and Reset Signals ............................................................................................................... 4-46 Table 4-10. Programmable Resolution of Timer1 and Timer2 ............................................................................................. 4-53 Table 4-11. DRAM Wait State Configurations ..................................................................................................................... 4-55 Table 4-12 ...
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Table 8-6. PADC Timing Diagram ......................................................................................................................................... 8-4 Table 8-7. TADC Block Diagram ........................................................................................................................................... 8-5 Table 9-1. Untitled Table ....................................................................................................................................................... 9-2 Table 9-2: Procedure to determine Pixels to remove........................................................................................................... 9-17 Table 9-3: Resolution Conversion Examples....................................................................................................................... 9-17 Table 12-1. Full Step/Single Phase ...
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This page is intentionally blank Conexant 100723A ...
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... If V.17 or V.34 faxing without voice is required, the internal V.17/V.34 Fax Modem in the MFC2000 chip is used and the MFC2000 is connected to the external Conexant SmartDAA or IA chip. If the voice/speech function is required, the external Voice Fax Modem device from Conexant will be needed. Any other external interface device can be supported by using the external ARM for CPU and DMA accesses or by using the internal serial interface ...
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... MFC2000 performs no resolution conversion. If host printing and faxing need to be performed for the same image, the printing image data must be sent to the MFP. The MFC2000 converts the printing image data to the faxing image data locally and then faxes it out. An external printer interface chip is designed to support inkjet print mechanism/head subsystems ...
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... The Conexant MFC2000 Evaluation System provides demonstration, prototype development, and evaluation capabilities to full color MFP developers using the MFC2000 Engine device set. The MFC2000 Evaluation system provides flexibility for visibility and access, i.e., plug-on board for the modem, sockets for programmable parts, and connectors for an emulator (refer to Figure 1-2) ...
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... MFC2000 Multifunctional Peripheral Controller 2000 100 MHz 85.7 MHz 28.224 28.224 48 MHz MHz for for USB Mono and Color CIS Control Scanner In Analog 12-bit Frontend External Conexant Signal Video Chip 1-4 32 Cache Controller ...
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... Hardware Description 1.3 Reference Documentation MFC2000 Data Sheet MFC2000 Firmware Architecture MFC2000 Hardware Description (this document) MFC2000 Programmer’s Reference Manual 100723A Table 1-1. Reference Documentation Document Conexant MFC 2000 Multifunctional Peripheral Controller 2000 Number 100505 100972 100723 100971 1-5 ...
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... MFC2000 Multifunctional Peripheral Controller 2000 1-6 This page is intentionally blank Conexant Hardware Description 100723A ...
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... MFC2000 Summary 2.1 MFC2000 Device Family The MFC2000 contains an internal 32-bit RISC Processor with 64-MB address space, the Countach Imaging DSP (Conexant’s DSP) subsystem including embedded data and program memory, and dedicated circuitry optimized for color scanning, color faxing, color copying, color printing, and multifunctional control and monitoring. The device family with relevant features is described in Table 2-1 ...
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... MFC2000 Multifunctional Peripheral Controller 2000 PLL Clock Generator Timing Control Prime/Battery Power and Reset Control DMA Controller IRQ/CPU Access Scan/Print IRQ/ Motor Motor CPU Drivers Controller Access Sync/ IRQ/ Async CPU Serial Port Access Sync CPU Serial Access Panel IF Serial CPU ...
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... ROM chip select (active low) I/O chip select (active low). SRAM chip select (active low) (VRTC powered) DRAM row Address select for bank 0 and 1(active low) (VDRAM powered) DRAM column odd address selects used for non- interleave mode and interleave mode. (VDRAM powered) MFC2000 3-1 ...
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... External DMA request input (channel 2). Flash memory chip select 0 or PWM channel 1 output Flash memory chip select 1 or PWM channel 2 output signal. (Hysteresis, Pull up) MFC2000 Reset input/output - Crystal oscillator input pin for RTC. (VRTC powered) Crystal oscillator output pin for RTC. (VRTC powered) ...
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Hardware Description Pin Name GPIO[6]/CS[4]n/ EADC_D[3] U1 GPIO[7]/CS[5] GPIO[8]/IRQ[11]/ SSSTAT1/SC_CLK1/2B GPIO[9]/IRQ[13]/ EADC_D[2] T2 GPIO[10]/RING_DETECT/PW T1 M[4] GPIO[11]/CPCIN/PWM[0]/ALT R4 TONE GPIO[12]/SASCLK/ R3 SMPWRCTRL GPIO[13]/SASTXD/ R2 PMPWRCTRL GPIO[14]/SASRXD/ RINGER R1 GPIO[15]/IRQ[16]/ P4 SC_CLK1/2C GPIO[16]/M_TXSIN P3 GPIO[17]/M_CLKIN P2 GPIO[18]/M_RXOUT P1 GPIO[19]/M_SCK/MIRQn ...
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... Hardware Description Pin Description PIO Returned status to PC PIO Returned status to PC PIO Returned status to PC (active low) (Hysteresis) Driven MFC2000 and used to send data or address depending on which mode is used - (Hysteresis) For test only, It must be ‘low’ for the normal operation ...
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Hardware Description Pin Name SDADDR[12:0] V20,W20,Y20, W19,Y19,W18, Y18,W17,Y17,V 16,W16,Y16,V1 5 SDCASn U20 SDRASn V19 SDWRn V18 SDCSn V17 SDCLK100MHz M19 USB_Dp B8 USB_Dn C8 SDAA_PWRCLK E1 SDAA_PWRCLKn E2 SDAA_DIBp E4 SDAA_DIBn E3 EV_VD[0]/EADC_D[4]/ MREQn W12 EV_VD[1]/EADC_D[5] U12 EV_VD[2]/EADC_D[6]/ OPCn Y13 ...
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... MFC2000 Multifunctional Peripheral Controller 2000 Pin Name DMACYC/ CLK_CONFIG[2] M18 WAITn J17 CACHEHIT/ J18 JTAG_MODE_SEL SEQ N17 SSD_DIBRX F3 TX_DATA F2 SDAA_GPIO_INT F1 VSS L1,L2,L3,L4,U1 0,V10,W10,Y10, L17,L18,L19,L2 0,A11,B11,C11, D11 VDD A10,B10,C10,K 1,K2,K3,K4,U11 ,V11,W11,Y11, K17,M20 P80VSS M1 P80VDD M2 VGG1 M17 VGG2 D14 VGG3 D5 VGG4 M4 VDRAM E18 VRTC ...
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Hardware Description 3.2 Maximum Ratings Parameter VDD Digital Power Battery Power VGG Digital Power Digital GND Digital Input (3V) Digital Input (5VT) Operating Temperature Range (Commercial) Storage Temperature Range Voltage Applied to Outputs in High Z State (3V) Voltage Applied ...
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... MFC2000 Multifunctional Peripheral Controller 2000 3.3 Electrical Characteristics Symbol Description 3V 3V CMOS input U3V 3V CMOS input w/pullup H3V 3V CMOS input w/hysteresis HD3V 3V CMOS input w/hysteresis and pull down HU3V 3V CMOS input w/hysteresis and pullup H5VT 5V tolerant CMOS input w/hysteresis U5VT 5V tolerant CMOS ...
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Hardware Description Symbol Description VGG Digital Power for 5VT VDD Digital Power GND Digital GND IDD Total Digital Current VBAT Battery Power VDRAM Battery Power Note: * Maximum power supply current is measured at 3.6V. Table 3-6. Battery Power Supply ...
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... MFC2000 Multifunctional Peripheral Controller 2000 3.4 Pin Layout 3- Chip Bottom View Figure 3-1. MFC2000 BGA Bottom View Conexant Hardware Description 100723A ...
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... M) are arranged for the external device/memory use on the ARM Bus. Only 24 address lines (A23-A0) are brought out of the MFC2000 chip, and the lower half and the higher half are multiplexed through the same 12 pins. The 16 MB address range (maximum) can be decoded externally, if necessary ...
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... MFC2000 Multifunctional Peripheral Controller 2000 The internal RAM space includes the following: 1. Bit rotation RAM area Bit rotation RAM: 512 halfwords (1 kB) (Reserved) (3072 bytes) 2. Countach Subsystem memory area Countach Scratch Pad (512 bytes) (256 halfwords)(01FFA000h-01FFA1FFh) Countach Data DMA Channel 0 (1 halfword) ...
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... Most external chip selects have programmable address ranges, start locations, wait states, and read and write strobe timing. SRAM and DRAM/ARAM chip select controls are battery-backed up. Refer to Figure 4-1 for the MFC2000 memory map and to Figure 4-2 for the internal memory map. ...
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... MFC2000 Multifunctional Peripheral Controller 2000 ROMCSn FCS1n/FCS0n CS0n CS1n (Optional) Optional MCSn (Optional) CS2n CS3n (Optional) CS4n (OptionaL0 CS5n DRAM/ARAM chip selects can also be programmed sizes (from 512 M). ROM Chip Select (ROMCSn) ROMCSn selects external ROM located in 4-MB address space 00000000h-003FFFFFh, and is active for read and write accesses ...
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Hardware Description Flash Memory Chip Selects (FCS1n and FCS2n) FCS0n and FCS1n are multiplexed with PWM[1] and PWM[2] and output through FCS0n/PWM[1] and FCS1n/PWM[2] pins. After reset, the Flash disable bit (bit 0) of the FlashCtrl register is 0 and ...
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... SDRAM 017FFFFF (reserved) 01FDFFFF 01FFFFFF RASn[0] 02FFFFFF RASn[1] 03FFFFFF 4-6 (reserved) cachecs (reserved) imemcs RASn[0] Figure 4-1. MFC2000 Memory Map Conexant Hardware Description 01FDFFFF 01FEFFFF ics 01FF7FFF iiocs 01FF8FFF 01FFFFFF 100723A ...
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... F Tag memory 01FF8FF F (reserved) iiocs 01FF8FFF Bit Rotation Buffer 01FF93FF 01FFA000 Countach ScratchPad 01FFA3FF VSI Buffer 01FFA4FF 01FFFFFF RASn[0] Figure 4-2. MFC2000 Internal Memory Map Conexant MFC 2000 Multifunctional Peripheral Controller 2000 01FDFFFF 01FE0FFF cachecs C 01FE1FFF imemcs 4-7 ...
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... MFC2000 Multifunctional Peripheral Controller 2000 4.1.2 Register Map Operation registers are located from 01FF8000H to 01FF87FFH. Address Register Name 01FF8000-01 TADCCtrl 01FF8002-03 TADCInsData 01FF8004-05 TADCCh0Data 01FF8006-07 TADCCh1Data 01FF8008-09 TADCCh2Data 01FF800A-1F (Not Used) 01FF8020-21 IRQFIQEvent1 01FF8022-23 IRQFIQEvent2 01FF8024-25 IRQEnable1 01FF8026-27 IRQEnable2 01FF8028-29 FIQEnable1 01FF802A-2B ...
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Hardware Description Address Register Name 01FF8072-73 BiRCInFIFO1 01FF8074-75 BiRCInFIFO2 01FF8076-77 BiRCInFIFO3 01FF8078-79 BiRCInHold 01FF807A-7B BiRCInFIFOCtrl 01FF807C-7D BiResConRatio 01FF807E-7F BiResConCtrl 01FF8080-81 BiRCOutFIFO0 01FF8082-83 BiRCOutFIFO1 01FF8084-85 BiRCOutFIFO2 01FF8086-87 BiRCOutFIFO3 01FF8088-89 BiRCOutHold 01FF808A-8B BiRCOutFIFOCtrl 01FF808C-8D SinglingMask 01FF808E-8F HSZeroNo 01FF8090-1 Sec_Min 01FF8092-3 Hour_Day 01FF8094-5 ...
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... MFC2000 Multifunctional Peripheral Controller 2000 Address Register Name 01FF80C8-C9 PWMCh4Ctrl 01FF80CA-CF (Not Used) 01FF80D0-DF (Not Used) 01FF80E0-EF (Reserved) 01FF80F0-1 SASCmd 01FF80F2-3 SASData 01FF80F4-5 SASDiv 01FF80F6-7 (Not Used) 01FF80F8-9 SASIRQSTS 01FF80FA-FF (Not Used) 01FF8100 SSCmd 01FF8102 SSData 01FF8104 SSDiv 01FF8106-07 (Not Used) ...
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Hardware Description Address Register Name 01FF815E-5F T4RefDataPortTfr 01FF8160-61 T4CurDataFIFO0 01FF8162-63 T4CurDataFIFO1 01FF8164-65 T4CurDataFIFO2 01FF8166-67 T4CurDataFIFO3 01FF8168-69 T4CurDataHold 01FF816A-6B T4CurDataFIFOCtrl 01FF816C-6D T4CurDataPort 01FF816E-6F T4CurDataPortTfr 01FF8170-71 T4Config 01FF8172-73 T4Control 01FF8174-75 T4 Status 01FF8176-77 T4IntMask 01FF8178-79 T4Bytes 01FF817A-7B T4FIFOBitRem 01FF817C-7F (Not Used) 01FF8180-81 ...
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... MFC2000 Multifunctional Peripheral Controller 2000 Address Register Name 01FF81B0-B1 DMA0Config 01FF81B2-B3 DMA2Config 01FF81B4-B5 DMA2BlkSize 01FF81B6-B7 DMA2BufBlkSize 01FF81B8-B9 (Not Used) 01FF81BA-BB DMA5BlkSize 01FF81BC-BD DMA6/10Throttle 01FF81BE-BF DMA9BlkSize 01FF81C0-C1 DMA10BlkSize 01FF81C2-C3 DMAIncConfig 01FF81C4-C5 DMACntEnbConfig 01FF81C6-C7 DMAEndian 01FF81C8-C9 DMAUSB0CntLo 01FF81CA-CB DMAUSB0CntHi 01FF81CC-CD DMAUSB0BlkSiz 01FF81CE-CF DMAUSB1CntLo ...
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Hardware Description Address Register Name 01FF8212-13 PIOFIFOIF 01FF8214-1F (Not Used) 01FF8220-21 PIOOutFIFO0 01FF8222-23 PIOOutFIFO1 01FF8224-25 PIOOutFIFO2 01FF8226-27 PIOOutFIFO3 01FF8228-29 PIOOutHold 01FF822A-2B PIOOutFIFOCtrl 01FF822C-2F (Not Used) 01FF8230-31 PIOInFIFO0 01FF8232-33 PIOInFIFO1 01FF8234-35 PIOInFIFO2 01FF8236-37 PIOInFIFO3 01FF8238-39 PIOInHold 01FF823A-3B PIOInFIFOCtrl 01FF823C-4F (Not Used) ...
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... MFC2000 Multifunctional Peripheral Controller 2000 Address Register Name 01FF82AC-AD DefWrHiAddr 01FF82AE-AF DefWrLoAddr 01FF82B0-B1 DefRdData 01FF82B2-B3 DefWrData 01FF82B4-FF (Not Used) 01FF8300-01 ABIA2Cbuff1 01FF8302-03 ABIA2Cbuff2 01FF8304-05 ABIA2Cbuff3 01FF8306-07 ABIA2Cbuff4 01FF8308-09 ABIC2Abuff1 01FF830A-0B ABIC2Abuff2 01FF830C-0D ABIC2Abuff3 01FF830E-0F ABIC2Abuff4 01FF8310-11 CSIDMABuff1 01FF8312-13 CSIDMABuff2 01FF8314-15 CSIDMABuff3 ...
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Hardware Description Address Register Name 01FF85AA-AB USBEP2Ctrl 01FF85AC-AD USBEP2Data 01FF85AE-AF USBEP2Tran 01FF85B0-B1 USBEP3FIFO1 01FF85B2-B3 USBEP3FIFO2 01FF85B4-B5 USBEP3FIFO3 01FF85B6-B7 USBEP3FIFO4 01FF85B8-B9 USBEP3Hold 01FF85BA-BB USBEP3Ctrl 01FF85BC-BD USBEP3Data 01FF85BE-BF USBEP3Tran 01FF85C0-C1 USBEP4FIFO1 01FF85C2-C3 USBEP4FIFO2 01FF85C4-C5 USBEP4FIFO3 01FF85C6-C7 USBEP4FIFO4 01FF85C8-C9 USBEP4Hold 01FF85CA-CB USBEP4Ctrl 01FF85CC-CD ...
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... MFC2000 Multifunctional Peripheral Controller 2000 Address Register Name 01FF8600-01 SASTxFIFOHW0 01FF8602-03 SASTxFIFOHW1 01FF8604-05 SASTxFIFOHW2 01FF8606-07 SASTxFIFOHW3 01FF8608-09 SASTxFIFOHW4 01FF860A-0B SASTxFIFOHW5 01FF860C-0D SASTxFIFOHW6 01FF860E-0F SASTxFIFOHW7 01FF8610-11 SASRxFIFOHW0 01FF8612-13 SASRxFIFOHW1 01FF8614-15 SASRxFIFOHW2 01FF8616-17 SASRxFIFOHW3 01FF8618-19 SASRxFIFOHW4 01FF861A-1B SASRxFIFOHW5 01FF861C-1D SASRxFIFOHW6 01FF861E-1F SASRxFIFOHW7 01FF8620-7FF ...
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Hardware Description Setup Registers are located from 01FF8800H to 01FF8DFFH. Address Register Name 01FF8800-01 SIUConfig 01FF8802-03 ROMCtrl 01FF8804-05 CS0/CS5Ctrl 01FF8806-07 CS1/2Ctrl 01FF8808-09 MCSCtrl 01FF880A-0B FlashCtrl 01FF880C-0D RotPackCtrl 01FF880E-0F CS3/4Ctrl 01FF8820-21 DRAMCtrl 01FF8822-2F (Not Used) 01FF8830-31 GPIOConfig 01FF8832-33 GPIOData 01FF8834-35 GPIODir ...
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... MFC2000 Multifunctional Peripheral Controller 2000 Address Register Name 01FF88A6-A7 ClampCtrl 01FF88A8-A9 ClampDelay 01FF88AA-AB ClampEdges 01FF88AC-AD LED0Edges 01FF88AE-AF LED1Edges 01FF88B0-B1 LED2Edges 01FF88B2-B3 LED0PWM 01FF88B4-B5 LED1PWM 01FF88B6-B7 LED2PWM 01FF88B8-B9 LEDConfig 01FF88BA-BB ScanIAConfig 01FF88BC-BD ScanCtrlDelay 01FF88BE-BF ADCConfig 01FF88C0-C1 SPIConfig 01FF88C2-C3 SPIData 01FF88C4-C5 (Not Used) ...
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... ARM to bypass the Cache Controller unit. 1 bit 100723A Way 1 Way 0 1 bit 1 bit 21 bits 32 bits v a[ Cache Tag (128 Sets) Figure 4-3. MFC2000 Cache Organization Conexant MFC 2000 Multifunctional Peripheral Controller 2000 16 bytes 32 bits 32 bits 32 bits Cache RAM ( 2K Bytes ) 4-19 ...
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... MFC2000 Multifunctional Peripheral Controller 2000 Table 4-4. Cache Tag Data Format (for Test Mode Read/Write Operation) 31 30: 20:0 4.2.1.3 Cache RAM The Cache RAM consists of four 512 X 16 Asynchronous Static RAM modules, and they are organized into two 512 words (32 bit/word) to support two way set associative. The memory map for direct accesses while in Test ...
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Hardware Description If the access results in a hit, the wait state is de-asserted and a 32-bit Cache data is output to the ARM. Subsequent Sequential (S-cycles) access(es) require zero wait state if they are found in the same Cache ...
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... MFC2000 Multifunctional Peripheral Controller 2000 4.2.2 Register Description Name/Address Bit 7 Bit 6 Cache Control N/A Flush Cache Global Lock Register $01FF8800 This register resides in the SIU block. The SIU, upon detecting the set condition for a given bit(s) in this register, asserts the corresponding control signal(s) to the Cache controller. ...
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Hardware Description 4.2.3 Firmware Operation 4.2.3.1 Enabling the Cache The Cache Enable bit in the SIU Cache Control register determines if the Cache is enabled or not. In power-up reset state, the Cache is disabled. If disabled, all CPU accesses ...
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... ROM interleave control (including wait state control for the interleave mode): no interleave and 2-way interleave with external Q-switch. 5. Fast page mode ROM operation. 6. Even though ARM7TDMI is fixed to the little endian in this MFC2000 chip, the SIU can support the little endian or big endian for the DMA operation. 7. Support Arm and Thumb mode operations. ...
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Hardware Description ISB Bus The ISB Bus is used for connecting ARM and Cache Controller to the highest performance. The 32-bit ISB bus directly interfaces with the ARM core 32-bit data bus. The cache memory controller resides on this bus. ...
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... The MFC2000 assigns 4 multi-function pins (AE[2], AO[2], AE[3], and AO[3]) to facilitate the interleave access. SIU generates 4 signals on these 4 pins to control ROMs for the following types of interleave accesses. In 2-way interleave mode, MFC2000 pins AE[2] ,AO[2], AE[3], and AO[3] are connected to pin A[1:0] of the even and odd external ROMs. MFC2000 pins A[1:0] are used to enable the ROM’s data busses. ...
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Hardware Description ROM Access Data Type Cache Memory Mode 8-bit non- instruction Cache enabled interleave and Cache miss 16-bit non- instruction Cache enabled interleave and Cache miss 8-bit non- instruction Cache disabled interleave 16-bit non- instruction Cache disabled interleave 8-bit ...
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... MFC2000 Multifunctional Peripheral Controller 2000 If the ROM write access (Flash memory in the ROM address range) is performed in the interleave access mode, the SIU still generates those signals to control ROMs and external multiplexes to perform the interleave access. But, all the access (no matter the sequential access or not) have W wait states. ...
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Hardware Description Table 4-6. Read Operation (Internal Peripheral Gets Data From Memory) DMA SIZE MEM SIZE Half Word Byte Half Word Byte Half Word Half Word Half Word Half Word Table 4-7. Write Operation (Internal Peripheral Puts Data Into Memory) ...
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... MFC2000 Multifunctional Peripheral Controller 2000 4.3.2 Register Description SIU Control Address Bit 15 Bit 14 SIU Configuration (Not Used) (Not Used) (SIUConfig) 01FF8801 Address Bit 7 Bit 6 SIU Configuration CS3n Write Flush Only Cache (SIUConfig) 01FF8800 Bit 8 CS4n Read only Bit 7 CS3n Write only Bit 6 Flush: Write only bit ...
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Hardware Description External Chip Select Control Registers Associated with each external chip select pin is a register to control automatic functions that will be executed when a location within the chip select range is accessed. All bits default to 0 ...
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... MFC2000 Multifunctional Peripheral Controller 2000 Address Bit 15 Bit 14 CS5 Control Write Strobe Read/Write Early Off Strobe (CS5Ctrl) Delay On[1] 01FF8805 Address Bit 7 Bit 6 CS0 Control Write Strobe Read/Write Early Off Strobe (CS0Ctrl) Delay On 01FF8804 Bit 7,15 Write Strobe Early Off Bit 6,14-13 Read/Write Strobe Delay On ...
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Hardware Description Bit 4 Size Bit[3:1] Wait states Bit 0 CS1n Enable Address Bit 15 Bit 14 CS4 Control Read/Write Write Strobe Strobe (CS4Ctrl) Delay Early Off 01FF880F On[1] Address Bit 7 Bit 6 CS3 Control Read/Write Write Strobe Strobe ...
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... MFC2000 Multifunctional Peripheral Controller 2000 Bit 4 Size Bit 3,2&1 Wait states (default =0) Bit 0 MCSn Enable. (default = 1) Address: Bit 15 Bit 14 Flash Memory (Not Used) (Not Used) (Not Used) Control (FlashCtrl) 01FF880B Address: Bit 7 Bit 6 Flash Memory Write Strobe FCSn Control Early Off ...
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Hardware Description Address Bit 15 Bit 14 RotPacked (Not Used) (Not Used) (Not Used) (Not Used) (Not Used) (Not Used) (Not Used) (Not Used) Rst. Value Data register Access Control (RotPackCtrl) 01FF880D Address Bit 7 Bit 6 RotPacked Read/Write Write ...
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... MFC2000 Multifunctional Peripheral Controller 2000 4.3.3 Timing (internal clock) A ARM_A[31:0] ALE EXT_AD[11: CSn RDn WRn Read Data Write Data Figure 4-5. Zero Wait State, Single Access, Normal Read, Normal Write 4- ...
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Hardware Description (internal clock) A ARM_A[31:0] ALE EXT_AD[11:0] A[23:12] A[11:0] CSn RDn WRn Read Data Write Data Figure 4-6. One Wait State, Single Access, One Read, One Write 100723A Internal A[11:0]+2 B[23:12] B[11:0] Byte0 ...
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... MFC2000 Multifunctional Peripheral Controller 2000 (internal clock) A ARM_A[31:0] ALE EXT_AD[11:0] A[23:12] A[11:0] CS1n CS2n RDn WRn Read Data Write Data Figure 4-7. Two Wait States, Single Access, Read On Delayed (CS1n), Write Early Off (CS2n) 4-38 A[11:0]+ B[11:0] Byte0 Conexant Hardware Description B B[11:0]+2 C[23:12] C[11:0] Byte1 ...
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Hardware Description (internal clock ARM_A[31:0] ALE EXT_AD[11: ...
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... MFC2000 Multifunctional Peripheral Controller 2000 (internal clock) A ARM_A[31:0] ALE EXT_AD[11: ROMCSn RDn WREn/WROn Figure 4-9. Fast Page Mode ROM Access 1,0,0 Read Access Followed by 1,1,1,1, Write Access 4- A+2 A B[11:0] Conexant Hardware Description ...
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Hardware Description Detail External Bus Timing (internal clock) A[11: ALE Ext. CS's (romcsn, gpio21(mcsn),gpio7- 4(cs5,2n), cs1n,cs0n GPIO[5] (CS3n), GPIO[6] (CS4n) ...
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... MFC2000 Multifunctional Peripheral Controller 2000 (internal clock) A[11:0] upper address Ext. CS GPIO[5] (CS3n), GPIO[6] (CS4n) D[15:0] (read) D[15:0] (write) Figure 4-11. System Bus Timing Zero-Wait-State Read/Write 4-42 zero wait state lower address CSD t t R0D ...
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Hardware Description (internal clock) A[11: CSD AE[2] AE[3] AO[2] AO[ D[15:0] (read) Figure 4-12. System Bus ...
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... MFC2000 Multifunctional Peripheral Controller 2000 3 wait states (w= (internal clock) A[11: CSD AE[2] AE[3] AO[2] AO[ D[15:0] (write) t DOS Figure 4-13. System Bus Timing 2-Way Interleave Write Timing ( 4-44 3 wait states 3 wait states t iAD ...
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Hardware Description Table 4-8. Read/Write with Wait States Timing Parameters Parameter Address delay time Chip select delay time Read delay time for the normal case and delay-on) Write delay time (the normal case, delay-on, and early-off) CS[4:3] delay time (gated ...
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... System Interrupt (irqsys) Software Interrupt (irqsw) SSIF Interrupt (irqssif) DMA ch.5 Interrupt (irqdma5) SmartDAA IF Interrupt (irqsdaa) Timer Interrupt 2 (irqtimer2) USB Interrupt (irqusb) 4-46 Table 4-9. MFC2000 Interrupt and Reset Signals Description External Source MIRQn PRTIRQn BATRSTn RESETn IRQ11 IRQ13 IRQ16 Conexant Hardware Description Internal ...
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Hardware Description This section describes the three methods of interrupting the CPU program flow, which are: Reset Interrupts for the normal functions (IRQs) Interrupt for the development system (through the IRQ16 pin)/Power Down (through the Power Down block) The reset ...
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... MFC2000 Multifunctional Peripheral Controller 2000 External Interrupts The optional IRQ13 and IRQ11 external interrupt requests share pins with GPIO9 and GPIO8, respectively, and these interrupts are enabled by setting the corresponding bits in the IRQ ENABLE registers to 1. These interrupt enable bits must be set to 0 when using GPIO[9:8] as GPIO to prevent these pins from causing interrupts. ...
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Hardware Description 4.4.2 Register Description 4.4.2.1 IRQ/FIQ Event1 Register Address: Bit 15 Bit 14 IRQFIQEvent1 IRQ15 IRQ14 irqsopif irqt4 Event Event Status Status 0x01FF8021 Address: Bit 7 Bit 6 IRQFIQEvent1 IRQ7 irqbrc IRQ6 irqdma2 Event Status Event Status 0x01FF8020 Bit ...
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... MFC2000 Multifunctional Peripheral Controller 2000 4.4.2.2 IRQ/FIQ Event2 Register Address: Bit 15 Bit 14 IRQFIQEvent2 (Not (Not Used) Used) 0x01FF8023 Address: Bit 7 Bit 6 IRQFIQEvent2 (Not IRQ22 Used) irqusb Event Status 0x01FF8022 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 4.4.2.3 IRQ Enable1 Register Address: Bit 15 Bit 14 ...
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Hardware Description 4.4.2.4 IRQ Enable2 Register Address: Bit 15 Bit 14 IRQEnable2 (Not Used) (Not Used) 0x01FF8027 Address: Bit 7 Bit 6 IRQEnable2 (Not Used) Enable IRQ22 irqusb 0x01FF8026 Bit 3 – 0: 4.4.2.5 FIQ Enable1 Register Address: Bit 15 ...
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... MFC2000 Multifunctional Peripheral Controller 2000 4.4.2.7 External Interrupt Configuration Register Address: Bit 7 Bit 6 EIRQConfig irq16edge irq13edge 0x01FF802C Bit 7 – 4: Bit 3 – 0: 4.4.2.8 External Interrupt Clear Register Address: Bit 7 Bit 6 EIRQClear (Not Used) (Not Used) 0x01FF802D Bit 3 – 0: Bit 5 – 4: 4.4.2.9 Timer1 Register Address: Bit 15 ...
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Hardware Description 4.4.2.10 Timer2 Register Address: Bit 15 Bit 14 Timer2 0x01FF8031 Address: Bit 7 Bit 6 Timer1 0x01FF8030 Bit 15 – 0: The resolution of the timer1 and timer2 is dependent on SIUCLK and can be calculated as follows: ...
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... MFC2000 Multifunctional Peripheral Controller 2000 4.4.3 Timing SIUCLK (internal) MIRQn PRTIRQn(IRQ2) or GPIO[8](IRQ11) or GPIO[9](IRQ13) or IRQ16(SYSIRQ) Note: The MFP2000 chip resynchronizes MIRQn, IRQ16 signals internally. There are no setup time and hold time requirements for MIRQn, GPIO[8], GPIO[9], MIRQn, and IRQ16 PRTIRQn, external interrupts PRTIRQn, GPIO[8], GPIO[9], and IRQ16 can also be programmed as edge triggered interrupts. In this case, the interrupt signals are implemented as clock into flip-flops with D-input either tied to high or low ...
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Hardware Description If a burst of data is sent to the DRAM, the DRAM Controller will run in page mode once the initial access is completed. The maximum burst length is limited to 8 halfwords (i.e., the maximum burst length ...
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... MFC2000 Multifunctional Peripheral Controller 2000 4.5.1.2 Non-Interleaved DRAM Accesses Non-interleaved DRAM accesses are available for 8-bit or 16-bit data bus. Byte access is available for both 8-bit and 16-bit data bus and 16-bit halfword access is available for 16-bit data bus. DRAM early-write mode, normal read mode and page mode are supported. Read-modify-write is not supported. Note: 16-bit DRAMs must have upper and lower CAS’ ...
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Hardware Description Address Select Option 000 Multiplexing Register Physical Address ROW A[13] A[22] A[12] A[21] A[11] A[20] A[10] A[19] A[9] A[18] A[8] A[17] A[7] A[16] A[6] A[15] A[5] A[14] A[4] A[13] A[3] A[12] A[2] A[11] A[1] A[10] A[0] A[9] Address ...
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... MFC2000 Multifunctional Peripheral Controller 2000 Memory Size Address Multiplex Setting 8-bit 256K x 8 000 000 256K x 16 DRAMs 000 000 --- --- 512K x 8 000 000 001 001 DRAMs 001 001 --- --- 010 010 DRAMs 001 111 --- --- 16M x 8 011 ...
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Hardware Description 4.5.1.5 Power Down Mode When the ASIC is powered down, the DRAMs cannot be accessed. Only DRAM refresh will continue on battery power (VDRAM). Refresh timing is generated from a one shot and an internal gate delay circuit ...
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... MFC2000 Multifunctional Peripheral Controller 2000 ASIC Figure 4-17 gives an example of how each bank of DRAMs might be setup for non-battery back-up DRAM system. In this example, Bank 0 is setup for an 8-bit non-interleaved memory bank and Bank 1 is setup with a 16- bit 2-way interleaved DRAM bank. ...
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Hardware Description 4.5.2 Register Description Address Bit 15 Bit 14 DRAM Control Bank 1 Address Multiplexing Register (DRAMCtrl1) $01FF8821 Address Bit 7 Bit 6 DRAM Control Bank 0 Address Multiplexing Register (DRAMCtrl1) $01FF8820 Register Description: The DRAM Control register is ...
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... MFC2000 Multifunctional Peripheral Controller 2000 Bit 4: Bank 0 Increase RAS Cycle Time Bit 3: Bank 0 2-cycle RAS Precharge Bit 2: Bank 0 1-cycle RAH Bits 1-0: Bank 0 Speed Control Address Bit 15 Bit 14 Backup (Not Used) (Not Used) Configuration Register (BackupConfig) $01FF8099 Address Bit 7 Bit 6 Backup DRAM Backup Time ...
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Hardware Description Note: Power_down1 and power_down2 are output signals from the power-down detection circuit 1 and 2. Bit12: Betrstn Detected Bit11: Bit10: SRAM Chip Select Enable Bit 9: Bank 1 Interface Size Bit 8: Bank 0 Interface Size Bits 7-6: ...
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... MFC2000 Multifunctional Peripheral Controller 2000 Refresh Oscillator Speed: Speed: (bit 5) (bit Bits 3: Bank 1 Enable Bit 2: Bank 0 Enable Bit 1: Bank 1 Interleave Enable Bit 0: Bank 0 Interleave Enable 4-64 Refresh Speed: normal RTC crystal frequency = 32.768 kHz, Refresh clock = the crystal frequency = 32.768 kHz, The refresh cycle time = 15 ...
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Hardware Description 4.5.3 Brief Timing No matter which mode you use and which address you access, the DRAM access timing is lined up with the octal halfword boundary. SIUCLK RASn[0] CASEn[ ...
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... MFC2000 Multifunctional Peripheral Controller 2000 The timing diagram illustrates a 16-bit memory data bus, a burst of word transfers (2 words) from the ARM7 for full clock width CASn and PG = one wait state (non-interleaved). It also illustrates that the octal halfword boundary doesn’t occur in the middle of the burst of word transfers. ...
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Hardware Description This example illustrates a read of two-way interleaved memory with halfword bursts of data (6 halfwords). It also illustrates that the octal halfword boundary doesn’t occur in the middle of the burst of halfword transfers. It assumes external ...
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... MFC2000 Multifunctional Peripheral Controller 2000 The timing diagram illustrates two-way interleaved DRAM write. This configuration assumes that the data bus is available to the DRAM with enough setup time to the CASn falling edge. In addition, this configuration has a 2- cycle wide RASn and allows one cycle after the falling edge of RASn before the row/column address mux. ...
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Hardware Description RASN[1:0] CASEN[1:0] CASON[1:0] DOEN[1: Figure 4-26. DRAM Timing for 2-way Interleave Write S I ...
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... MFC2000 Multifunctional Peripheral Controller 2000 RASN[1:0] CASEN[1:0], CASON[1: RASN[1:0] CASEN[1:0 4- Figure 4-28. DRAM Refresh Timing t RRAS t t CRD CRD t R CAS Figure 4-29. DRAM Battery Refresh Timing ...
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Hardware Description Parameter RASN delay CASN delay (0 wait state) CASN delay CASN address setup (0 wait state) (10Mhz) CASN address setup (30 MHz) RASN address hold 1 RASN address hold 2 DWRN delay OE delay CASN pulse width RASN ...
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... MFC2000 Multifunctional Peripheral Controller 2000 4.6 Flash Memory Controller The Flash memory controller provides an interface for both NAND and NOR type flash memory devices two NOR type Flash memory devices or two NAND type devices can be connected to the ASIC. FCS0n and FCS1n pins are the flash memory control pins. FWRn and FRDn are the flash read and write signals for NAND type devices ...
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Hardware Description 4.6.2.3 NAND-Type Flash Memory NAND type devices can only be used for data memory. NAND type flash devices have no address bus. Command, address and data are passed through the external data bus. Accesses are accomplished by first ...
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... MFC2000 Multifunctional Peripheral Controller 2000 4.6.3 Timing All accesses can be performed from zero to seven wait states. The number of wait states is programmable in the FlashCtrl register. During write operations, if one to seven wait states is used, the EarlyOff option must be set in the FlashCtrl register. The EarlyOff option is ignored with zero wait state. ...
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Hardware Description FCSN[1: (GPIO (GPIO) GPIO[ GPIO[1] (FRDN) D[15:0] (read) D[15:0] (write) Figure 4-31. NAND-Type ...
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... MFC2000 Multifunctional Peripheral Controller 2000 4.6.4 Register Description Address: Bit 7 Bit 6 NANDFlash (Not Used) (NANDFLSH) 00C00001h Address: Bit 7 Bit 6 NANDFlash Reading this location activates the FRDn signal. Writing to this location activates the FWRn signal. No physical register exists for this location. (NANDFLSH) 00C00000h Register description: This register is the IO address space for the NAND type flash ...
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Hardware Description Addressing Modes All of the DMA Channels increment by 2 after each access. The external channels 1 and 2, can be set to increment by 1 for byte wide peripherals. The count enable register allows the user to ...
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... MFC2000 Multifunctional Peripheral Controller 2000 Each of the DMA channels, its function, and its characteristics are provided in Table 4-17. Table 4-17. DMA Channel Functions and Characteristics DMA Channel Function 1 0 USB data to/from memory for PC print, PC fax TX, PC Fax RX, PC scan 1 External DMA access only. ...
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Hardware Description 4.7.2 DMA Operation and Timing The DMA controller arbitrates DMA requests from all sources (internal and external), and then acknowledges the request of the source with the highest priority at the start of the next bus cycle. After ...
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... DMA requesting device, the external DMA requesting device will get the second DMAACK signal for the next single data transfer, when system bus is ready. The MFC2000 chip continues to perform single DMA access as long as the DMAREQ is kept active by the external DMA requesting device. ...
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Hardware Description Ext. address bus Ext. data bus W R ...
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... MFC2000 Multifunctional Peripheral Controller 2000 4.7.4 USB Block Diagrams Below is a block diagram depicting the four USB logical channels. Each logical channel shows the double buffering of the address and block registers. The right side of the diagram shows the common counters for the block and address ...
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Hardware Description 4.7.5 DMA Controller Registers USB Logical Channel Assignments DMA Channels 1 12 addressing is controlled by the following registers. Note: If the DMA address counter points to an invalid location, invalid data is read or written Address: Bit ...
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... MFC2000 Multifunctional Peripheral Controller 2000 Address: Bit 15 Bit 14 chcsh[10:0] DMA Hi Counter Not Used Not Used (DMAiCnthi) Address:chcsh[10: Bit 7 Bit 6 0] DMA Hi Counter DMA0-12 DMA0-12 Addr. (DMAiCnthi) Addr. Bit 23 Bit 22 DMA Channel 0 12 Upper Address Counter Value 4-84 Bit 13 Bit 12 Bit 11 Not Used ...
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Hardware Description Address:ch0cscntl Bit 15 Bit 14 DMA 0 Configuration Channel Channel Enable Enable (DMA0config) LC3 LC2 $xx81B1 Address:ch0cscntl Bit 7 Bit 6 DMA 0 Configuration Not Used Not Used (DMA0config) $xx81B0 Bit 15-12: Logical Channel Enable Bit 11-8: Read/Write ...
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... MFC2000 Multifunctional Peripheral Controller 2000 Address: Bit 15 Bit 14 chcsh[10:0] DMAUSB Hi Counter Not Used Not Used (DMAiCnthi) Address:chcsh[10: Bit 7 Bit 6 0] DMAUSB Hi Counter DMA0-10 DMA0-10 Addr. (DMAiCnthi) Addr. Bit 23 Bit 22 DMAUSB Channel 0-3 Upper Address Counter Value. Address will only count by 2. Reading this register will return the active Address value when the last USBACK occurred. ...
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Hardware Description Address:ch4csbs Bit 15 Bit 14 DMAUSB Transfer USB Channel Stop At Block Size Reg. Block Enable = 1 (DMAUSBBlockSize ) Address:ch4csbs Bit 7 Bit 6 DMAUSBTransfer Low Byte Value for USB Memory Block Size Counter Block Size Reg. ...
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... MFC2000 Multifunctional Peripheral Controller 2000 Address:ch1cscntl Bit 15 Bit 14 DMA 1 Configuration DMAACK1 Not Used (DMA0config) Delay-off $xx8183 0=normal 1=delay ½ SIUCLK cycle Address:ch1cscntl Bit 7 Bit 6 DMA 1 Configuration Read = 1 Enable (DMA0config) Write = disable $xx8182 1 = enable Bit 0: Bit 6: Bit 7: Bit 15: Address:ch2cscnt Bit 15 Bit 14 ...
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Hardware Description Bit 8: Bit 7: Bit 6: Bit 5: Bit 4-0: Note: Requests to this channel are delayed by two clocks for synchronization. Address:ch2csbs Bit 15 Bit 14 DMA 2 Transfer Channel 2 Not Used Block Size Reg. Enable ...
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... MFC2000 Multifunctional Peripheral Controller 2000 Address:ch2csbbs Bit 15 Bit 14 DMA Ch2 Buffered Ch2 Not Used Transfer Block Size Enable = 1 Reg. (DMA2BfBlockSize) $xx81B7 Address:ch2csbbs Bit 7 Bit 6 DMA Ch2 Buffered Low Byte Value for the External DMA Block Size Counter Transfer Block Size Low Byte Reg. ...
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Hardware Description Address: chcsbh[2] Bit 15 Bit 14 DMA Ch2 Buffered Not Used Not Used Hi Counter (DMA2Cntbhi) $xx818F Address:chcsbh[2] Bit 7 Bit 6 DMA Ch2 Buffered DMAB2 DMAB2 Hi Counter Addr. Addr. (DMA2Cntbhi) Bit 23 Bit 22 $xx818E DMA ...
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... MFC2000 Multifunctional Peripheral Controller 2000 Address:ch9csbs Bit 15 Bit 14 DMA9 Transfer Channel 9 Not Used Block Size Reg. Enable = 1 (DMA9BlockSize) $xx81BF Address:ch9csbs Bit 7 Bit 6 DMA9Transfer Low Byte Value for the Bi-level resolution conversion logic Block Size Counter Block Size Reg. (DMA9BlockSize) $xx81BE DMA Channel 9 Block Size Limit Counter ...
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Hardware Description Address:ch10csbs Bit 15 Bit 14 DMA10 Transfer Channel 10 Not Used Block Size Reg. Enable = 1 (DMA10BlockSize) $xx81C1 Address:ch10csbs Bit 7 Bit 6 DMA10Transfer Low Byte Value for the PIO to Memory Block Size Counter Block Size ...
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... MFC2000 Multifunctional Peripheral Controller 2000 Address: Bit 15 Bit 14 cscontenb DMA Count Enable Not Used Not Used (DMACntConfig) $xx81C5 Address:cscontenb Bit 7 Bit 6 DMA Count Enable DMA 9 DMA 8 (DMACntConfig) Count Count $xx81C4 Enable Enable DMA Address Count Enable Control. The Count Enable control bit allows the user to enable address Count after each DMA access ...
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Hardware Description 100723A MFC 2000 Multifunctional Peripheral Controller 2000 This page is intentionally blank Conexant 4-95 ...
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...
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... RESET Logic/Battery Backup/Watch Dog Timer 5.1 Reset Logic/Battery Backup The MFC2000 has two power resets, Battery Power Reset and Prime Power Reset. The Battery Power Reset is the primary reset used to initialize battery-powered logic when battery power is first applied. Prime Power Reset initializes all non-battery powered logic whenever system power is applied. A third reset is generated by the watchdog timer or by the RESETn pin ...
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... MFC2000 Multifunctional Peripheral Controller 2000 Prime Power Battery Power Divider Pwrdwn pwrdwn_padn select logic ext_pdsel SYSIRQ for power down routine 5-2 Fax Timing Sync Block SIUCLK Power up Delay 2 Retime to local_clk ...
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... Battery Power Reset is generated when BATRSTn (as shown at lower left in Figure 5-1) is driven low, and initializes the MFC2000 when battery power is first applied, as well as forcing a Prime Power Reset present. As long as battery power is maintained, there is no need to reactivate this reset. If the system design does not utilize the MFC2000's battery power features, this reset should be tied to PWRDWNn and be activated upon system power initialization ...
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... XOUT rising edge Power Off V DD power off occurs when PWRDWNn is driven low while normal operating level MFC2000 battery backed up feature, PWRDWNn has been designed to work with an early warning power loss detector. This allows the firmware to backup sensitive variables, and the MFC2000 to protect nonvolatile data from erroneous logic operations while prime power transitions through low voltage levels (i.e., < ...
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Hardware Description 5.1.3 External Reset (RESETn) and Watchdog Reset A driver on the AMPFC's RESETn pin provides a reset signal to external devices whenever the internal Battrtc_RESn or watchdog reset is active (low). This pin also includes an input driver ...
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... Connect to VGG pins on the MFC2000 chip to supply +5v prime power to all +5v tolerant pads in the MFC2000 chip. +3V battery power signal Connect to the VBAT pin on the MFC2000 chip to supply battery power to the battery backup RTC in the MFC2000 chip and external SRAM. Connect to the VDRAM pin on the MFC2000 chip to supply battery power to the battery backup DRAM refresh logic in the MFC2000 chip and external DRAM ...
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Hardware Description 5.1.6 Register Description Battery Backup and Prime Power Reset Registers Name/Address Bit 15 Bit 14 Backup (Not Used) (Not Used) Internal Configuration Register (BackupConfig) $01FF8099 Name/Address Bit 7 Bit 6 Backup DRAM Backup Time Configuration ...
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... MFC2000 Multifunctional Peripheral Controller 2000 Bit 8: Bank 0 Interface Size Bits 7-6: DRAM Battery Backup Time Bit 6 Bit Bit 5-4: DRAM Refresh Rate Refresh Oscillator Speed: Speed: (bit 5) (bit Bits 3: Bank 1 Enable 5-8 This register defines whether the databus to the bank 0 DRAMs is 8 bits wide or 16 bits wide ...
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Hardware Description Bit 2: Bank 0 Enable Bit 1: Bank 1 Interleave Enable Bit 0: Bank 0 Interleave Enable Address Bit 15 Bit 14 Lock Enable A Dummy write to the Lock Enable register will enable the battery/prime power lockout ...
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... The power down detection circuit was only external for the MFC1000 chip. The PWRDWNn input signal to MFC1000 is the output of the external power down detection circuit. The MFC2000 has two internal power down detectors. The PWRDWNn is configurable either from internal power down detectors or from external power down detector ...
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Hardware Description V off V hys Note: The output voltage to represent logic 0 must be guaranteed ADGA (typically ADGA = GND = 0V). The input resistance to the voltage detector is specified as follows ...
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... MFC2000 Multifunctional Peripheral Controller 2000 4. As soon as the Watchdog Timer is enabled, the Time-out Down Counter begins counting. The Time-out Down Counter is decremented based pulse which is derived from (125 µs prescaler period /8); the count occurs on the rising edge of SIUCLK. After the Time-out Down Counter reaches 'zero', the (internal) watchdog reset signal becomes active at the next 1 ms pulse ...
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Hardware Description SIUCLK T1msCI Counter Enable WDRES 5.2.1 Watchdog Timer Registers Address: Bit 15 Watchdog Enable (Not Used) Retrig. (WatchdogEnRetrigger) 01FF8041 Address: Bit 7 Watchdog Enable Writing 0Fh followed by F0h to this register after setting the Watchdog Interval register ...
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... MFC2000 Multifunctional Peripheral Controller 2000 Address: Bit 15 Bit 14 Watchdog Interval (Not Used) (WatchdogInterval) 01FF8043 Address: Bit 7 Bit 6 Watchdog Interval Watchdog Interval (n = 0-255) (WatchdogInterval) (n*1ms) 01FF8042 Once enabled, the Watchdog Timer can only be disabled by reset. On reset, the Watchdog Timer is disabled until it is enabled by writing to the WatchdogInterval register followed by writing $0F and $F0 to the WatchdogEnRetrigger register. The basic Watchdog time-out unit (1 ms) is based on the internal 125 µ ...
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Hardware Description 100723A MFC 2000 Multifunctional Peripheral Controller 2000 This page is intentionally blank. Conexant 5-15 ...
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...
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... The MFC2000 can only operate in one mode at a time. The mode selection is made during the reset through clock configuration pins (CLKConfig[2:0]). The input reference frequency is 28.224 MHz, which is generated by a crystal oscillator pad. 28.224MHz is also used for the internal P80 modem DSP. ...
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... MFC2000 Multifunctional Peripheral Controller 2000 6.2 Fax Timing Logic The fax timing logic block generates all of the time bases needed by the MFC2000. The fax timing logic block diagram is provided in Figure 6-1. A= [IHSCLK period]+ from Divide SIUCLK [ICLK period]+ from ...
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... Hardware Description 6.3 MFC2000 Timing Chain The MFC2000 timing chain is illustrated in Figure 6-2. SIUCLK Divide [IHSCLK Period [ICLK Period Divide by B Divide by 8 ICLK (AUXCLK) on/off Control Divide [ScanDotScaler] +1 ONEMSCLK(from RTC) 100723A 125us synchronized to SIUCLK Divide [125us Prescaler [MSINT Period ...
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... MFC2000 Multifunctional Peripheral Controller 2000 6.4 Scan Control Timing In this example, the scan motor has the constant speed. The scan motor stepping is synchronized to the MSINT. The scan IRQ is used to disable motor stepping when we want to finish scanning. If the delay time for the scan motor is long enough, the last step will occur after the scan IRQ ...
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Hardware Description 6.5 Fax Timing Registers Address: Bit 15 Bit 14 125 uS Prescaler (Not Used) (125usPrescaler) 01FF8881 Address: Bit 7 125 uS Prescaler n (8 bits) as applied in the equation: (n+1)*(ICLK period *8) (125usPrescaler) 01FF8880 Address: Bit 15 ...
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... MFC2000 Multifunctional Peripheral Controller 2000 Address: Bit 15 Bit 14 Interrupt Clear (Not Used) (Not Used) (IntClear) 01FF8887 Address: Bit 7 Interrupt Clear (Not Used) (Not Used) (IntClear) 01FF8886 (W) 6-6 Bit 13 Bit 12 (Not Used) (Not Used) (Not Used) Bit 6 Bit 5 Bit 4 (Not Used) (Not Used) ...
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... Figure 7-1. Video/Scanner Controller Block Diagram 100723A Video/Scan Controller Two-wire Serial Interface Video Decoder Interface LEDCtrl sensorCtrl SIACtrl Scan Analog Frontend Conexant system Registers interface msintcy msint counter & irq generator vsc_irq vsc_adc_start vsc_adc_stop data and clock vsc_adc_drdy vsc_adc_dclk vsc_adc_data[7:0] MFC2000 7-1 ...
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... MFC2000 Multifunctional Peripheral Controller 2000 7.1 Scanner Controller The function of scanner controller can be divided into three areas: 1. Scanner sensor controller 2. Scanner light controller 3. Scan integrated analog controller Pins related to scanner and external ADC # Scanner related SC_START[0] SC_LEDCTRL[0] SC_LEDCTRL[1]/SC_START[1] SC_LEDCTRL[2]/SC_START[2] SC_CLK1/SC_CLK2A ...
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... LEDs) programmable clamping signal (mode, delay, width, length) programmable sampling location (mode, location) supports external 12-bit ADC with programmable latency and programmable data transfer position MFC2000 sc_led0 sc_st0 sc_led0st1 sc_led2st2 sc_clk12a ...
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... MFC2000 Multifunctional Peripheral Controller 2000 Name/Address Bit 15 Bit 14 Scan Control (Not Used) (Not Used) Status (ScanCtrlStat) $01FF8543 Name/Address Bit 7 Bit 6 Scan Control (Not Used) (Not Used) Status (ScanCtrlStat) $01FF8542 This register is read only. The value written in ScanCtrl register will be transferred to this register at the beginning of scan cycle. ...
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Hardware Description Bit 15-8 Shift Enable[7:0] Bit 2 VSC on EV bus EV_VD[5: Bit 1 ihsclk period Bit 0 VSC Mode Name/Address Bit 15 Bit 14 Scan Cycle (Not Used) (Not Used) (ScanCycle) $01FF8891 ...
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... MFC2000 Multifunctional Peripheral Controller 2000 Notes 1. Bits [4:0] of this register specify the number of MSINTs (1-32) per Scan Cycle. Total Scan Cycle Period = [MSINT period * (ScanCycle register value + 1)]. 2. The transition from maximum count to 0 determines the start of a scan cycle. 3. Reading bits [4:0] of this register returns the current scan cycle MSINT count. ...
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Hardware Description Name/Address Bit 15 Bit 14 Scan Length (Not Used) (Not Used) (Not Used) (ScanLength) $01FF8897 Name/Address Bit 7 Bit 6 Scan Length (ScanLength) $01FF8896 Bits 12-0 ScanLength[12:0] Note: The internal pixel counter is 14-bit wide. The extra bit ...
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... MFC2000 Multifunctional Peripheral Controller 2000 Bits 7-4 StartNeg (0-15) Bits 3-0 StartPos (0-15) Name/Address Bit 15 Bit 14 Start Config Guardband Guardband Enable for Enable for (StartConfig) scctrl[6] scctrl[5] $01FF889D Name/Address Bit 7 Bit 6 Start Config (in terms of pixel period) (StartConfig) $01FF889C Bit 15-13 Guardband Enable for scctrl[6:4] Bit 12-8 Guardband[4:0] ...
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Hardware Description Name/Address Bit 15 Bit 14 Clk2b Edges (Not Used) (Not Used) (Clk2bEdges) $01FF88A1 Name/Address Bit 7 Bit 6 Clk2b Edges Clk2bNeg Value (0-15) (Clk2bEdges) $01FF88A0 Bits 7-4 Clk2bNeg Bits 3-0 Clk2bPos Name/Address Bit 15 Bit 14 Clk2c Edges ...
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... MFC2000 Multifunctional Peripheral Controller 2000 Bits 15 Mode Bits 7-4 SampleNeg Bits 3-0 SamplePos Name/Address Bit 15 Bit 14 Clamp Control Clamp Internal Mode Clamp (ClampCtrl) Enable $01FF88A7 Name/Address Bit 7 Bit 6 Clamp Control (Not Used) (ClampCtrl) $01FF88A6 Bit 15 ClampMode (1 = line–based pixel–based) Bits 6-0 ClampLength[6:0] Note: Both internal and external clamp share the same control signals for ‘shift’ and ‘delay’. ...
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Hardware Description Bit 15 Clamp Position (only valid for line–based clamping) Bits 13-0 Clamp Delay[13:0] (only valid for line–based clamping) Note: If ClampPosition bit = 0 and a new scanline is started before the ClampDelay value has been satisfied, the ...
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... MFC2000 Multifunctional Peripheral Controller 2000 Name/Address Bit 15 Bit 14 Clk2d Control Select (Not Used) (Clk2dCtrl) $01FF88C5 Name/Address Bit 7 Bit 6 Clk2d Control (Clk2dCtrl) $01FF88C4 Bit 15 Select Bit 12 Shift Bit 11-10 Delay Bit 9 Invert Bit 8 Guardband Enable Bit 7-4 NegEdge position Bit 3-0 PosEdge position Name/Address Bit 15 ...
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Hardware Description Name/Address Bit 15 Bit 14 LEDCtrl[1] Edges Trailing edge position = (NegEdge[7:0] * 64) pixels before/after scan start delay (LED1Edges) 01FF88AF Bit 7 Bit 6 LEDCtrl[1] Edges Leading edge position = (PosEdge[7:0] * 64) pixels before/after scan start ...
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... MFC2000 Multifunctional Peripheral Controller 2000 Bits 10-8 clock divider[2:0] Bits 7-0 duty cycle[7:0] Note: In order to have a non-modulated signal, the duty cycle must be set to 0xFF. Name/Address Bit 15 Bit 14 LED1 PWM Config (Not Used) (Not Used) (LED1PWM) $01FF88B5 Name/Address Bit 7 Bit 6 LED1 PWM Config (LED1PWM) ...
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Hardware Description Bits 10-8 clock divider[2:0] Bits 7-0 duty cycle[7:0] Note: In order to have a non-modulated signal, the duty cycle must be set to 0xFF. Name/Address Bit 15 Bit 14 LEDCtrl Config (Not Used) (Not Used) (LEDConfig) $01FF88B9 Name/Address ...
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... MFC2000 Multifunctional Peripheral Controller 2000 In order to apply the content of this register to the analog die, the content must be sent serially by writing to the ‘ADCSerialCmd’ register. Please refer to the ‘ADCSerialCmd’ register description for more information. Bit 15 ADC enable Bit 12-8 OffsetSel[4:0] Bit 5 GPO on EV_VD[5] ...
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Hardware Description Bit 1-0 Transmit Mode[1:0] Prior to writing to this register, check the ‘Send Status’ bit, and make sure that this bit is clear. If this bit is set, then writing to this register will be ignored. If this ...
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... MFC2000 Multifunctional Peripheral Controller 2000 Bit 15-12 AdclkNeg Bit 11-8 AdclkPos Bit 7-4 Digital Data Capture Position Bit 3-0 Data Latency Important note on how to program adclk & adsample when an internal ADC is selected: 1. The location and the width of adsample must be established first according to the scanner requirement (the analog signal is being sampled while adsample = 1, and at the falling edge of adsample, the signal is stored into an internal capacitor ...
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Hardware Description 7.1.3 Timing msintcy scanenb write '1' to EnableScan bit in ScanConfig1 register current 0 cycle cycle_start start[0] enb write '1' to Start[0]enable bit in ScanCtrl register (write to ScanCtrl reg) start[0] enb_status (read from ScanCtrl Status reg) startposedge ...
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... MFC2000 Multifunctional Peripheral Controller 2000 firmware change the number of msint in a scancycle setup.scancycles scancycles_sync sccyc_nxt 1 sccyc_ctr 1 sccyc_count sccyc_reset setup.msintirqloc msintirqloc_sync scanirq_set scanirq_cur msintcy Scan Cycle buffer) Scan Cycle buffer) cycle_start Scan Cycle 2 (counter) 7- one msint period firmware change the location of msint irq ...
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Hardware Description ihsclk 0 dotscaler_ctr 2 dotperiod_ctr 99 pixaddr_ctr clk1 clk2a Note: The rising and falling edges timing of clk2a also applies to clk2b, clk2c, start, clamp, and adsample. 100723A scan ...
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... MFC2000 Multifunctional Peripheral Controller 2000 cycle_start write '1' LEDCtrl[0]enb (write to ScanCtrl reg) LEDCtrl[0]enb_status (read from ScanCtrl Status reg) LED0PWMClkDiv[2:0] LEDCtrl[0] (place = 0) ScanStartDelay LEDCtrl[1]enb (write to ScanCtrl reg) LEDCtrl[1]enb_status (read from ScanCtrl Status reg) LEDCtrl[1] (place = 0) LEDCtrl[2]enb (write to ScanCtrl reg) ...
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Hardware Description msint scCycCur[4:0] start pixeladr[13:0] 0 Hi- Z LEDCtrl[0] LED0pad_en = LED0pad_en = 1 (default value from reset) Notes: 1. MSInt_period = (msintPeriod + 1) * 125 us msintPeriod[5:0] is set in MSINTPeriod register (assuming ...
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... MFC2000 Multifunctional Peripheral Controller 2000 msintcy IRQ loc current 3 cycle scan_irq The scanner controller will issue adc_start, adc_drdy, and adc_stop as follows: 1 adc_dclk wide adc_start adc_drdy adc_stop External ADC timing summary National: ADC 12662 Vin S/H Data[11:0] 7- ScanCycle = 3 generated here because MSINT IRQ location = 3 & ...
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Hardware Description Analog: AD 9220 Vin min = Data[11: Linear: LTC 1412 Vin Data[11:0] 7.1.4 Firmware Operation In order to obtain the optimal digital data, the dynamic ...
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... MFC2000 Multifunctional Peripheral Controller 2000 ROHM Manufacturer IA3008 – ZE22 Part # CIS Type 300 dpi Resolution 2560 Pixels/line 9 ms/line Scan time (color) 1.8~4.5 ms/line Scan time (B/W) 1.5 MHz (max) Data Rate 25 – Main clock ‘H’ duty Timing ihsclk dotscaler_ctr dotperiod_ctr clk2a ...
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Hardware Description Register Name ScanConfig ScanDotControl StartConfig StartEdges ScanStartDelay Clk2aEdges Clk2bEdges Clk2cEdges ADCSampleCfg ADCConfig ClampCtrl ClampDelay ClampEdges LEDConfig LED0Edges LED1Edges LED2Edges ScanLength ScanCyles 100723A Table 7-1. Register setup for Rohm–IA3008–ZE22 Bits Name scctrl[6:0] invert scctrl[6:2] select Scan Dot Scaler[3:0] Scan ...
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... MFC2000 Multifunctional Peripheral Controller 2000 DYNA Manufacturer DL507–07UAH Part # CIS Type 300 dpi Resolution 2552 Pixels/line 7.5 ms/line Scan time (color) Scan time (B/W) 2.0 MHz (typ) Data Rate 25 % (typ) Main clock ‘H’ duty Timing ihsclk dotscaler_ctr dotperiod_ctr clk2a start[0] start[0] ...
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Hardware Description Register Name ScanConfig ScanDotControl StartConfig StartEdges ScanStartDelay Clk2aEdges Clk2bEdges Clk2cEdges ADCSampleCfg ADCConfig ClampCtrl ClampDelay ClampEdges LEDConfig LED0Edges LED1Edges LED2Edges ScanLength ScanCyles 100723A Table 7-2. Register setup for Dyna–DL507–07UAH Bits Name scctrl[6:0] invert scctrl[6:2] select Scan Dot Scaler[3:0] Scan ...
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... MFC2000 Multifunctional Peripheral Controller 2000 Mitsubishi Manufacturer GT3R216 Part # CIS Type 300 dpi Resolution 2552 Pixels/line 7.5 ms/line Scan time (color) 1.5 ms/line Scan time (B/W) 3 – 4 MHz Data Rate 20 – Main clock ‘H’ duty Timing: ihsclk dotscaler_ctr dotperiod_ctr clk2a start[0] start[0] delay of 1 pixel ...
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Hardware Description Register Name ScanConfig ScanDotControl StartConfig StartEdges ScanStartDelay Clk2aEdges Clk2bEdges Clk2cEdges ADCSampleCfg ADCConfig ClampCtrl ClampDelay ClampEdges LEDConfig LED0Edges LED1Edges LED2Edges ScanLength ScanCyles 100723A Table 7-3. Register setup for Mitsubishi-GT3R216 Bits Name scctrl[6:0] invert scctrl[6:2] select Scan Dot Scaler[3:0] Scan ...
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... MFC2000 Multifunctional Peripheral Controller 2000 TOSHIBA Manufacturer CIPS218MC300 Part # CIS pkg w/ CCD Type 300 dpi Resolution 2576 Pixels/line Scan time (color) Scan time (B/W) 0.1 – 2.5 MHz Data Rate 50 % Main clock ‘H’ duty Timing ihsclk dotscaler_ctr dotperiod_ctr clk2a clk2b clk2c clk2a ...
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Hardware Description Table 7-4. Register Setup for Toshiba–CIPS218MC300 Register Name ScanConfig ScanDotControl StartConfig StartEdges ScanStartDelay Clk2aEdges Clk2bEdges Clk2cEdges ADCSampleCfg ADCConfig ClampCtrl ClampDelay ClampEdges LEDConfig LED0Edges LED1Edges LED2Edges ScanLength ScanCyles 100723A MFC 2000 Multifunctional Peripheral Controller 2000 Bits Name scctrl[6:0] invert ...
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... MFC2000 Multifunctional Peripheral Controller 2000 NEC Manufacturer •PD3724 Part # CCD Type 300 dpi Resolution 2700 x 3 Pixels Scan time (color) Scan time (B/W) 3 MHz (max) Data Rate 50 % Main clock ‘H’ duty Timing ihsclk dotscaler_ctr dotperiod_ctr clk1 inv( clk1 ) clk2a clk1 ...
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Hardware Description Register Name ScanConfig ScanDotControl StartConfig StartEdges ScanStartDelay Clk2aEdges Clk2bEdges Clk2cEdges ADCSampleCfg ADCConfig ClampCtrl ClampDelay ClampEdges LEDConfig LED0Edges LED1Edges LED2Edges ScanLength ScanCyles 100723A Table 7-5. Register Setup for NEC – PD3724 Bits Name scctrl[6:0] invert scctrl[6:2] select Scan Dot ...
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... MFC2000 Multifunctional Peripheral Controller 2000 NEC Manufacturer •PD3794 Part # CCD Type 300 dpi Resolution 2700 x 3 Pixels Scan time (color) Scan time (B/W) 4 MHz (max) Data Rate Main clock ‘H’ duty Timing ihsclk dotscaler_ctr dotperiod_ctr clk2a clk2b clk2c clk1 start[0] ...
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Hardware Description Register Name ScanConfig ScanDotControl StartConfig StartEdges ScanStartDelay Clk2aEdges Clk2bEdges Clk2cEdges ADCSampleCfg ADCConfig ClampCtrl ClampDelay ClampEdges LEDConfig LED0Edges LED1Edges LED2Edges ScanLength ScanCyles 100723A Table 7-6. Register setup for NEC – PD3794 Bits Name scctrl[6:0] invert scctrl[6:2] select Scan Dot ...
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... MFC2000 Multifunctional Peripheral Controller 2000 SONY Manufacturer ILX516K Part # CCD Type 400 dpi Resolution 3648 x 3 Pixels Scan time (color) Scan time (B/W) 5 MHz (max) Data Rate 50 % Main clock ‘H’ duty Timing ihsclk dotscaler_ctr dotperiod_ctr clk2a clk2b clk2c PixelTime = 200 ns (min) ...
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Hardware Description Register Name ScanConfig ScanDotControl StartConfig StartEdges ScanStartDelay Clk2aEdges Clk2bEdges Clk2cEdges ADCSampleCfg ADCConfig ClampCtrl ClampDelay ClampEdges LEDConfig LED0Edges LED1Edges LED2Edges ScanLength ScanCyles 100723A Table 7-7. Register Setup for SONY – ILX516K Bits Name scctrl[6:0] invert scctrl[6:2] select Scan Dot ...
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... MFC2000 Multifunctional Peripheral Controller 2000 External circuit required for SONY–ILX516K interface: SONY - ILX516K Figure 7-21. External circuit required for SONY–ILX516K interface LED timing for SONY–ILX516K start[0] LEDCtrl[0] expsoure time as required by RED sensor LEDCtrl[2:1] Used as selectors for analog MUX 7-40 + ...
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Hardware Description 7.2 Serial Programming Interface The serial programming interface is a two-wire bidirectional serial bus, which provides a simple and efficient way for data exchange between devices. Main Features: Only two bus lines are required; a serial interface data ...
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... MFC2000 Multifunctional Peripheral Controller 2000 Bus Protocol Slave Address b7 SID SIC Slave Address Start Figure 7-25. Serial Programming Interface, Timing Diagram 7-42 Data transfer acknowledge) 7-bit 1-bit 8-bit Data Figure 7-24. Bus Protocol R/W A Conexant Hardware Description (n bytes + 8-bit ...
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Hardware Description START condition STOP condition Bit transfer Getting ACK Giving ACK 100723A SID SIC SID SIC SID SIC SID 'z' master LSB 'z' slave '0' wire 'H' '0' LSB SIC end of WAC write SID 'z' master '0' 'z' ...
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... MFC2000 Multifunctional Peripheral Controller 2000 Clock Stretching Slave can add wait state as needed by stretching the low period of the clock. This will slow down the bus as shown below. Master's SIC Slave's SIC 7.2.2 Register Description Name/Address Bit 15 Bit 14 SPI Control (Not Used) (Not Used) ...
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Hardware Description Bit 2 WAC – Write Acknowledge Bit 1 SID – Serial Input Data Bit 0 SIC – Serial Input Clock Note: In normal case, only one of bit [7:2] should be set. However, if for some reasons, more ...
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... MFC2000 Multifunctional Peripheral Controller 2000 Name/Address Bit 15 Bit 14 SPI Status (Not Used) (Not Used) (SPIStat) $01FF854D Name/Address Bit 7 Bit 6 SPI Status (Not Used) (Not Used) (SPIStat) $01FF854C Bit 8 Received ACK Bit 1 SID – Serial Input Data line Bit 0 SIC – Serial Input Clock line ...
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Hardware Description Note: The freqencies specified above are based on iclk = 10MHz. Name/Address Bit 15 Bit 14 SPI Data Read Read Data[6] (SPIData) Data[7] (Read only) $01FF88C3 (Read only) Name/Address Bit 7 Bit 6 SPI Data Write Write Data[6] ...
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... MFC2000 Multifunctional Peripheral Controller 2000 7.2.3 Firmware Operation Initialization: select the desired frequency for SIC by writing the appropriate value to “SPI_Config” register Transmission: write to 'SPI_Data' reg 7- write 0x0020 to 'SPI_Ctrl' reg receive & clear spi_irq write to 'SPI_Data' reg receive & clear spi_irq write 0x0004 to 'SPI_Ctrl' reg receive & ...
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Hardware Description Reception: write 0x0020 to 'SPI_Ctrl' reg receive & clear spi irq receive & clear spi irq write 0x0004 to 'SPI_Ctrl' reg receive & clear spi irq write 0x0040 to 'SPI_Ctrl' reg receive & clear spi irq write 0x0080 ...
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... MFC2000 Multifunctional Peripheral Controller 2000 7.3 Video Controller Main features: Capture a frame from an external video decoder device Support ITU–R BT.656 or VESA Video Interface Port (VIP) format of YCrCb 4:2:2 Store captured frame into memory in a non-interlace format Software interrupt at the end of a frame capture ITU– ...
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... Name/Address Bit 7 Bit 6 Video Capture (Not Used) (Not Used) Control (VidCaptureCtrl) $01FF8548 Bit 8 Video Error Bit 0 Start Capture 100723A MFC2000 EV_CLK clk EV_VD[7:0] /EADC_D[11:4] Bit 13 Bit 12 Bit 11 (Not Used) (Not Used) (Not Used) Bit 5 Bit 4 Bit 3 (Not Used) (Not Used) ...
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... MFC2000 Multifunctional Peripheral Controller 2000 Name/Address Bit 15 Bit 14 Video Line Config (Not Used) (Not Used) (VidLineCfg) $01FF88C7 Name/Address Bit 7 Bit 6 Video Line Config LineSize[7] LineSize[6] (VidLineCfg) $01FF88C6 Bit 10-1 LineSize[10:1] Note: The jump or skip parameter in DMA setting must be at least 1 halfword bigger than the “ ...