BT8110EPJ Conexant Systems, Inc., BT8110EPJ Datasheet
BT8110EPJ
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BT8110EPJ Summary of contents
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Bt8110/8110B High-Capacity ADPCM Processor This specification describes the Bt8110 and Bt8110B multichannel ADPCM processor CMOS integrated circuits that implement Adaptive Differential Pulse-Code Modulation (ADPCM) encoding and decoding. The fixed-rate coding algorithms include those specified in ANSI Standard T1.303-1989. These algorithms ...
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... Ordering Information Model Number Bt8110EPJ Bt8110EPJB Revision History Revision Level A Advanced B C © 1996, 2000 Conexant Systems, Inc. All Rights Reserved. Information in this document is provided in connection with Conexant Systems, Inc. ("Conexant") products. These materials are provided by Conexant as a service to its customers and may be used for informational purposes only. ...
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Table of Contents List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Electrical and Mechanical Specifications 4.1 Microprocessor Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Bt8110/8110B High-Capacity ADPCM Processor List of Figures Figure 1-1. Bt8110 Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures vi High-Capacity ADPCM Processor Conexant Bt8110/8110B 100060C ...
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Bt8110/8110B High-Capacity ADPCM Processor List of Tables Table 1-1. ADPCM Operational Modes ...
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List of Tables viii High-Capacity ADPCM Processor Conexant Bt8110/8110B 100060C ...
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Product Description The Adaptive Differential Pulse Code Modulation (ADPCM) algorithm is a transcoding operation which consists of encoding 64 kbit/s Pulse Code Modulation (PCM) to 16, 24, 32 kbit/s ADPCM and decoding from ADPCM to 64 kbit/s ...
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Product Description 1.1 Channel Capacity and Configuration Modes 1.1 Channel Capacity and Configuration Modes There are four configurations for the operational mode of the Bt8110/8110B (see Table bits ([MODE[2:0]) and the enable framer bit [EN_FRMR] in the Mode Control ...
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Bt8110/8110B High-Capacity ADPCM Processor 1.1.2 Embedded Coding The Bt8110/8110B has the capability to provide embedded coding according to ANSI Standard T1.310-1991 and ITU-T Recommendation G.727. This coding technique allows the encoding to be performed with 5 bits of encoding information, ...
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Product Description 1.2 Pin Descriptions 1.2 Pin Descriptions The Bt8110 and Bt8110B are packaged as 68-pin Plastic Leaded Chip Carriers (PLCCs). respectively. Pin assignments are listed in numerical order in Bt8110, and in partitioned logic diagrams for Bt8110 and ...
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Bt8110/8110B High-Capacity ADPCM Processor Table 1-2. Bt8110 Pin Descriptions Pin ...
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Product Description 1.2 Pin Descriptions Figure 1-2. Bt8110 Logic Diagram Clock In I Sync In I Serial Input I Reset I Parallel Signal Enable I (MSB) Parallel Signal Parallel Signal Parallel Signal In ...
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Bt8110/8110B High-Capacity ADPCM Processor Figure 1-3. Bt8110B Pinout Diagram 100060C GND 10 AD[0] 11 AD[1] 12 AD[2] 13 SERIAL_IN 14 CLOCK 15 SERIAL_OUT 16 Bt8110B VCC 17 ADPCM GND 18 Processor AD[3] 19 RESET 20 SYNC MICREN ...
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Product Description 1.2 Pin Descriptions Table 1-3. Bt8110B Pin Descriptions Pin ...
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Bt8110/8110B High-Capacity ADPCM Processor Figure 1-4. Bt8110B Logic Diagram 15 Clock Sync Serial Input I 20 Reset I Parallel Signal Enable I (MSB) Parallel Signal Parallel Signal Parallel ...
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Product Description 1.2 Pin Descriptions Table 1-4. Bt8110/8110B Hardware Signal Definitions ( Pin Label Signal Name CLOCK Clock SYNC Synchronization Reset (1) RESET ADPCM_STB ADPCM Strobe PCM_STB PCM Strobe SERIAL_IN Serial Data Input SERIAL_OUT Serial Data Output ...
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Bt8110/8110B High-Capacity ADPCM Processor Table 1-4. Bt8110/8110B Hardware Signal Definitions ( Pin Label Signal Name A[13:0] ROM Address Bus CTRL[1,0] Control Inputs V Supply CC GND Ground SE SE Parameter TDP TDP Parameter Y Y Parameter NOTE(S): (1) ...
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Product Description 1.2 Pin Descriptions 1-12 High-Capacity ADPCM Processor Conexant Bt8110/8110B 100060C ...
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Functional Description 2.1 Overview Figure 2-1 respectively. The quantizer and reconstruction tables are stored in the external (Bt8110) or internal (Bt8110B) ROM that holds the fixed parameter values and lookup tables specified in the ADPCM algorithms. Both the encoder ...
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Functional Description 2.1 Overview Figure 2-1. Bt8110 Block Diagram SYNC SERIAL_IN Processor SERIAL_OUT CLOCK PSIG[7:0] Processor ALE, CS, MICREN Microprocessor AD[6:0] Figure 2-2. Bt8110B Block Diagram SYNC SERIAL_IN SERIAL_OUT CLOCK PSIG[7:0] ALE, CS, MICREN Microprocessor AD[6:0] 2-2 Quantizer Serial ...
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Bt8110/8110B High-Capacity ADPCM Processor 2.1.1 Clocking and Synchronization Each operating mode of the Bt8110/8110B requires clock and synchronization inputs to allow proper operation. If the microprocessor mode is used, then the synchronization signal frequency can be any submultiple of a ...
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Functional Description 2.1 Overview Table 2-1. Signal Connections Bt8110/8110B The interface for the Intel 8051 or Motorola 68HC11 microprocessors comprises the latch enable signal, the write enable (8051) or enable signal (68HC11), the chip select signal (one pin from ...
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Bt8110/8110B High-Capacity ADPCM Processor 2.2 Modes of Operation This section details the functional timing of the clock, synchronization, and signal interfaces. The data and control interfaces include the clock and synchronization inputs, the PCM and ADPCM inputs and outputs, and ...
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Functional Description 2.2 Modes of Operation Figure 2-3. Input and Output Timing for 24- or 32-Channel Full-Duplex Interleaved Operation (Microprocessor Control) Ref. Cycle ...
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Bt8110/8110B High-Capacity ADPCM Processor Bits e1 and e0 of the decoder input are used only for embedded coding operation where they specify the number of bits in the applied decoder input. Unused decoder input bits must be set to 0. ...
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Functional Description 2.2 Modes of Operation Table 2-3. Parallel Signal Output Bus 2.2.1.2 Reset Control The RESET signal pin can be used to reset the algorithm according to ANSI T1.303–1989 and ITU-T G.726 when microprocessor operation mode is used; ...
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Bt8110/8110B High-Capacity ADPCM Processor Figure 2-4. Input and Output Timing for 48- or 64-Channel Half-Duplex Encoder-Only Operation (Microprocessor Control) Ref. Cycle ...
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Functional Description 2.2 Modes of Operation Figure 2-5. Input and Output Timing for 48- or 64-Channel Half-Duplex Decoder-Only Operation (Microprocessor Control) Ref. Cycle ...
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Bt8110/8110B High-Capacity ADPCM Processor 2.3 Direct Framer Interface Operation The direct framer interface operation modes are intended for voice compression and storage applications such as voice mail, voice message store and forward, or voice response. For more details, see the ...
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Functional Description 2.3 Direct Framer Interface Operation 2.3.2 E1 Framer Interface In this configuration, address 0x40 must be set to a value of 0x1C to properly set the Bt8110/8110B mode. The per-channel control registers given in must be configured ...
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Bt8110/8110B High-Capacity ADPCM Processor 2.4 Hardware Control Some applications require precise timing of the modification of the code selected, transparent operation, or coding law. In these cases, the control signals can be provided by hardware and are updated each time ...
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Functional Description 2.4 Hardware Control 2.4.1 Mode Pins Mode Control (AD[2:0]) and Enable 32-Channel Operation (AD[3]) control pins are fixed for a given operational configuration and are not subject to timing specifications. Mode and control operation pins are defined ...
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Bt8110/8110B High-Capacity ADPCM Processor Figure 2-6. Hardware Control Interleaved Timing Ref. Cycle ...
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Functional Description 2.4 Hardware Control Figure 2-7. Hardware Control Encoder-Only Timing Ref. Cycle ...
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Bt8110/8110B High-Capacity ADPCM Processor Figure 2-8. Hardware Control Decoder-Only Timing Ref. Cycle ...
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Functional Description 2.4 Hardware Control 2-18 High-Capacity ADPCM Processor Conexant Bt8110/8110B 100060C ...
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Registers NOTE: 3.1 0x00–0x3F—Per-Channel Control Registers (per_chan_ctrl) Per-channel Control Registers can be used by the microprocessor to set the code selection, transparency, algorithm reset, and PCM coding type on a per-channel basis. This capability allows each channel configuration ...
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Registers 3.1 0x00–0x3F—Per-Channel Control Registers (per_chan_ctrl) Table 3-1. Bt8110 or Bt8110B with External Lookup Table ROM CODE[3:0] NOTE(S): Table 3-2. Bt8110B Internal Lookup Table ROM ( CODE[3:0] 3-2 ROM Code Table 0000 32 kbit/s G.726 0001 24 ...
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Bt8110/8110B High-Capacity ADPCM Processor Table 3-2. Bt8110B Internal Lookup Table ROM ( CODE[3:0] 3.2 0x40—Mode Control Register (mode) A write to address 0x40 will address the mode control registers for all channels. Five bits are ...
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Registers 3.2 0x40—Mode Control Register (mode) 3-4 High-Capacity ADPCM Processor Conexant Bt8110/8110B 100060C ...
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Bt8110/8110B High-Capacity ADPCM Processor 100060C Conexant 3-5 ...
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High-Capacity ADPCM Processor Conexant Bt8110/8110B 100060C ...
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Electrical and Mechanical Specifications 4.1 Microprocessor Interface Timing To enable the microprocessor interface, MICREN must logic high level. The pinouts for the controller interface are connected as given in either the 8051 or the 68HC11 controller. ...
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Electrical and Mechanical Specifications 4.1 Microprocessor Interface Timing Figure 4-1. Microprocessor Interface Timing WR* (8051) E (68HC11) 4.1.1 Bt8110 Timing The Bt8110/8110B is a fully static synchronous digital processor. The inputs MICREN, PSIGEN, and hardware mode AD[3:0] are all ...
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Bt8110/8110B High-Capacity ADPCM Processor Table 4-2. Bt8110/8110B Hardware Mode Timing Signal Name SYNC SERIAL_IN RESET CS WR* PSIG[7:0] ALE AD[6] AD[5] AD[4] Table 4-3. Input and Output Signal Timing Parameter Figure 4-2. Input and Output Signal Timing 100060C 4.0 Electrical ...
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Electrical and Mechanical Specifications 4.1 Microprocessor Interface Timing 4.1.2 ROM Specifications The ROM used as a part of the Bt8110/8110B requires an access time of less than two clock cycles. The worst-case internal propagation delays total 30 ns requiring ...
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Bt8110/8110B High-Capacity ADPCM Processor 4.2 Absolute Maximum Ratings The power consumption is proportional to the internal Bt8110/8110B system clock rate as shown in Stresses above those listed as Absolute Maximum Ratings may cause permanent damage to the device. This is ...
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Electrical and Mechanical Specifications 4.3 DC Characteristics 4.3 DC Characteristics All inputs in Leakage current for each pin is less than 10 µA in any state. All outputs have drive current 0.4 V ...
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Bt8110/8110B High-Capacity ADPCM Processor 4.4 Mechanical Specifications Figure 4-3. 68-Pin Plastic Leaded Chip Carrier (J-Bend) .042" X 45˚ .048" PIN 1 IDENTIFIER INCHES MIN. NOM. MAX .165 .200 A .090 .130 ...
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Electrical and Mechanical Specifications 4.4 Mechanical Specifications 4-8 High-Capacity ADPCM Processor Conexant Bt8110/8110B 100060C ...
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Appendix A. Hardware Mode Operation A.1 48- or 64-Channel Full-Duplex Hardware Mode Operation A.1.1 Introduction This appendix details the Bt8110/8110B ADPCM Processor 48- or 64-channel operation. This configuration may be used in conjunction with the Bt8200 ADPCM Line Formatter to ...
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Appendix A . Hardware Mode Operation A.1 48- or 64-Channel Full-Duplex Hardware Mode Operation Figure A-1. 48- or 64-Channel Configuration of the Bt8110/8110B CLOCK CLOCK SYNC SYNC WR* LAW AD[3] 64 CHANNEL SERIAL_IN SERIAL_IN RESET, CS CNTRL AD[4] CODE12 AD[5] ...
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Bt8110/8110B High-Capacity ADPCM Processor In addition, MICREN and PSIGEN must be held low if the serial inputs are used. However, the Bt8110/8110B has a parallel signal input capability. If PSIGEN is connected to the supply voltage, the parallel signal input ...
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Appendix A . Hardware Mode Operation A.1 48- or 64-Channel Full-Duplex Hardware Mode Operation Figure A-3. 96- or 128-Channel Half-Duplex Encoder-Only Functional Timing Ref. Cycle ...
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Bt8110/8110B High-Capacity ADPCM Processor Figure A-4. 96- or 128-Channel Half-Duplex Decoder-Only Functional Timing Ref. Cycle ...
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Appendix A . Hardware Mode Operation A.1 48- or 64-Channel Full-Duplex Hardware Mode Operation A-6 High-Capacity ADPCM Processor Conexant Bt8110/8110B 100060C ...
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Appendix B. T1 Speech Compression B.1 Introduction This appendix details the operation of the Bt8110/8110B ADPCM Processor with the Bt8300 Dual T1 Framer for application to speech compression. This operation mode can be used to provide full-duplex speech compression to ...
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Appendix Speech Compression B.1 Introduction Figure B-1. T1 Speech Compression Interface Block Diagram 12.352 MHz Oscillator TX A CLK 1.544 CLK 12 MHz CLK TX B CLK TX SYNC SYNC A OUT REC SLIP ...
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Bt8110/8110B High-Capacity ADPCM Processor the free-running synchronization signal TX SYNC A on the Bt8300 (this signal must also be connected to TX SYNC synchronize the B side transmitter). The Bt8110/8110B clock of 6.144 MHz is obtained by ...
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Appendix Speech Compression B.1 Introduction There is an offset in the timing between the input and the output signals caused by the processing delay of the Bt8110/8110B. In the encoded output from PCM-3 and ADPCM-22 results in ...
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Bt8110/8110B High-Capacity ADPCM Processor B.1.3 Microprocessor Interface And Per-Channel Configuration The microprocessor interface of the Bt8300 provides all control and status functions for the T1 lines; it can also be used to insert and extract signaling in this application. Table ...
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Appendix Speech Compression B.1 Introduction serial output with the same delay as when ADPCM decoding is taking place. The input to PSIG[0], the LSB, must be held at a logic low level in this application. Table B-2. ...
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Bt8110/8110B High-Capacity ADPCM Processor Table B-3 This table is a cross-reference between the encoder and decoder addresses and the PCM channel timeslots. Table B-3. Bt8110/8110B Processor Per-Channel Control Locations 100060C Appendix Speech Compression shows the encoder and ...
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Appendix Speech Compression B.1 Introduction B-8 High-Capacity ADPCM Processor Conexant Bt8110/8110B 100060C ...
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Appendix C. E1 Speech Compression C.1 Introduction This appendix details of operation of the Bt8110/8110B ADPCM Processor with the Bt8510 E1 Framer/LIU (or Bt8370 T1/E1 Framer/LIU) for application to speech compression. This mode can be used to provide full-duplex speech ...
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Appendix Speech Compression C.1 Introduction A 2.048 MHz bit clock is then provided at BITCKO. This bit clock is used as the clock input to both the transmitter circuit and the slip buffer circuit. This procedure ensures ...
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Bt8110/8110B High-Capacity ADPCM Processor The MICREN input must be connected to the supply voltage to enable the microprocessor interface. The PSIGEN pin must be held at a logic low level. If the RESET input is not used to reset the ...
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Appendix Speech Compression C.1 Introduction Figure C-2. E1 Speech Compression Functional Timing Diagram 8.192 MHz CLOCK SYNC ADPCM_STB 2.048 Mbit SERIAL_IN PCM-31 (Frame 15) 2.048 Mbit SERIAL_OUT PCM-31 ...
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Bt8110/8110B High-Capacity ADPCM Processor C.1.3 Microprocessor Interface and Per-Channel Configuration The microprocessor interface of the Bt8510 provides all control and status functions for the E1 lines; it can also be used to insert and extract signaling in this application. The ...
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Appendix Speech Compression C.1 Introduction Table C-2. Bt8110/8110B Microprocessor Memory Map C-6 High-Capacity ADPCM Processor Address 0 Encoder 0 Control 1 Decoder 0 Control 2 Encoder 1 Control • • • 0x3E Encoder 31 Control 0x3F Decoder ...
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Bt8110/8110B High-Capacity ADPCM Processor Table C-3 control word. This table is a cross-reference between the encoder and decoder addresses and the PCM channel timeslots. Table C-3. Bt8110/B Per-Channel Control Locations 100060C Appendix Speech Compression gives the encoder ...
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Appendix Speech Compression C.1 Introduction C-8 High-Capacity ADPCM Processor Conexant Bt8110/8110B 100060C ...
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Appendix D. T1 ADPCM Transcoder D.1 Introduction This appendix describes an assembly of the Bt8110/B ADPCM Processor, Bt8200 ADPCM Line Formatter, and Bt8300 (dual), Bt8360 (single) T1 Clear-Channel Framers, or the Bt8370 T1/E1 Framer/LIU that realizes a single-board transcoder meeting ...
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Appendix ADPCM Transcoder D.1 Introduction Figure D-1 microprocessor; a 12.352 MHz timing oscillator that can be synchronized to any of the T1 signals or synchronized externally; T1 line interface units, used to generate and recover pulses to ...
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Bt8110/8110B High-Capacity ADPCM Processor D.1.2 Summary The transcoder assembly can be used to double the voice-channel capacity line, as shown in channel banks, PBXs, or other T1 PCM stream signal sources. The ADPCM transcoder can be used ...
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Appendix ADPCM Transcoder D.1 Introduction D.1.3 ADPCM Transcoder System Specifications Table D-1. ADPCM Transcoder System Specifications Channel Capacity ADPCM Coding Signaling Modes T1 Framing T1 Clear Channel T1 ESF Data Link Configuration Control Synchronization Alarms T1 Self-Test ...
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Appendix E. E1 ADPCM Transcoder E.1 Introduction This appendix describes an assembly of the Bt8110/B ADPCM Processor, Bt8200 ADPCM Line Formatter, and Bt8510 E1 Framer or the Bt8370 T1/E1 Frame/LIU that realizes a single-board transcoder meeting the transcoding requirements of ...
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Appendix ADPCM Transcoder E.1 Introduction full-rate and compressed ports required by G.761, and to enter, implement, and monitor diagnostic tests of the Bt8110/B. The Bt8510 E1 framers include analog line interfaces that are compatible with 75 Ω ...
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Bt8110/8110B High-Capacity ADPCM Processor E.1.2 Summary The transcoder assembly can be used to double the voice-channel capacity line, as shown in channel banks, PBXs, or other E1 PCM stream signal sources. Figure E-2. Single-Board Transcoder Application E1 ...
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Appendix ADPCM Transcoder E.1 Introduction E-4 High-Capacity ADPCM Processor Conexant Bt8110/8110B 100060C ...
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... Phone: (91 11) 692 4780 Web Site www.conexant.com Fax: (91 11) 692 4712 Korea World Headquarters Phone: (82 2) 565 2880 Conexant Systems, Inc. Fax: (82 2) 565 1440 4311 Jamboree Road P. O. Box C Phone: (82 53) 745 2880 Newport Beach, CA Fax: (82 53) 745 1440 92658-8902 ...