PM7322-SI PMC-Sierra Inc, PM7322-SI Datasheet
PM7322-SI
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... S P TANDARD RODUCT PMC-940904, ISSUE 6 ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps ______________________________________________________________________________________________ PMC-Sierra, Inc. ROUTING CONTROL, MONITORING AND POLICING 800 Mbps PM7322 RCMP-800 ATM LAYER Issue 6: August 1997 105-8555 Baxter Place, Burnaby, BC Canada V5A 4V7 604 415-6000 PM7322 RCMP-800 ...
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... S P TANDARD RODUCT PMC-940904, ISSUE 6 ______________________________________________________________________________________________ ______________________________________________________________________________________________ PMC-Sierra, Inc. ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 105-8555 Baxter Place, Burnaby, BC Canada V5A 4V7 604 415-6000 PM7322 RCMP-800 ...
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... ELL ORMAT S S RAM YNCHRONOUS TATIC S OAM C F ................................................................................................................................145 ELL ORMAT DENTIFICATION EARCH JTAG S ......................................................................................................................................159 UPPORT ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps M ..................................................................................2 ONITORING (24) .................................................................................................12 (30) .....................................................................................................15 S (70) ...................................................................................19 IGNALS S (30).........................................................................................22 IGNALS ....................................................................................................59 ...............................................................................................................59 .......................................................................................................141 ...............................................................................................................144 .............................................................................................149 LGORITHM i PM7322 RCMP-800 ...
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... NPUT ELL NTERFACE ......................................................................................................................169 UTPUT ELL NTERFACE ABSOLUTE MAXIMUM RATINGS ..............................................................................................................171 D.C. CHARACTERISTICS..........................................................................................................................172 MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS............................................................174 RCMP-800 TIMING CHARACTERISTICS ..................................................................................................179 ORDERING AND THERMAL INFORMATION ............................................................................................189 MECHANICAL INFORMATION ...................................................................................................................190 ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps ii PM7322 RCMP-800 ...
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... OAM), VC table access, control and status monitoring, and configuration of the device. • Supports DMA access for cell extraction and insertion. • Uses common synchronous SRAMs for maintaining per-VC information. ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 1 6 ...
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... OAM performance monitoring for all VCs as described in ITU-T Recommendation I.610, Bellcore TR-NWT-001248 and Bellcore GR-1113-CORE. • Automatic OAM handling includes reception and generation of AIS, RDI, Forward Monitoring and Backward Reporting cells. ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 2 ...
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... Backward generated OAM cell identification/tagging provided to enable direct extraction by Egress device. • Incoming OAM cells can be terminated or passed to the Output Cell Interface and/or microprocessor. • Outgoing OAM cells sourced from automatic OAM generating circuitry, Input Cell Interface or microprocessor. ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 3 ...
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... IEEE 1149.1 - Standard Test Access Port and Boundary Scan Architecture, May 21, 1990. • PMC-940212, ATM_SCI_PHY, "SATURN Compliant Interface For ATM Devices", July 1994, Issue 2. • ATM Forum/95-0013R9, Draft Version 3.0 of ATM Forum Traffic Management Specification Version 4.0, October, 1995 ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 4 ...
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... ROUTING CONTROL MONITORING AND POLICING INGRESS UT OPIA Int PER PER PHY SHA PING CELL 4 PRO CESSIN G OUT PUT EGRESS B UFFER PM7322 RCMP-800 Ext SCI-PH Y Int ATM SWITCHING Ce lls FABRIC ...
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... ROUTING CONTROL, MONITORING AND POLICING 800 Mbps E load D 3-to-N decoder Q IPRTY[0] ISOC IFCLK IAVALID 4:2 ICA[ IPOLL N-to-1 IBUS8 mux 6 PM7322 RCMP-800 OSC TSOC TDAT[7:0] TXPRTY TCAMPH TWA[1:0] TWRMPHB TFCLK S/UNI-MPH RSOC #1 RDAT[7:0] RXPRTY RCAMPH RRA[1:0] RRDMPHB RFCLK TSOC TDAT[7:0] TXPRTY TCAMPH ...
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... PMC-940904, ISSUE 6 ______________________________________________________________________________________________ The IAVALID output is not required for this application. In this application, the aggregate throughput is less than 6.144 Mbyte/s with 32 DS-1 ports; therefore, the clock oscillator frequency can be as low as 6.5 MHz. ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 7 ...
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... itra tio ffe r 8 PM7322 RCMP-800 T TY OSOC ORDENB ...
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... PMC-940904, ISSUE 6 ______________________________________________________________________________________________ DESCRIPTION The PM7322 Routing Control, Monitoring and Policing 800 Mbps (RCMP-800) device is a monolithic integrated circuit that implements ATM layer functions that include fault and performance monitoring, header translation and cell rate policing. The RCMP-800 is intended to be situated between a switch core and the physical layer devices in the ingress direction ...
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... FIFO. The microprocessor can send cells over the Output Cell Interface. The RCMP-800 is implemented in low power, 0.6 micron, +5 Volt CMOS technology. It has TTL compatible inputs and outputs and is packaged in a 240 pin copper slugged plastic QFP package. ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 10 ...
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... IBUS8 VDD_AC VSS_AC VDD_DC VSS_DC IFCLK VDD_DC VSS_DC TCK TMS TDI TDO TRSTB D[0] D[1] D[2] D[3] VDD_DC VSS_DC VDD_AC VSS_AC D[4] D[5] D[6] D[7] PIN 60 ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps PM7322 RCMP-800 TOP VIEW 11 PIN 180 NC VSS_AC VDD_AC SA[9] SA[8] SA[7] SA[6] SA[5] SA[4] VSS_AC VDD_AC VSS_DC VDD_DC SA[3] SA[2] SA[1] SA[0] SD[15] SD[14] SD[13] VDD_AC ...
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... When ORDENB is sampled high using the rising edge of OFCLK, no read is performed and outputs ODAT[15:0], OPRTY[1:0] and OSOC are tristated if the OTSEN input is high. ORDENB must operate in conjunction with OFCLK to access the FIFO at a high enough instantaneous rate as to avoid FIFO overflows. 12 PM7322 RCMP-800 ...
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... ODAT[15:0] bus. When OSOC is high, the first word of the cell structure is present on the ODAT[15:0] stream. OSOC is updated on the rising edge of OFCLK. When the Output Cell Interface is configured for tristate operation using the OTSEN input, tristating of the OSOC output is controlled by the ORDENB input. 13 PM7322 RCMP-800 ...
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... ODAT[15:0], OPRTY[1:0] and OSOC outputs. When OTSEN is high, the active low read enable input, ORDENB, controls when the ODAT[15:0], OPRTY[1:0] and OSOC outputs are driven. When OTSEN is low, the ODAT[15:0], OPRTY[1:0] and OSOC outputs are always driven. 14 PM7322 RCMP-800 ...
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... FIFO interface bus width. When IBUS8 is tied high, a 10-bit interface consisting of a start of cell indication, an 8-bit octet bus, and a parity bit is selected. When IBUS8 is low, a 19-bit interface consisting of a start of cell indication, a 16-bit word bus, and two parity bits is selected. 15 PM7322 RCMP-800 ...
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... IAVALID to logic 0. When this occurs, no PHY device should drive ICA[1] during the following clock cycle. Polling is performed in a incrementing sequential order. The PHY device selected for transfer is based on the IADDR[4:0] value present when IWRENB[1] falls. The IADDR[4:0] bus is updated on the rising edge of IFCLK. 16 PM7322 RCMP-800 ...
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... IDAT[15:0] bus. Odd or even parity selection can be made using a register. A maskable interrupt status is generated upon a parity error; no other actions are taken. IPRTY[1:0] is sampled on the rising edge of IFCLK and is considered valid only when one of the IWRENB[4:1] signals so indicates. 17 PM7322 RCMP-800 ...
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... RCMP-800 will not poll the PHY device which is sending the cell and so PHY devices need not support cell availability indication during cell transfer.) The selection of a particular PHY device from which to transfer a cell is indicated by the state of IADDR[4:0] when IWRENB[1] falls. Note that ICA[ input only 18 PM7322 RCMP-800 ...
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... The four most significant bits (SA[19:16]) identify the fields within a VC Table Record. In most applications, SA[19:16] is decoded to SRAM chip selects. Physical memory need not be allocated for unused fields. The SA[15:0] outputs are also used to access the Search Table. The SA[19:0] bus is updated on the rising edge of SYSCLK. 19 PM7322 RCMP-800 ...
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... The RCMP-800 presents valid data on the SD[39:0] pins upon the rising edge of SYSCLK which is written into the SRAM on the next SYSCLK rising edge. SD[39:0] is tri-stated on the rising edge of SYSCLK. Contention is avoided by not performing a read during the cycle after the write burst. 20 PM7322 RCMP-800 ...
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... SRAM access type. SRWB is qualified by the SADSB output. The RCMP-800 drives the SRWB output high if the subsequent cycle is a SRAM read. The RCMP- 800 drives the SRWB output low if the current cycle is a SRAM write. SRWB is updated on the rising edge of SYSCLK. 21 PM7322 RCMP-800 ...
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... Microprocessor Cell Data register after DREQ is asserted will return the first word of the cell. DREQ is deasserted after the last word of the cell has been read or an abort has been signaled. The polarity of the DREQ output is programmable and defaults to active high. 22 PM7322 RCMP-800 ...
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... ALE is active high and latches the address bus A[6:0] when low. When ALE is high, the internal address latches are transparent. It allows the RCMP-800 to interface to a multiplexed address/data bus. ALE has an integral pull up resistor. 23 PM7322 RCMP-800 ...
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... ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 73 The interrupt request (INTB) output goes low when a RCMP-800 interrupt source is active and that source is unmasked. INTB returns high when the interrupt is acknowledged via an appropriate register access. INTB is an open drain output. 24 PM7322 RCMP-800 ...
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... ONESEC must be glitch free and may be treated as an asynchronous input. 82 The active low reset (RSTB) signal provides an asynchronous RCMP-800 reset. RSTB is a Schmitt triggered input with an integral pull up resistor. When RSTB is forced low, all RCMP-800 registers are forced to their default states. 25 PM7322 RCMP-800 ...
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... RCMP-800 test access port reset via the IEEE P1149.1 test access port. TRSTB is a Schmitt triggered input with an integral pull up resistor. The JTAG TAP controller must be initialized when the RCMP-800 is powered up. If the JTAG port is not used TRSTB must be connected to the RSTB input or VSS. 26 PM7322 RCMP-800 ...
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... ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 11 The DC power (VDD_DC1 - VDD_DC20) pins should 31 be connected to a well-decoupled + supply in 39 common with VDD_AC The DC ground (VSS_DC1 - VSS_DC20) pins should 32 be connected to GND in common with VSS_AC PM7322 RCMP-800 ...
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... ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 25 The AC power (VDD_AC1 - VDD_AC16) pins should 37 be connected to a well-decoupled + supply in 55 common with VDD_DC The AC ground (VSS_AC1 - VSS_AC16) pins should 38 be connected to GND in common with VSS_DC PM7322 RCMP-800 ...
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... Failure to connect these pins externally may cause malfunction or damage the RCMP-800. 5. The VDD_DC and VDD_AC power pins are not internally connected together. Failure to connect these pins externally may cause malfunction or damage the RCMP-800. ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 29 ...
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... If one of the PHY links is a User-Network Interface (UNI) and the GFC field is non-zero, the cell will not be filtered by the Input Cell Interface, but will be discarded by the VC Identification circuit option, all cells can be interpreted as UNI cells. ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 30 ...
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... Figure 3 is not intended to imply any restrictions on the positioning of Field A and Field B. These fields may occur any where within the appended octets or the ATM header. The Primary Key and Secondary Key may also intersect. ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 31 ...
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... Field B and the VPI/VCI field are positioned "right justified" within the routing word. ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Cell Postpend Field A Field length <= 128 bits PHY Field A Field B VPI/VCI ID Primary Key Secondary Key 32 PM7322 RCMP-800 Cell Header VPI/VCI HEC UDF (NNI (UNI) ...
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... Primary Search Key. Field B and the VPI/VCI field are concatenated to form the secondary search key. ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Field 0-16 bits + L <= 16 bits P A Field 0-11 bits Unused PM7322 RCMP-800 VPI / VCI 28 bits = 39 bits ...
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... Some VPI and VCI bits may always be zero; therefore, they need not be used in the search. In some instances, the Primary Search Key may ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Field B Size & Location Field A Size & Location VPI/VCI PHY ID PRIMARY SECONDARY SEARCH KEY SEARCH KEY 34 PM7322 RCMP-800 ROUTING WORD ...
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... Search Table and the VC Table. ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 6 cell/s is guaranteed. The general expression for 1 (17 max.binary tree depth)(SYSCLK period) cell / s 1 (cell word length)(SYSCLK period) cell / words of memory. The Secondary Search PM7322 RCMP-800 ...
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... SD[32:17] SD[16] Left Branch Right Leaf 36 PM7322 RCMP-800 ( ...
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... If "Left Leaf" logic zero, "Left Branch" contains the SA[15:0] value pointing to another Secondary Search Table entry. If the Search Table entry is part of a multicast linked list, the Left Branch is the VC Table address of one VC in the multicast. ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 37 ...
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... If the Primary Search Table is in use, no root node shall use location SA[15:0]=0x0000, although this location may be used for nodes at least one level down. A value of 0x0000 in the Primary Search Table represents a null pointer. ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps = L = 0), the root of the single P ...
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... When a new VC is provisioned, the microprocessor must initialize the contents of the VC Table Record. Refer to the External RAM Address (MSB) and Access Control register description for details on access control. Once provisioned, the microprocessor can retrieve the contents of the VC Table Record. ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 39 ...
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... Output Header (40) Pre/Post pend (40) Pre/Post pend (40) CLP=0 cell count (32) CLP=1 cell count (32) current cell count (16) Backward Reporting Counts Forward Monitoring Counts 40 PM7322 RCMP-800 LSB(0) Reserved for Search Table (16) VCI (16) BWD Routing Tag UDF (5) I#1 (20) non-compliant cell count #1 (16) ...
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... If this bit is set, the CLP=0 and CLP=1 cell counts include user information cells. If this bit is set, the CLP=0 and CLP=1 cell counts include OAM and RM cells. 41 PM7322 RCMP-800 ...
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... The threshold is set by the CCThresh bit of the Performance Monitoring Configuration 1 register (0x19). This bit is a logic least one cell has violated the traffic contract. This bit is not cleared upon a read; it must be cleared explicitly by writing to its location. 42 PM7322 RCMP-800 ...
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... OAM cell is routed to the same destination as the user cells. If the RCMP-800 is an end point, the default configuration terminates and processes all OAM cells except Activate/Deactivate and Loopback cells, which are routed to either the Output Cell Interface or the Microprocessor Cell Interface. ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 43 ...
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... SYSCLK period. With a 50 MHz clock 20, 40 160 ns. ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps t = time quantum (s) PCR = Peak Cell Rate (cell/s) = Cell Delay Variation (s) SCR = Substained Cell Rate (cell/s) MBS = Max. Burst Size at the Peak Cell Rate (cells Burst Tolerance ( PCR 44 PM7322 RCMP-800 ...
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... PCR min 11.9 cells / 5.96 cells / ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 1048575; therefore, the smallest peak rate (or max 20ns 40ns 80ns 160ns 45 PM7322 RCMP-800 LSB 0 , then L shall be taken to max ...
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... Set the POLI status bit but take no other action other than to increment the appropriate non- compliant cell count.. Reduce the priority of high priority cells. Reduce the priority of high priority cells and discard low priority cells. Discard all non-conforming cells. 46 PM7322 RCMP-800 ...
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... Dropped CLP=0 cells and dropped CLP=1 cells. 3.) Cells which are non-compliant with GCRA#1, and cells compliant with GCRA#1 which are non-compliant with GCRA#2. 4.) Cells which are non-compliant with GCRA#1, and cells which are non- compliant with GCRA#2 ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 47 ...
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... The RCMP-800 maintains counts on a per VC basis and over the aggregate cell stream. The following parameters are stored on a per VC basis: • number of low priority cells • number of high priority cells • non-compliant cell counts (user programmable) ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 48 ...
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... Events are accumulated over consecutive intervals as defined by the period of the microprocessor initiated data latching. The RCMP-800 maintains current counts and holding registers. A latching event transfers the counter values into holding registers ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 49 ...
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... If the RCMP-800 is configured as a source of PM cells, then the BIP-16, current cell count, MSN and TUC are updated dependent of the outcome of cell policing. That is, those fields are updated if and only if the cells are not discarded by the RCMP-800. ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 50 ...
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... Enables Continuity Checking user or AIS cell is received over a 1.5 +/- 0.5 or 2.5 +/- 0.5 (default, controlled by the AISRDIThresh bit in register 0x19) second window, a Continuity Check OAM cell is generated. The CC cell generation interval set by the CCThresh bit of the Performance Monitoring Configuration 1 register (0x19). 51 PM7322 RCMP-800 ...
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... SA[19:16] = 1101. If the RCMP-800 is configured as a source of PM cells (SRCPM = 1, PM_activate = 1, and the RCMP-800 is configured as a flow-end-point), the BLKSIZE[1:0] bits select the nominal number of user cells per performance monitoring block. BLKSIZE[1:0] User cells per block 00 1024 01 128 10 256 11 512 52 PM7322 RCMP-800 ...
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... This bit is cleared upon receiving the first PM cell. This clears the current cell count and BIP16. The PM0 bit is used to note the arrival of the first PM cell. The PM0 bit suppresses accumulation of error counts. If this bit is not set, errors counts will be accumulated. 53 PM7322 RCMP-800 ...
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... Block Error Detection Code - This field is the even parity BIP-16 error detection code computed over the information field of the block of user cells transmitted after the last monitoring cell. ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 54 ...
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... TUC field. If the number of misinserted cells equals or exceeds the threshold set by the MMISINSERT[7:0] register bits, the SECB count is incremented and the misinserted cell accumulation is suppressed. ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 55 ...
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... Interface or the Output Cell Interface. The flow of the Activation/Deactivation cells is controlled by the ACTDEtoUP and ACTDEtoOCIF bits of the ALCP Routing Configuration register. This enables the management entity to process the cell, and respond by modifying the "PM_activate" or "CC_activate" bit and sending back an acknowledgment. ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 56 ...
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... Input Cell Interface • cells inserted via the Microprocess Cell Inferface if • the UPHDRX register bit is a logic 1 • generated AIS cells if the TAGAIS register bit is a logic 0 • generated Continuity Check cells Forward RM cell. Backward RM cell. 57 PM7322 RCMP-800 ...
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... It is the Connection Admission Control entity's responsibilty to ensure the traffic is within the rate supported. ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Backward generated OAM cells: • generated RDI • generated Backward Reporting • generated AIS if the TAGAIS register bit is a logic 1 Reserved 58 PM7322 RCMP-800 ...
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... SRAM can be accessed through this port. Test mode registers are used to enhance the testability of the RCMP-800. The interface has a 16 bit wide data bus. Multiplexed address and data operation is supported. ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 59 ...
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... The INSRDYI bit in the Master Interrupt Status #1 (0x02) register is set whenever the INSRDY bit is asserted. 2.) Write the WRSOC bit in the Microprocessor Insert Buffer Control and Status register. At the same time, ensure that the OLEN[2:0], CRC10, UPHDRX ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 60 ...
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... Last pre-pended word, M • N (optional) 1st post-pended word (optional) ... Last post-pended word, N < 6 (optional) ATM header: GFC, VPI and VCI ATM header: VCI, PTI and CLP HEC and User Defined Field 1st ATM payload word 2nd ATM payload word ... 24th ATM payload word 61 PM7322 RCMP-800 ...
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... UPURS bit is a logic one, a causation word is prepended to the cell to indicate why the cell was routed to the Microprocessor Cell Buffer and provide cell status information. ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps ILEN[2:0] Buffer Capacity PM7322 RCMP-800 ...
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... ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Definition Bit 15 PHYID[4] Bit 14 PHYID[3] Bit 13 PHYID[2] Bit 12 PHYID[1] Bit 11 PHYID[0] Bit 10 PROV Bit 9 End_pt Bit 8 Seg_End_pt Bit 7 Reserved Bit 6 NNI Bit 5 VPC Bit 4 OAM_type Bit 3 TYP[3] Bit 2 TYP[2] Bit 1 TYP[1] Bit 0 TYP[0] 63 PM7322 RCMP-800 ...
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... AIS 0010 RDI 0011 Continuity Check 0100 Loopback 0101 Forward Monitoring 0110 Backward Reporting 0111 Monitoring/Reporting 1000 Activate/Deactivate 1001 Undefined OAM 1010 Reserved 1011 Forward RM 1100 Backward RM 1101 Invalid PTI 1110 Reserved 1111 OAM cell with errored CRC-10. 64 PM7322 RCMP-800 ...
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... External RAM Data (LSB) 0x24 External RAM Data 0x25 External RAM Data (MSB) 0x26 Maximum VC Table Index 0x27 Search Key Construction 0x28 Field A Location and Length 0x29 Field B Location and Length 0x2A-0x2F Reserved ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 65 ...
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... Count of Cells Dropped Due to Congestion 0x35-0x37 Reserved 0x38 Output Cell FIFO Configuration 0x39 Reserved 0x3A Output Cell Counter (LSB) 0x3B Output Cell Counter (MSB) 0x3C-0x3F Reserved 0x40 Master Test 0x41-0x7F Reserved for Test ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 66 ...
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... Certain register bits are reserved. These bits are associated with megacell functions that are unused in this application. To ensure that the RCMP-800 operates as intended, reserved register bits must only be written with logic 0. Similarly, writing to reserved registers should be avoided. ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 67 ...
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... RESET bit is a logic 1, the entire RCMP-800 is held in reset. This bit is not self-clearing. Therefore, a logic 0 must be written to bring the RCMP-800 out of reset. Holding the RCMP-800 in a reset state places it into a low power, ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Default PM7322 RCMP-800 ...
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... A hardware reset clears the RESET bit, thus negating the software reset. Note, unlike the hardware reset input, RSTB, the software reset bit, RESET does not force the RCMP-800's digital output pins tristate. ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 69 ...
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... The SEL1SEC bit determines the trigger for processing that relies on an one second clock, such as AIS and RDI cell generation. If SEL1SEC is a logic 0, ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Default PM7322 RCMP-800 ...
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... RDI alarm status. If RDIVC is a logic 1, the Latest Alarmed Virtual Connection register will be loaded with the VC Table index corresponding to the virtual connection whose “RDI” bit has changed. ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 71 ...
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... DREQ output is active low. BUSYPOL: The BUSYPOL bit sets the polarity of the BUSYB primary output. If BUSYPOL is a logic 0, the BUSYB output is active low. If BUSYPOL is a logic 1, the BUSYB output is active high. ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 72 ...
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... VP Resource Management cell has been received with PTI not equal to '110'. This bit is cleared when this register is read. ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Default PM7322 RCMP-800 ...
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... Alarmed Virtual Connection register is updated with the VC Table index for the virtual connection simultaneously with the setting of the AISI bit. RDII: The RDII bit indicates a RDI alarm has changed state. When logic 1, the RDII ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 74 ...
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... The FULLI bit may also become a logic result of setting the FIFORST bit of the Output Cell Configuration register (0x38). With the output FIFO reset unable to accept any cells, which is the same immediate symptom as a full buffer. ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 75 ...
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... Status (0x30) register has been asserted. The XFERI bit is cleared when this register is read. REG3I: The REG3I bit indicates that at least one bit in Register 0x03, RCMP-800 Master Interrupt Status #2, is currently asserted. ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 76 ...
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... SD[39:32]. When logic 1, the SPRTYI[3] bit indicates a parity error over inputs SD[31:24]. When logic 1, the SPRTYI[2] bit indicates a parity error over inputs SD[23:16]. When logic 1, the SPRTYI[1] bit indicates a parity error over inputs ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Default PM7322 RCMP-800 ...
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... LIMITMC register bit is logic 1. If the BADVCtoUP register bit is a logic 1, the cell associated with the failed search is routed to the Microprocessor Cell Interface. This bit is cleared when this register is read. ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 78 ...
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... This bit is an image of the VCVALID bit in the Master Interrupt Status #1 register (0x02 provided so that VCVALID may be sampled without clearing the interrupt status bits. ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Default PM7322 RCMP-800 ...
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... Master Interrupt Status #2 register. When an enable bit is set to logic 1, the INTB output is asserted low when the corresponding interrupt status bit is a logic 1. ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Default PM7322 RCMP-800 ...
Page 85
... The SYSCLK active (SYSCLKA) bit monitors for low to high transitions on the SYSCLK input. SYSCLKA is set high on a rising edge of SYSCLK, and is set low when this register is read. ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Default PM7322 RCMP-800 ...
Page 86
... It is recommended the entire contents of the FIFO be transferred and cached for subsequent processing. ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Default PM7322 RCMP-800 ...
Page 87
... S P TANDARD RODUCT PMC-940904, ISSUE 6 ______________________________________________________________________________________________ VCINDEX[15:0] corresponds to the value which must be written into the External RAM Address (LSB) register to access the new status information of the virtual connection. ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 83 ...
Page 88
... It is recommended that, whenever any other bit in this register or the Input Polling Configuration register is changed, FIFORST be set to logic one upon the change and set to logic zero after. ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Default PM7322 RCMP-800 ...
Page 89
... IDAT[15:0] and IPRTY[0] is ignored. The IBYTEPRTY register bit is ignored if the IBUS8 input is asserted, in which case IPRTY[0] is the parity over IDAT[7:0] and IPRTY[1] is ignored. ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps FIFODP[1] FIFODP[ PM7322 RCMP-800 FIFO DEPTH 4 cells 3 cells 2 cells 1 cell ...
Page 90
... I.e., if BUS8 is logic 0, the third word of the 27-word ATM cell is omitted and a 26-word cell (plus appended words) is transferred. If BUS8 is logic 1, the fifth octet of the 53-octet ATM cell is omitted and a 52-octet cell (plus appended octets) is transferred. ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 86 ...
Page 91
... The contents of these registers are valid within four IFCLK cycles after a transfer is triggered by a write to address 0x00, 0x09, 0x0A or 0x0B. ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Default PM7322 RCMP-800 ...
Page 92
... ICELL[7] Bit 6 R ICELL[6] Bit 5 R ICELL[5] Bit 4 R ICELL[4] Bit 3 R ICELL[3] Bit 2 R ICELL[2] Bit 1 R ICELL[1] Bit 0 R ICELL[0] ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Default PM7322 RCMP-800 ...
Page 93
... The contents of these registers are valid within four SYSCLK cycles after a transfer is triggered by a write to address 0x00, 0x09, 0x0A or 0x0B. ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Default PM7322 RCMP-800 ...
Page 94
... ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Default Meaning Poll all 32 PHY devices. Poll PHY#1 thru PHY#2 Poll PHY#1 thru PHY Poll PHY#1 thru PHY#31 Poll all 32 PHY devices 90 PM7322 RCMP-800 ...
Page 95
... Any Physical Layer UNI cells which contain non-zero GFC fields shall be passed through the input FIFO and subsequently rejected by the VC Identification algorithm. This results in a increment of the Invalid Cell Count instead of the Physical Layer Cell Count. ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 91 ...
Page 96
... DREQ output is deasserted even if more cells are contained in the cell buffer. This eases the identification of cell boundaries. If DMAEN is a logic 0, the DREQ output is held deasserted. ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Default PM7322 RCMP-800 ...
Page 97
... If ABORT is set to a logic 1, the current cell being read is purged from the buffer and the DREQ output will be deasserted. ABORT is not readable and is cleared upon a read of the Microprocessor Cell Data register (0x12). ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 93 ...
Page 98
... If multiple cells exist in the buffer, then EXTCA will remain at logic 1 until the last word of the last cell is read. Assertion of the EXTCA status bit also results in a maskable interrupt. ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 94 ...
Page 99
... CRC-10. UPHDRX: The header translation (UPHDRX) bit controls the header processing of the current cell written into the buffer. ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Default PM7322 RCMP-800 ...
Page 100
... The state of PHY[4:0] when the WRSOC is set selects the PHY device for that cell: PHY[4:0] 00000 00001 00010 00011 ........... 11111 ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Associated Source PHY #1/single PHY PHY #2 PHY #3 PHY #4 ........... PHY #32 96 PM7322 RCMP-800 ...
Page 101
... It remains set for as long as the buffer is not completely full. INSRDY is cleared upon the write of the first word of a cell. Assertion of the INSRDY bit results in a maskable interrupt. ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 97 ...
Page 102
... For interrupt driven systems, the INSRDYI interrupt status bit and associated maskable interrupt indicate that a cell may be written. ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Default PM7322 RCMP-800 ...
Page 103
... When performance management is disabled, no physical memory needs to be provided at the SA[19:16]=1101, 1110 and 1111 locations. ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Default PM7322 RCMP-800 ...
Page 104
... Interface have the HEC and UDF bytes replaced with the VC Table index. This enables the microprocessor to immediately determine the location record in its data structure without having to perform its own binary search. This feature is provided to enable high speed processing of cells. ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 100 ...
Page 105
... ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Definition Disable overwrite Appended byte 1 Appended byte 2 Appended byte 3 Appended byte 4 Appended byte 5 Appended byte 6 Appended byte 7 Appended byte 8 Appended byte 9 Appended byte 10 Header byte 1 Header byte 2 Header byte 3 Header byte 5 UDF 101 PM7322 RCMP-800 ...
Page 106
... ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Do not copy; drop at flow end-points. Do not copy; do not drop at flow end-points. Copy and drop loopback cells at flow end-points. Copy for all connections, drop at flow end-points. 102 PM7322 RCMP-800 ...
Page 107
... If CCThresh is a logic 1, the Continuity Check alarm threshold period is 3.5 +/- 0.5 sec, and CC cells are generated on one second boundaries. ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Default 103 PM7322 RCMP-800 ...
Page 108
... Note that the TAGAIS does not affect the Cell Status Information byte for AIS cells received through the Input Cell Interface or the Microprocessor Cell Interface. The TAGAIS bit allows a more flexible treatment of generated AIS cells. ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 104 ...
Page 109
... Block (SECB). The number of misinserted cells is not counted for SECBs. If MMISINS[7: binary zero, SECB is not declared as a result of excessive lost cells. ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Default 105 PM7322 RCMP-800 ...
Page 110
... GCRA2[7:0]=11000000. If GCRA1[7:0] = 00000000, the first GCRA policing instance is globally disabled for ABR connections. ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Default BRM 106 PM7322 RCMP-800 OAM USER GCRA1[7] ...
Page 111
... ABR connections. Note that Resource Management (RM) cells are considered distinct and separate from OAM cells for the purposes of cell rate policing. ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps BRM 107 PM7322 RCMP-800 OAM USER GCRA2[7] ...
Page 112
... Note that Resource Management (RM) cells are considered to be OAM cells for the purposes of cell rate policing in VBR connections. ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Default OAM USER GCRA1[0] GCRA1[1] GCRA1[2] GCRA1[3] 108 PM7322 RCMP-800 1 ...
Page 113
... ABR and VBR/CBR connections. POLQNTM[1: ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Cell Type OAM GCRA2[0] GCRA2[1] GCRA2[2] GCRA2[3] SYSCLK Period 1 times SYSCLK period. 2 times SYSCLK period 4 times SYSCLK period 8 times SYSCLK period 109 PM7322 RCMP-800 USER 1 ...
Page 114
... CLP=0 cells. dropped CLP=0 cells. Cells which compliant with with GCRA#1 Cells which are non-compliant with GCRA#1 110 PM7322 RCMP-800 definition non-compliant CLP=1 cells. dropped CLP=1 cells. Cells GCRA#1 which are non-compliant with GCRA#2. Cells which are non-compliant with GCRA#2 ...
Page 115
... Cell Interface. Regardless of the state of this bit, all RDI cells are passed to the Output Cell Interface if the RCMP-800 is not an end point for the connection. ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Default 111 PM7322 RCMP-800 ...
Page 116
... RM cells and VCI=6 for VP-RM cells. If the VPRMSEL bit of the CRAM Configuration register is a logic 1, VP-RM cells are further qualified by PTI=110. BADVCtoUP: If the BADVCtoUP bit is a logic 1, all cells with an unprovisioned VPI/VCI are routed to the Microprocessor Cell Interface for header logging. ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 112 ...
Page 117
... Output Cell Interface). If the RCMP-800 is not an OAM end flow then the state of the DROPCRC10 bit determines whether or not the cell is passed to the Output Cell Interface. ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 113 ...
Page 118
... If CNTUNDEF is a logic 0, only CRC-10 errors result in an increment; received OAM cells with undefined Type and Function fields will result in an increment of the Vaild OAM Cell Count register. ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Default 114 PM7322 RCMP-800 ...
Page 119
... If DROPCRCRM is a logic 0, the RM cells are transparently passed regardless of whether the CRC10 is in error. Regardless of the DROPCRCRM bit, RM cells with CRC10 errors are indicated via the INVALI bit of the Master Interrupt Status #1 register (0x02). ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 115 ...
Page 120
... Access Control register to access the external SRAM. SA[15:0]: This register holds the 16 least significant bits of the external SRAM address used for µP accesses. It identifies the desired VC Table Record. ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Default 116 PM7322 RCMP-800 ...
Page 121
... Table Record before this register is written. SA[19:16]: The SA[19:16] bits represent the four most significant bits of the external SRAM address used for µP accesses. ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Default 117 PM7322 RCMP-800 ...
Page 122
... First, the read requested. Next, a write of all zeros to the SSRAM location just read. Similarly, after reading SRAM address SA[19:16] = 0111, the RCMP-800 clears bits 31:0 of the location just read. Bits 39:32 of the address just read are preserved. ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 118 ...
Page 123
... Bit 11 R/W SD[27] Bit 10 R/W SD[26] Bit 9 R/W SD[25] Bit 8 R/W SD[24] Bit 7 R/W SD[23] Bit 6 R/W SD[22] Bit 5 R/W SD[21] Bit 4 R/W SD[20] Bit 3 R/W SD[19] Bit 2 R/W SD[18] Bit 1 R/W SD[17] Bit 0 R/W SD[16] ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Default Default 119 PM7322 RCMP-800 ...
Page 124
... Note, these are not typical read/write registers. When performing a Read operation, the data in these registers represents the external SRAM data which were read from a previous external SRAM read operation. ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Default 120 PM7322 RCMP-800 ...
Page 125
... Setting MAX[15:0] to all zeros effectively disables (for all locations except location SA[15:0] = 0x0000) the generation of AIS, RDI and Continuity Check cells and disables the clearing of AIS, RDI and Continuity Check alarms. ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Default 121 PM7322 RCMP-800 ...
Page 126
... ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Default PHY[0] Number of PHY ID bits in Primary Key X Reserved (single PHY interface) 122 PM7322 RCMP-800 Number of Supported PHYs - ...
Page 127
... bit Field A should be extracted starting at the 120th bit of the Routing Word, we would set LA ='01010' (length = 10) and SA='1110111' (starting address = 119), i.e. write 0x0A77 to 0x28. ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Default 123 PM7322 RCMP-800 ...
Page 128
... bit Field B should be extracted starting at the 120th bit of the Routing Word, we would set LB ='1010' (length = 10) and SB0='1110111' (starting address = 119), i.e. write 0x0A77 to 0x29. ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Default 124 PM7322 RCMP-800 ...
Page 129
... The OAMERRCH bit is set to logic 1 if the Errored OAM Cell Count register contains a non-zero value. OAMCH: The OAMCH bit is set to logic 1 if the Valid OAM Cell Count register contains a non-zero value. ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Default 125 PM7322 RCMP-800 ...
Page 130
... A logic 0 indicates that no overrun has occurred. The OVR bit is cleared by reading this register. The XFERI bit of the Master Interrupt Status #1 is set when the OVR bit is asserted. ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 126 ...
Page 131
... CNTUNDEF bit of the CRAM Configuration register (register 0x20). If the CNTUNDEF bit is a logic 1, then OAM cells with a correct CRC-10, but an undefined Type of Function field will be counted as vaild OAM cells. ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Default 127 PM7322 RCMP-800 ...
Page 132
... This transfer and reset is carried out in a manner that ensures that coincident events are not lost. ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Default 128 PM7322 RCMP-800 ...
Page 133
... This transfer and reset is carried out in a manner that ensures that coincident events are not lost. ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Default 129 PM7322 RCMP-800 ...
Page 134
... This transfer and reset is carried out in a manner that ensures that coincident events are not lost. ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Default 130 PM7322 RCMP-800 ...
Page 135
... OCA[1] outputs indicate that the output FIFO is empty. When OCALEVEL0 is set to logic 0, a deassertion of the OCA output indicates that the output FIFO is near empty and contains only four words. ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Default 131 PM7322 RCMP-800 ...
Page 136
... ATM cell. When OBUS8 is a logic 0, the binary CELLPOST[3:0] value is the number of words post-pended to the basic 27 word ATM cell. OCAINV: The OCAINV bit selects the active polarity of the OCA signal. The default ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 132 ...
Page 137
... BUS8 is logic 0, the third word of the 27-word ATM cell is omitted and a 26-word cell (plus appended words) is transferred. If BUS8 is logic 1, the fifth octet of the 53-octet ATM cell is omitted and a 52-octet cell (plus appended octets) is transferred. ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 133 ...
Page 138
... Bit 6 R OCELL[6] Bit 5 R OCELL[5] Bit 4 R OCELL[4] Bit 3 R OCELL[3] Bit 2 R OCELL[2] Bit 1 R OCELL[1] Bit 0 R OCELL[0] ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Default 134 PM7322 RCMP-800 ...
Page 139
... The contents of these registers are valid within four OFCLK cycles after a transfer is triggered by a write to the Output Cell Count register space. ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Default 135 PM7322 RCMP-800 ...
Page 140
... All digital device inputs except SD[39:0] and SP[4:0] may be read and all digital device outputs except SD[39:0]. SP[4:0], SADSB, SRWB, SOEB and SA[19:0] may be forced via the JTAG test port. ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 136 ...
Page 141
... HIZDATA bit. The DBCTRL bit is used to measure the drive capability of the data bus driver pads. PMCTST: The PMCTST bit is used to configure the RCMP-800 for PMC's manufacturing ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 137 PM7322 RCMP-800 ...
Page 142
... ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 0x4A 0x5C 0x62 1 SD[15] 1 SD[14] 1 IPOLL SD[13] 1 SD[12] 1 IBUS8 CONG SD[11 ISOC SD[10 IPRTY[1] SD[ IPRTY[0] SD[ ICA[4] SD[ ICA[3] SD[ ICA[2] SD[ ICA[1] SD[4] 1 SD[3] 1 SD[2] 1 SD[1] 1 SD[0] 138 PM7322 RCMP-800 0x63 0x64 0x7A 0x7B SD[31] SD[30] SD[29] SD[28] SP[4] SD[27] SP[3] OBUS8 SD[26] SP[2] SD[25] SP[1] SD[24] SP[0] SD[23] SD[39] SD[22] SD[38] SD[21] SD[37] SD[20] SD[36] SD[19] SD[35] SD[18] SD[34] SD[17] SD[33] SD[16] SD[32] ORDENB ...
Page 143
... Manufacturer's identification code - 0CDH Device identification - 273220CDH ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Selected Instruction Register Codes, IR[2:0] Boundary Scan 000 Identification 001 Boundary Scan 010 Bypass 011 Bypass 100 Boundary Scan 101 Bypass 110 Bypass 111 139 PM7322 RCMP-800 ...
Page 144
... RSTB 71 INTB 70 DREQ 69 OTSEN 68:67 OBUS8 66 ORDENB 65:63 OCA 62 OFCLK 61 OSOC 60 ODATOEB (for ODAT[15:0], OSOC and OPRTY[1:0] 59 OPRTY[1:0] 58:43 ODAT[15:0] 42 BUSYB 41:35 CONG 34 HIZ* 140 PM7322 RCMP-800 Boundary Type Scan Register Bit 20:19 ...
Page 145
... The extension allows for the appending bytes of additional information. Figures 6 and 7 illustrate the 8 bit wide and 16 bit wide data structures. The length of the pre-pends and post-pends are independently programmable for each interface. ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 141 ...
Page 146
... ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Bit 7 Bit 0 Prepend 1 Prepend 2 Prepend X Cell Byte 1 H1 Cell Byte 2 H2 Cell Byte 3 H3 Cell Byte 4 H4 Total of Cell Byte 5* UDF Bytes Cell Byte 6 PAYLOAD1 Cell Byte 53 PAYLOAD48 Postpend 1 Postpend 2 Postpend Y 142 PM7322 RCMP-800 ...
Page 147
... Bit 7 Bit 0 Prepend 1 Prepend 2 Prepend X Cell Word Cell Word Cell Word 3* UDF1 UDF2 Cell Word 4 PAYLOAD1 PAYLOAD2 Cell Word 5 PAYLOAD3 PAYLOAD4 Cell Word 6 PAYLOAD5 PAYLOAD6 Cell Word 27 PAYLOAD47 PAYLOAD48 Postpend 1 Postpend 2 Postpend Y 143 PM7322 RCMP-800 Total Words ...
Page 148
... Device Configuration 64K x 18 64K x 18 64K x 18 64K x 18 64K x 18 64K x 18 64K x 18 32K x 36 64K x 18 64K x 18 64K x 18 144 PM7322 RCMP-800 Access Max. Time Frequency MHz MHz MHz MHz MHz ...
Page 149
... ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Function Specific Fields (45 octets) Don't care Don't care Don't care Don't care Time Stamp Don't care (4 octets) 145 PM7322 RCMP-800 Reserved Error Detection (6 bits) Code (10 bits) CRC-10 Don't care CRC-10 Don't care CRC-10 Don't care ...
Page 150
... Unused Delay Result Don't care Don't care (29 oct.) (4 oct.) Unused Don't care Don't care Don't care (4 octets) (29 octets) (4 oct.) Don't care 146 PM7322 RCMP-800 CRC-10 Don't care Block Error Lost/Misdelivered Result Cell Count (1 oct.) (2 octets) 000000 CRC-10 Delay Block Lost/ Result ...
Page 151
... ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Function Specific Fields (45 octets) all octets 6AH all octets 6AH all octets 6AH Time Stamp FFH (4 octets) 147 PM7322 RCMP-800 Reserved Error Detection (6 bits) Code (10 bits) 000000 CRC-10 000000 CRC-10 000000 CRC-10 ...
Page 152
... Loopback cells. These can be inserted through the Microprocessor Cell Interface. The microprocessor is responsible for coding all fields except the CRC-10. All generated OAM cells contain a correct Error Detection Code (EDC). ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 000000 Block Error Lost/Misdelivered Result (1 oct ...
Page 153
... That is, as two values are compared, starting with the MSB (most significant bit) and moving to the LSB (least significant bit), the two can ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 149 ...
Page 154
... VC Table Record via the Microprocessor RAM Address and Data registers (0x21 through 0x25). Care should be taken to set the following fields appropriately: All counts should be set to zero. The "PM0" field should be set to one. The "Extended Status" field should be set to 0x050. ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 150 ...
Page 155
... Perform a SRAM write (via the Microprocessor RAM Address and Data registers) to incorporate the new Secondary Search Table entry in the existing tree structure. This step must be performed last to ensure a binary search in progress is not corrupted. ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 151 ...
Page 156
... ROUTING CONTROL, MONITORING AND POLICING 800 Mbps BEFORE 0 - pointers to Secondary Search Table entries pointers to VC Table entries - "select" field contents BEFORE TABLE Ent r y 152 PM7322 RCMP-800 AFTER TABLE Ent r y AFTER ...
Page 157
... ROUTING CONTROL, MONITORING AND POLICING 800 Mbps BEFORE a k > n > TABLE Ent TABLE TABLE Ent r y Ent r y 153 PM7322 RCMP-800 AFTER TABLE Ent TABLE Ent r y ...
Page 158
... Ent r y ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps BEFORE > n > TABLE Ent TABLE Ent r y 154 PM7322 RCMP-800 AFTER TABLE Ent TABLE ...
Page 159
... ROUTING CONTROL, MONITORING AND POLICING 800 Mbps BEFORE a k > n > TABLE Ent TABLE TABLE Ent r y Ent r y 155 PM7322 RCMP-800 AFTER TABLE Ent TABLE Ent r y ...
Page 160
... VCs. A second Secondary Search Table entry needs to be allocated whose Left_Branch points to the existing VC Table Record. (Although not used suggested that the Right_Branch be set to all zeroes.) Set the ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 156 ...
Page 161
... TABLE ones Ent TABLE Ent ones TABLE Ent TABLE Ent r y 157 PM7322 RCMP-800 AFTER TABLE Ent ones ones 1 1 TABLE Ent r y ...
Page 162
... ROUTING CONTROL, MONITORING AND POLICING 800 Mbps AFTER x c ones ones 1 1 TABLE Ent TABLE Ent TABLE Ent r y 158 PM7322 RCMP-800 Tag as free ones TABLE Ent TABLE Ent r y ...
Page 163
... Fig. 8 Boundary Scan Architecture TDI TMS Test Access Port Controller TRSTB TCK ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Boundary Scan Register Device Identification Register Bypass Register Instruction Register and Decode Control Select Tri-state Enable 159 PM7322 RCMP-800 Mux DFF TDO ...
Page 164
... The TAP controller is a synchronous finite state machine clocked by the rising edge of primary input, TCK. All state transitions are controlled using primary input, TMS. The finite state machine is described below. ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 160 ...
Page 165
... Run-Test-Idle 0 ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 1 Select-DR-Scan 0 1 Capture-DR 0 Shift- Exit1-DR 0 Pause- Exit2-DR 1 Update- All transitions dependent on input TMS 161 PM7322 RCMP-800 1 Select-IR-Scan 0 1 Capture-IR 0 Shift- Exit1-IR 0 Pause- Exit2-IR 1 Update- ...
Page 166
... The new instruction must be scanned in using the Shift-IR state. The load occurs on the falling edge of TCK. The Pause-DR and Pause-IR states are provided to allow shifting through the test data and/or instruction registers to be momentarily paused. ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 162 ...
Page 167
... TDI and TDO. During the Capture-DR state, the device identification code is loaded into the boundary scan register. The code can then be shifted out output, TDO using the Shift-DR state. ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 163 ...
Page 168
... The internal test instruction is not fully implemented. When this instruction is the current instruction, the boundary scan register is connected between TDI and TDO. During the Capture-DR state, primary outputs are sampled and loaded into the boundary scan register. ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 164 ...
Page 169
... (n-2) •••• 165 PM7322 RCMP-800 Ignored if ICALEVEL0 bit = (n-1) (n) ...
Page 170
... Fig. 11 Input Cell Interface Address Line Polling Master Configuration (IPOLL=1) – Example 1 IFCLK (I) ICA[1] (I) CA(N+4) IWRENB[1] (O) IADDR[4:0] (O) N+4 1Fh IAVALID (O) ISOC (I) IDAT[15:0] ( (n-7) IPRTY[1:0] (I) ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps CA(N+5) CA(N+6) N+5 1Fh N+6 1Fh (n-6) (n-5) (n-4) (n-3) (n-2) (n-1) 166 PM7322 RCMP-800 CA(N+5) CA(N+6) N+5 1Fh N+6 1Fh (n) N ...
Page 171
... When a PHY device with an available cell is found, polling ceases and the PHY device is selected for transfer of the next cell. (If the PHY is found while a cell is ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps CA(N+8) CA(N+9) N+8 1Fh N+9 1Fh 1Fh (n-1) (n) 167 PM7322 RCMP-800 CA(N+8) CA(N+9) N+8 1Fh N+9 1Fh N+ ...
Page 172
... ISOC is sampled high during any byte other than the first byte of the data structure, an interrupt may be generated and the input cell write address counter is reset to the first byte of the data structure. ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 168 ...
Page 173
... ROUTING CONTROL, MONITORING AND POLICING 800 Mbps •••• •••• OCALEVEL0 = 0 •••• •••• invalid read, no data available •••• W(n-5) W(n-4) W(n-3) W(n-2) •••• 169 PM7322 RCMP-800 W(n- W(1) ...
Page 174
... ROUTING CONTROL, MONITORING AND POLICING 800 Mbps •••• •••• OCALEVEL0 = 0 •••• •••• invalid read, no data available •••• W(n-5) W(n-4) W(n-3) W(n-2) •••• 170 PM7322 RCMP-800 W(n-1) W(n) XX W(1) ...
Page 175
... Case Temperature under Bias Storage Temperature Supply Voltage Voltage on Any Pin Static Discharge Voltage Latch-Up Current DC Input Current Lead Temperature Absolute Maximum Junction Temperature ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps -40°C to +85°C -40°C to +125°C -0.5V to +6.0V -0. +0.5V DD ±1000 V ±100 mA ± ...
Page 176
... Max -0.5 0.8 2 +0.5 0.4 VDD -0.5V 3.5 0.6 1 +175 +350 +525 -10 +10 -10 +10 -10 +10 5 172 PM7322 RCMP-800 Units Conditions Volts Guaranteed Input LOW Voltage Volts Guaranteed Input HIGH Voltage Volts V = min mA Note 3 Volts V = min mA Note 3 Volts Volts Volts µ GND, Notes 1, 3 µ ...
Page 177
... Input pin or bidirectional pin with internal pull-up resistor. 2. Input pin or bidirectional pin without internal pull-up resistor 3. Negative currents flow into the device (sinking), positive currents flow out of the device (sourcing). ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps ...
Page 178
... RD tZ Valid Read Negated to Output Tristate RD tP Valid Read Asserted to DREQ Deasserted DREQ tZ Valid Read Negated to INTB Tristate INTH ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps = 5 V ±5%) DD 174 PM7322 RCMP-800 Min Max Units 10 (typ (typ ...
Page 179
... Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output. ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps tS AR Valid Address tS ALR DREQ tP RD 175 PM7322 RCMP-800 ALR INTH tZ RD Valid Data ...
Page 180
... Output tristate delay is the time in nanoseconds from the 1.4 Volt point of the reference signal to ±300mV of the termination voltage on the output. The test load 1.4V in parallel with GND. ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps , tV , and tS are not applicable. ALR L LR 176 PM7322 RCMP-800 ...
Page 181
... Fig. 16 Microprocessor Interface Write Timing A[6:0] ALE (CSB+WRB) D[15:0] ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Valid Address tS tH ALW ALW Valid Data 177 PM7322 RCMP-800 Min Max Units ...
Page 182
... When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock. ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps , tV , and tS are not applicable. ALW L LW 178 PM7322 RCMP-800 ...
Page 183
... IFCLK High to IADDR[4:0] Valid IADDR t P IFCLK High to IAVALID Valid IAVALID ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps = 5 V ±5 179 PM7322 RCMP-800 Min Max Units 52 MHz ...
Page 184
... RODUCT PMC-940904, ISSUE 6 ______________________________________________________________________________________________ Fig. 17 Input Cell Interface Master (IPOLL=0) Timing IFCLK ICA[4:1] IDAT[15:0] IPRTY[1:0] ISOC IWRENB[4:1] ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps tS tH ICA ICA tS tH IDAT IDAT tH tS IPRTY IPRTY tS tH ISOC ISOC tP IWRENB 180 PM7322 RCMP-800 ...
Page 185
... RODUCT PMC-940904, ISSUE 6 ______________________________________________________________________________________________ Fig. 18 Input Cell Interface Master (IPOLL=1) Timing IFCLK tS ICA[1] tS IDAT IDAT[15:0] tS IPRTY[1:0] tS ISOC IWRENB[1] IADDR[4:0] IAVALID ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps tH ICA ICA tH IDAT tH IPRTY IPRTY tH ISOC ISOC tP IWRENB tP IADDR tP IAVALID 181 PM7322 RCMP-800 ...
Page 186
... OFCLK High to OPRTY[1:0] Valid, OPRTY t P OFCLK High to Output Enable OFCLK t Z OFCLK High to Output Tristate OFCLK t P OFCLK High to OCA Valid, OCA ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Min ...
Page 187
... Fig. 19 Output Cell Interface Slave Timing OTSEN = 0: OFCLK ORDENB ODAT[15:0] OPRTY[1:0] OCA OSOC OTSEN = 1: OFCLK ORDENB ODAT[15:0] OPRTY[1:0] OSOC ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps tS tH ORDENB ORDENB tP ODAT tP OPRTY tP OCA tP OSOC tP tZ OFCLK OFCLK Valid Data 183 PM7322 RCMP-800 ...
Page 188
... N(Max. Search Tree Depth 17) ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps = 50pf 20pf L = 50pf 20pf 50pf 20pf 50pf 20pf L 1 184 PM7322 RCMP-800 Min Max Units 19.2 † ...
Page 189
... PMC-940904, ISSUE 6 ______________________________________________________________________________________________ Fig. 20 Synchronous SRAM Interface Timing SYSCLK t CYC SA[19:0] tP SADSB SADSB SOEB tP SRWB SRWB Valid RCMP SD[39:0], SP[4:0] ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps SADSB tP SOEB tP SRWB SD Data 185 PM7322 RCMP-800 tP SOEB Valid SRAM Data Out ...
Page 190
... TMS Set-up time to TCK TMS tH TMS Hold time to TCK TMS tS TDI Set-up time to TCK TDI tH TDI Hold time to TCK TDI t P TCK Low to TDO Valid TDO ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps Min 186 Max Units 6 MHz ...
Page 191
... S P TANDARD RODUCT PMC-940904, ISSUE 6 ______________________________________________________________________________________________ Fig. 21 JTAG Port Interface Timing TCK TMS TDI TCK TDO ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps tS tH TMS TMS tS tH TDI TDI tP TDO 187 PM7322 RCMP-800 ...
Page 192
... Output tristate delay is the time in nanoseconds from the 1.4 Volt point of the reference signal to ±300mV of the termination voltage on the output. The test load 1.4V in parallel with GND. ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 188 ...
Page 193
... P TANDARD RODUCT PMC-940904, ISSUE 6 ______________________________________________________________________________________________ ORDERING AND THERMAL INFORMATION PART NO. PM7322-SI PART NO. CASE TEMPERATURE PM7322-SI ______________________________________________________________________________________________ ROUTING CONTROL, MONITORING AND POLICING 800 Mbps DESCRIPTION 240 Slugged Plastic Quad Flat Pack (PQFP) -40°C to +85°C 189 PM7322 RCMP-800 Theta Ja Theta Jc 24 °C/W ...
Page 194
... Pin 1 Designator Hx STANDOFF NOTES: 1) ALL DIMENSIONS IN MILLIMETER. 2) DIMENSIONS SHOWN ARE NOMINAL A1 3) FOOT LENGTH "L" IS MEASURED AT C 0-7 DEG b LEAD COPLANARITY ccc C DETAIL 31.90 34.35 31.90 0.45 0.17 32.00 34.60 32.00 0.60 0.50 0.22 32.10 34.85 32.10 0.75 0.27 190 PM7322 RCMP-800 A Hy 8-12 DEG. 8-12 DEG. A2 WITH TOLERANCES AS INDICATED. GAGE PLANE, 0.25 ABOVE SEATING PLANE. Hy ccc Hx 24.20 24.20 0.10 ...
Page 195
... S P TANDARD RODUCT PMC-940904, ISSUE 6 ______________________________________________________________________________________________ NOTES ______________________________________________________________________________________________ PM7322 RCMP-800 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps 191 ...
Page 196
... Seller has knowledge of the possibility of such potential loss or damage and even if caused by Seller’s negligence. © 1997 PMC-Sierra, Inc. PMC-940904(R6) ref PMC-940903(A9) ______________________________________________________________________________________________ PMC-Sierra, Inc. ROUTING CONTROL, MONITORING AND POLICING 800 Mbps . Issue date: August, 1997 105-8555 Baxter Place, Burnaby, BC Canada V5A 4V7 604 415-6000 PM7322 RCMP-800 ...