RM5271-266S PMC-Sierra Inc, RM5271-266S Datasheet
RM5271-266S
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RM5271-266S Summary of contents
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... Cvt, Div, Sqrt QUANTUM EFFECT DEVICES, INC., 3255-3 SCOTT BLVD., SUITE 200, SANTA CLARA, CA 95054 PHONE 408.565.0300 RM5271™ Superscalar Microprocessor with External Cache Interface • High-performance floating point unit - up to 700 MFLOPS — Single cycle repeat rate for common single precision opera- tions and some double precision operations — ...
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... RM5271 provides unparalleled price/per- formance in computationally intensive embedded applica- tions. CPU Registers Like all MIPS ISA processors, the RM5271 CPU has a sim- ple, clean user visible state consisting of 32 general pur- General Purpose Registers 63 0 ...
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... Move-from-Hi and Move- from-Lo (MFHI/MFLO) instructions. In addition to the baseline MIPS IV integer multiply instruc- tions, the RM5271 also implements the multiply instruction, MUL. This instruction specifies that the multiply result go directly to the integer register file rather than the Lo regis- FAX 408 ...
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... Hi and Lo registers. The multiply-accumulate operation is the core primitive of almost all signal processing algorithms allowing the RM5271 to eliminate the need for a separate DSP engine in many embedded applications. By pipelining the multiply-accumulate function and dynami- cally determining the size of the input operands, the RM5271 is able to maximize throughput while still using an area efficient implementation ...
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... This mechanism is available to system software to provide a secure environment for user processes. Bits in the CP0 Status register determine which virtual addressing mode is used. In the user mode, the RM5271 provides a single, uni- form virtual address space of 256GB (2GB in 32-bit mode). When operating in the kernel mode, four distinct virtual ...
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... JTLB. The operation of the ITLB is completely transpar- ent to the user. Data TLB The RM5271 uses a 4-entry data TLB (DTLB) for the same reasons cited above for the ITLB. Each DTLB entry maps a 4KB page. The DTLB improves performance by allowing data address translation to occur in parallel with instruction address translation ...
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... MHz. For applications requiring even higher performance, the RM5271 also has a direct interface to a large external sec- ondary cache. Instruction Cache The RM5271 incorporates a two-way set associative on- chip instruction cache ...
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... Secondary Cache Like the RM5270 and R5000, the RM5271 has direct sup- port for an external secondary cache. The secondary cache is direct mapped and block write-through with byte parity protection for data ...
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... SysClock. per-byte Figure 6 shows a typical embedded system using the none RM5271. In this example, a bank of DRAMs, an optional secondary cache, and a memory controller ASIC share the processor’s SysAD bus while the memory controller pro- vides separate ports to a boot ROM and an I/O system. ...
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... SysCmd bus indicates the number of bytes being transferred. Handshake Signals There are six handshake signals on the system interface. Two of these, RdRdy* and WrRdy*, are used by an exter- nal device to indicate to the RM5271 whether it can accept SysClock Addr SysAD Read ...
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... Standby Mode The RM5271 provides a means to reduce the amount of power consumed by the internal core when the CPU would otherwise not be performing any useful operations. This state is known as Standby Mode. ...
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... RM5271™ Superscalar Microprocessor, with External Cache Interface typically inserted in the idle loop of the operating system or real time executive. JTAG Interface The RM5271 interface supports JTAG boundary scan in conformance with IEEE 1149.1. The JTAG interface is especially helpful for checking the integrity of the proces- sor’s pin connections. ...
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... PIN DESCRIPTIONS The following is a list of interface, interrupt, and miscellaneous pins available on the RM5271. Pin Name Type System interface: ExtRqst* Input External request Signals that the system interface is submitting an external request. Release* Output Release interface Signals that the processor is releasing the system interface to slave state ...
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... RM5271™ Superscalar Microprocessor, with External Cache Interface Pin Name Type ScMatch Input Secondary Cache Tag Match This signal is asserted by the cache Tag RAM’s when a match occurs between the value on its data inputs and the contents of its RAM at the value on its address inputs. ...
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... OUT QUANTUM EFFECT DEVICES, INC., 3255-3 SCOTT BLVD., SUITE 200, SANTA CLARA, CA 95054 PHONE 408.565.0300 RM5271™ Superscalar Microprocessor, with External Cache Interface 1 Rating should not exceed 3.9 Volts. IN Vss VccInt 0V 2.5V 5% I/O Bus Speed 50/67/75/83/87/100/125 MHz Minimum Maximum ...
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... RM5271™ Superscalar Microprocessor, with External Cache Interface POWER CONSUMPTION Parameter standby VccInt Power R4000 write protocol with no FPU operation active (mWatts) Write re-issue or pipelined writes with superscalar Parameter standby VccInt Power R4000 write protocol with no FPU operation active (mWatts) Write re-issue or pipelined writes with superscalar Conditions: Max: VccIO = 3 ...
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... ModeCKP JTAG Clock Period t JTAGCKP Note 6: 0peration of the RM5271 is only guaranteed with the Phase Lock Loop Enabled. QUANTUM EFFECT DEVICES, INC., 3255-3 SCOTT BLVD., SUITE 200, SANTA CLARA, CA 95054 PHONE 408.565.0300 RM5271™ Superscalar Microprocessor, with External Cache Interface 200 MHz ...
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... RM5271™ Superscalar Microprocessor, with External Cache Interface System Interface Parameters Parameter Symbol Test Conditions mode14.. (fastest) mode14.. 8,9 t Data Output DO mode14.. mode14.. (slowest) 1 Data Setup t = see above table DS rise t = see above table 10 t Data Hold fall ...
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... SysClock System Interface Timing (SysAD, SysCmd, ValidIn*, ValidOut*, etc.) SysClock Data SysClock Data QUANTUM EFFECT DEVICES, INC., 3255-3 SCOTT BLVD., SUITE 200, SANTA CLARA, CA 95054 PHONE 408.565.0300 RM5271™ Superscalar Microprocessor, with External Cache Interface t t High Low t t Fall Rise ...
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... RM5271™ Superscalar Microprocessor, with External Cache Interface PACKAGING INFORMATION 304 SBGA Drawing ball corner 10 mm dia ink mark Body Size Symbol Min. A 1.41 A1 0. 30.90 D1, E1 27. aaa bbb ccc ddd 0.15 P 0.20 S Theta JC Theta JA 20 QUANTUM EFFECT DEVICES, INC., 3255-3 SCOTT BLVD., SUITE 200, SANTA CLARA, CA 95054 PHONE 408 ...
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... P21 Note: Pins marked Reserved are for RM7000 compatibility. Do not connect to any signal or power planes. QUANTUM EFFECT DEVICES, INC., 3255-3 SCOTT BLVD., SUITE 200, SANTA CLARA, CA 95054 PHONE 408.565.0300 RM5271™ Superscalar Microprocessor, with External Cache Interface Function Pin Function VssIO ...
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... RM5271™ Superscalar Microprocessor, with External Cache Interface Pin Function Pin R1 SysAD46 R2 R20 VccIO R21 T1 VssIO T2 T20 ExtRqst* T21 U1 Reserved U2 U20 VccInt U21 V1 VssIO V2 V20 VccIO V21 W1 JTDI W2 W20 VccIO W21 Y1 Do Not Connect Y2 Y5 VccIO Y6 Y9 VccIO Y10 Y13 SysCmd5 ...
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... Valid Combinations RM5271-200S RM5271-225S RM5271-250S RM5271-266S RM5271-300S RM5271-350S This document may, wholly or partially, be subject to change without notice. Quantum Effect Devices, Inc. reserves the right to make changes to its products or specifications at any time without notice, in order to improve design or performance and to supply the best possible product. ...