PM8354-NI PMC-Sierra Inc, PM8354-NI Datasheet
PM8354-NI
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... CHANNEL PHYSICAL LAYER TRANSCEIVER WITH GIGABIT ETHERNET PCS AND TRUNKING FOR 933 Mbit/s TO 1.25 Gbit/s INTERFACES Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2012433, Issue 4 QuadPHY 1G ASSP Telecom Standard Product Data Sheet PM8354 ® QuadPHY 1G Data Sheet Released Issue No ...
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Legal Information Copyright Copyright 2003 PMC-Sierra, Inc. All rights reserved. The information in this document is proprietary and confidential to PMC-Sierra, Inc., and for its customers’ internal use. In any event, no part of this document may be reproduced or ...
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Contacting PMC-Sierra PMC-Sierra 8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: +1 (604) 415-6000 Fax: +1 (604) 415-6200 Document Information: Corporate Information: Technical Support: apps@pmc-sierra.com Web Site: http://www.pmc-sierra.com Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal ...
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Revision History Issue No. Issue Date 1 July 2001 2 June 2002 Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2012433, Issue 4 QuadPHY 1G ASSP Telecom Standard Product Data Sheet Details of Change ...
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Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2012433, Issue 4 QuadPHY 1G ASSP Telecom Standard Product Data Sheet Updated MDC/MDIO Read Cycle Figure so that Opcode is 10. Added information in MDC/MDIO Interface ...
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March 2003 Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2012433, Issue 4 QuadPHY 1G ASSP Telecom Standard Product Data Sheet Added TMS note to TAP Controller Finite State Machine Figure. Changed item ...
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June 2003 Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2012433, Issue 4 QuadPHY 1G ASSP Telecom Standard Product Data Sheet description to show differences between rev A and rev B devices. - ...
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Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2012433, Issue 4 QuadPHY 1G ASSP Telecom Standard Product Data Sheet - Changed all references of 1.0 Gbit/s to 933 Mbit/s. - Added note 4 to ...
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Table of Contents Legal Information........................................................................................................................... 2 Copyright................................................................................................................................. 2 Disclaimer ............................................................................................................................... 2 Trademarks ............................................................................................................................. 2 Patents 2 Contacting PMC-Sierra.................................................................................................................. 3 Revision History............................................................................................................................. 4 Table of Contents........................................................................................................................... 9 List of Registers........................................................................................................................... 11 List of Figures .............................................................................................................................. 12 List of Tables................................................................................................................................ 14 1 ...
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Packet Generator and Packet Comparator ............................................................. 126 12.2 JTAG Test Access Port............................................................................................ 128 13 Operation ............................................................................................................................ 130 13.1 Power-up ................................................................................................................. 130 13.2 Parallel Interface ..................................................................................................... 130 13.3 High-Speed Serial Interface .................................................................................... 131 13.4 Clock Requirements ................................................................................................ 132 13.5 Hardware/Software ...
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List of Registers Register 0x00: GMII Control ........................................................................................................ 82 Register 0x01: GMII Status ......................................................................................................... 85 Register 0x02: GMII PHY Identifier 1 .......................................................................................... 88 Register 0x03: GMII PHY Identifier 2 .......................................................................................... 90 Register 0x04: GMII Auto-Negotiation Advertisement ................................................................ 91 Register 0x05: ...
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List of Figures Figure 1 QuadPHY 1G in Switch/Router Applications .............................................................. 21 Figure 2 IEEE 802.3-2000 Gigabit Ethernet Supported Functions ........................................... 22 Figure 3 QuadPHY 1G Block Diagram...................................................................................... 23 Figure 4 QuadPHY 1G Detailed Channel Block Diagram ......................................................... 25 Figure ...
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Figure 43 Recommended Power Supply Decoupling ............................................................. 140 Figure 44 QuadPHY 1G Reset Timing .................................................................................... 144 Figure 45 MDIO Timing Diagram ............................................................................................ 144 Figure 46 MDIO Sourced by PHY ........................................................................................... 145 Figure 47 JTAG Port Interface Timing..................................................................................... 146 Figure 48 ...
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List of Tables Table 1 Definitions..................................................................................................................... 16 Table 2 Receive Path Pins ........................................................................................................ 27 Table 3 Transmit Path Pins ....................................................................................................... 30 Table 4 MDC/MDIO Pins ........................................................................................................... 32 Table 5 Configuration/Status Pins............................................................................................. 33 Table 6 JTAG Pins .................................................................................................................... 35 Table 7 ...
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Table 35 Transmit Latency Timing .......................................................................................... 150 Table 36 High-speed I/O Characteristics (V Table 37 Gigabit Ethernet Jitter Specifications Table 38 Fibre Channel Jitter Specifications Table 39 Outside Plant Thermal Information .......................................................................... 154 Table 40 Device Compact Model ............................................................................................ 154 ...
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Definitions The following table defines terms and abbreviations used in this document. Table 1 Definitions Term ANSI ASIC BIST CABGA CMOS COL CRS DDR FIFO GMII IEEE IPG JTAG MDC/MDIO PCS Proprietary and Confidential to PMC-Sierra, Inc., and for ...
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Features General · Four 933 Mbit/s to 1.25 Gbit/s IEEE 802.3-2000 Gigabit Ethernet and Fibre Channel Physical Interfaces (FC-PI) System Compliant Transceivers · Four secondary channels to support channel redundancy · Configurable as four independent channels ...
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Test Features · IEEE 1149.1 JTAG Boundary Scan support · Built-in self-test (BIST) via internal packet generator/checker · Per-channel control of serial and parallel loopback · 8B/10B error counters Physical · Thermally enhanced 289-pin, 19mm x 19mm CABGA Package Proprietary ...
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Applications · High-speed serial backplanes · IEEE 802.3-2000 Gigabit Ethernet dense line cards · ANSI X3T11 Fibre Channel dense line cards · Link Aggregation · Intra-system and inter-system interconnect · Chassis Extender Proprietary and Confidential to PMC-Sierra, Inc., and ...
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References 1. IEEE 802.3-2000 Gigabit Ethernet, 2000 Edition 2. Methodologies for Jitter and Signal Quality Specification (MJSQ) Rev. 4.0 3. Fibre Channel Physical Interfaces (FC-PI) Rev IEEE 1149.1-2001 Standard Test Access Port and Boundary Scan Architecture, 23 ...
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... MAC QuadPHY 1G Parallel Parallel HS Serial I/F I/F I/F • 1.25 Gbit/s Serial • Backplane Links • 4-Port GE Line Card # n PM8354 MAC QuadPHY 1G Parallel Parallel HS Serial I/F I/F I/F Released Protect Switch Card Working Switch Card PM8354 QuadPHY 1G PM8354 QuadPHY 1G Switch Fabric • • • PM8354 QuadPHY 1G Parallel I/F 21 ...
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IEEE 802.3-2000 Gigabit Ethernet Transceiver As a Gigabit Ethernet Transceiver, the QuadPHY 1G integrates the PCS layer down to the PMA layer for fiber mediums and down to the PMD layer for copper mediums. Figure 2 shows in gray ...
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Block Diagram The block diagram of the QuadPHY 1G is shown in Figure 3. Figure 3 QuadPHY 1G Block Diagram TXDA[9:0] TXCKA TXDB[9:0] TXCKB TXDC[9:0] TXCKC TXDD[9:0] TXCKD RBCA0 RXDA[9:0] RxFIFO RBCA1 RBCB0 RXDB[9:0] RxFIFO RBCB1 RBCC0 RXDC[9:0] RxFIFO ...
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... The QuadPHY 1G provides redundant serial transmit and serial receive ports. The active port can be selected through the Management Interface for each pair of transmit and receive ports. The PM8354 has four primary channels and 4 secondary channels (A to D). Figure 4 shows a detailed block diagram of channel A’s primary and secondary channels. The block diagrams of channels B, C, and D are identical to channel A’ ...
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Figure 4 QuadPHY 1G Detailed Channel Block Diagram TXDA[9:0] TXCKA FIFO RXDA[9:0] RBCA0 RBCA1 LOC_CLK The QuadPHY 1G supports IEEE 802.3-2000 Gigabit Ethernet and Fibre Channel Physical Interfaces (FC-PI) Rev. 13. The high-speed outputs feature programmable output current that enables ...
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Pin Diagram The QuadPHY 1G is packaged in a 289-ball Chip Array Ball Grid Array (CABGA) package having a body size mm. Figure 5 shows the bottom view of the pin diagram of the ...
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Pin Description The following tables describe all pins of the QuadPHY 1G. Table 2 Receive Path Pins Pin Name Type SRDIA_P Input SRDIA_N High-speed Differential PRDIA_P PRDIA_N SRDIB_P SRDIB_N PRDIB_P PRDIB_N SRDIC_P SRDIC_N PRDIC_P PRDIC_N SRDID_P SRDID_N PRDID_P PRDID_N ...
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Pin Name Type RXDA[9] Output RXDA[8] CMOS RXDA[7] RXDA[6] RXDA[5] RXDA[4] RXDA[3] RXDA[2] RXDA[1] RXDA[0] RBCB0 Output CMOS RBCB1 Output CMOS RXDB[9] Output RXDB[8] CMOS RXDB[7] RXDB[6] RXDB[5] RXDB[4] RXDB[3] RXDB[2] RXDB[1] RXDB[0] Proprietary and Confidential to PMC-Sierra, Inc., and ...
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Pin Name Type RBCC0 Output CMOS RBCC1 Output CMOS RXDC[9] Output RXDC[8] CMOS RXDC[7] RXDC[6] RXDC[5] RXDC[4] RXDC[3] RXDC[2] RXDC[1] RXDC[0] RBCD0 Output CMOS RBCD1 Output CMOS Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document ...
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Pin Name Type RDDD[9] Output RXDD[8] CMOS RXDD[7] RXDD[6] RXDD[5] RXDD[4] RXDD[3] RXDD[2] RXDD[1] RXDD[0] Table 3 Transmit Path Pins Pin Name Type STDOA_P Output STDOA_N High-speed Differential PTDOA_P PTDOA_N STDOB_P STDOB_N PTDOB_P PTDOB_N STDOC_P STDOC_N PTDOC_P PTDOC_N STDOD_P STDOD_N ...
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Pin Name Type TXDA[9] Input TXDA[8] CMOS TXDA[7] TXDA[6] TXDA[5] TXDA[4] TXDA[3] TXDA[2] TXDA[1] TXDA[0] TXCKB Input CMOS TXDB[9] Input TXDB[8] CMOS TXDB[7] TXDB[6] TXDB[5] TXDB[4] TXDB[3] TXDB[2] TXDB[1] TXDB[0] TXCKC Input CMOS Proprietary and Confidential to PMC-Sierra, Inc., and ...
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Pin Name Type TXDC[9] Input TXDC[8] CMOS TXDC[7] TXDC[6] TXDC[5] TXDC[4] TXDC[3] TXDC[2] TXDC[1] TXDC[0] TXCKD Input CMOS TXDD[9] Input TXDD[8] CMOS TXDD[7] TXDD[6] TXDD[5] TXDD[4] TXDD[3] TXDD[2] TXDD[1] TXDD[0] Table 4 MDC/MDIO Pins Pin Name Type DVAD4 Input DVAD3 ...
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Pin Name Type MDIO Input/Output CMOS MDC Input CMOS Table 5 Configuration/Status Pins Pin Name Type CV_DIS_EN Input CMOS DEC_ENC_EN Input CMOS EN_SLPBK Input CMOS SMRESET Input Pulldown CMOS Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal ...
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Pin Name Type INS_DEL_DIS Input Pulldown CMOS ENPLPBK Input Pulldown CMOS GEMOD Input Pulldown CMOS BMOD Input Pulldown CMOS MODE1 Input MODE0 CMOS Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2012433, Issue 4 ...
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Pin Name Type REFCLK Input CMOS PLL_LOCK Output CMOS RESET Input CMOS Table 6 JTAG Pins Pin Name Type TCK Input CMOS TDI Input CMOS Pullup TMS Input Pullup CMOS TRSTB Input CMOS TDO Output Tristate CMOS Proprietary and Confidential ...
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Table 7 Miscellaneous Pins Pin Name Type NC No Connect POEN Input CMOS NC Input Pulldown CMOS RPRES Analog Bias Table 8 Digital Power and Digital Ground Pins Pin Name Type VDD Power Digital Core Proprietary and Confidential to PMC-Sierra, ...
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Pin Name Type VDDQ Power Digital I/O Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2012433, Issue 4 QuadPHY 1G ASSP Telecom Standard Product Data Sheet Pin Function No. E9 Digital I/O power. E8 ...
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Pin Name Type GND Ground Digital Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2012433, Issue 4 QuadPHY 1G ASSP Telecom Standard Product Data Sheet Pin Function No. E4 Digital ground ...
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Pin Name Type T_GND Ground Digital Thermal Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2012433, Issue 4 QuadPHY 1G ASSP Telecom Standard Product Data Sheet Pin Function No. F6 Thermal ground. Used as ...
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Table 9 Analog Power and Ground Pins Pin Name Type VDDA Power Analog GNDA Ground Analog Notes: 1. All QuadPHY 1G inputs and bi-directionals present minimum capacitive loading and operate at CMOS logic levels. 2. Digital and analog ground pins ...
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Functional Description 10.1 Modes of Operation The QuadPHY 1G has five modes of operation: · Locally Referenced Receive Clock (LRRC) Mode · Trunking Mode · Remotely Referenced Receive Clock (RRRC) Mode · Half-rate Receive Clock (HRRC) Mode · Parallel ...
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Locally Recovered Receive Clock (LRRC) Mode LRRC Mode uses the Receive FIFOs to transfer data from the recovered clock domain to the local (REFCLK) clock domain on all four channels. To activate this mode, the MODE pins must be ...
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Table 10 LRRC Mode Options LRRC Mode (MODE[1:0] = 00) Channel data are sampled on the positive edge of RBCD1 and TXCK. One 10-bit data port supports a single channel With frequency compensation Receive RXDY[7:0] = 8-bit data ...
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Trunking Mode Trunking Mode operation is identical to LRRC Mode, except that it also compensates for differences in wire length between channels and allows the QuadPHY 1G to appear to operate as a single 4 Gbit/s logical channel (when ...
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Table 11 Trunking Mode Options Trunking Mode (MODE[1:0] = 01) Trunking aligns all four lanes to create a high bandwidth data channel. A 10-bit parallel port services each lane. Data for each lane is sampled on the rising of RBCD1 ...
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Figure 7 RRRC Mode Receive Data Path SERIAL IN PRIMARY CHANNEL Y (PRDIY) SERIAL IN SECONDARY CHANNEL Y (SRDIY) Table 12 defines the Mode Options for RRRC Mode. The INS_DEL_DIS is automatically disabled while in RRRC Mode. To activate this ...
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... The internal 8B/10B Encoder/Decoder and the PCS Logic must be disabled while operating in HRRC Mode. When PCS logic is disabled the PM8354 will not keep track of even and odd byte locations. If the interfacing logic is implementing the PCS functions this logic will also have to keep track of even and odd byte locations as commas are expected to be sent in even byte locations ...
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Figure 8 Receive Data Path for HRRC Mode SERIAL IN PRIMARY CHANNEL Y (PRDIY) SERIAL IN SECONDARY CHANNEL Y (SRDIY) Table 13 defines the Mode Options for HRRC Mode. The INS_DEL_DIS is automatically disabled while in HRRC Mode. To activate ...
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Figure 9 Parallel Loopback Data Path TXDy[9:0] TXCKy RXDy[9:0] REC_CLK RBCy LOC_CLK The QuadPHY 1G is configured into parallel loopback via the MDC/MDIO management registers. Any of the configurations described in the LRRC or Trunking Mode sections can also be ...
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It is important to note that during internal serial data loopback testing, channel loopback enable bits in the Loopback control register must be coordinated with the redundancy control register’s channel select bits so that transmit primary and secondary channels are ...
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Table 14 Valid K Bit Values K-Bit Valid 9-bit Value (hex) K28.0 0x11C K28.1 0x13C K28.2 0x15C K28.3 0x17C K28.4 0x19C K28.5 0x1BC K28.6 0x1DC K28.7 0x1FC K23.7 0x1F7 K27.7 0x1FB K29.7 0x1FD K30.7 0x1FE Note: 1. Refer to Table ...
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Table 15 Example REFCLK and PLL Clock Combinations REFCLK Frequency 93.3 MHz 106.25 MHz 125 MHz 10.3.3 Transmit Path The QuadPHY 1G contains four transmit channels. Each channel consists of a SDR Parallel Interface, Transmit FIFO, Transmit PCS, 8B/10B Encoder, ...
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Figure 11 Transmit Timing TXDy[9:0] The device may be configured so that each TXDy port has it’s own clock or so that all four share a common clock. When the TXCLK4 bit in PMC Control 2 Register is set to ...
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Table 16 Parallel Transmit Interface Pin Mapping TXDy9 TXDy8 TXDy7 TXDy6 TXDy5 TXDy4 TXDy3 TXDy2 TXDy1 TXDy0 Transmit FIFO The Transmit FIFO is a 6-word by 10-bit FIFO that transfers data from the TXCKy domain to the internal clock domain ...
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Encoder When enabled, the encoder accepts an 8-bit word plus the k-bit and encodes these bits into a 10- bit parallel code. The encoder generates a running disparity for its own use in generating sub- blocks of 6- and ...
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Figure 12 Receive Channel Functional Blocks RXDy[9:0] REC_CLK RBCy LOC_CLK Each channel’s CDRU, comma detection and byte alignment logic run independently. The comma detection logic is programmable to detect +comma, -comma, or both. The decoded words with K bits are ...
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Clock and Data Recovery A 933 Mbit/s to 1.25 Gbit/s receive clock is extracted from the 10-bit coded serial data stream independently on each channel. The data rate of the received serial bit stream should be between 933 Mbit/s and ...
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Byte Alignment and Synchronization The character alignment logic searches the coded incoming serial stream for a sequence defined in IEEE 802.3-2000 as a comma. A comma is the sequence 0011111 or its complement and is unique in valid 10B coded ...
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Figure 13 Byte Synchronization State Machine bs!=comma (comma = K28.5 or K28.1 or K28. invalid bs_invalid bs_invalid bs=valid SYNC_ACQ_1 byte_align_stat=1 bs=invalid 1 SYNC_ACQ_2 good_cgs=0 bs=invalid 2 SYNC_ACQ_3 good_cgs=0 bs=invalid SYNC_ACQ_4 good_cgs=0 bs=invalid Proprietary and Confidential to PMC-Sierra, Inc., ...
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Decoder When enabled, each receive channel decodes incoming data into an 8-bit data byte and an associated control bit called the k-bit. Information is routed and processed internally in this 9-bit parallel form. The decoder monitors for proper disparity ...
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Register 0x19 is not cleared. Additional information on PCS and GMII can be found in IEEE 802.3 sections 35 and 36. Receive FIFO The Receive FIFO transfers data from the recovered clock domain to the internal clock domain that is ...
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The alternate IDLE sequence registers, IDLE1A and IDLE2A, are available for applications that make use of multiple idle sequences to indicate system conditions. An example of this would be flow control. One IDLE sequence might indicate clear to send while ...
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Figure 15 Trunking Mode Channel Alignment using Alignment Characters Channel Channel H Data Containing Alignment Characters Received ...
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While operating in the idle-data transition mode, frames should not be sent more often then every 16 columns or 128 bytes (including the IPG). This guarantees that there is enough separation between transitions so that a false realignment will not ...
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Figure 17 Insertion of a Column of Idle Sequences when Trunking Channel A Channel H Channel A Channel H Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2012433, Issue 4 QuadPHY 1G ASSP Telecom ...
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Figure 18 Deletion of a Column of Idle Sequences when Trunking Channel A Channel H Channel A Channel H Maximum Size Packets Supported Internal logic within the QuadPHY 1G establishes a relationship between the frequency at which serial data is ...
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These same FIFOs are used to eliminate the skew between lanes when in trunking mode. Lane skew is defined as the difference in time between the most delayed lane to the least delayed lane. For convenience, lane skew is measured ...
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Figure 19 Deskew State Machine Condition A : Received data or unaligned A characters. Condition B: Received correctly aligned A characters. Condition C: Received data, not unaligned A characters. Condition D: Received unaligned A characters. Condition ...
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A subset of the four lanes provided by QuadPHY 1G can be trunked by disabling the undesired channels’ ENABLE_CHN_[D:A] bits in PMC Control Register 1. 10.3.6 Gigabit Ethernet and PCS Operating Modes PCS_ENABLE (bit 2 in Register 0x11h) is used ...
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In RRRC Mode, the parallel receive pins are configured in SDR mode. The receive clocks are derived from the remote reference clock of each remote transmitter. A full rate receive clock (RBCD1, RBCC1, RBCB1, RBCA1) is used as a reference ...
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If the frequency of the recovered clock is the same as the local clock (i.e., a synchronous system), the insert/delete function of the receive FIFO can be disabled. In this case both the local receiver and the remote transmitter must ...
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Table 18 Parallel Receive Interface Pin Mapping RXDy9 RXDy8 RXDy7 RXDy6 RXDy5 RXDy4 RXDy3 RXDy2 RXDy1 RXDy0 10.4 JTAG Test Access Port The QuadPHY 1G supports the IEEE Boundary Scan Specification as described in the IEEE 1149.1 standards. The JTAG ...
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Figure 23 Boundary Scan Architecture TDI TMS TRSTB TCK The boundary scan architecture consists of a TAP controller, an instruction register with instruction decode, a bypass register, a device identification register and a boundary scan register. The TAP controller interprets ...
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Figure 24 TAP Controller Finite State Machine TRSTB=0 Test-Logic-Reset 1 0 Run-Test-Idle 0 Note: 1. TRSTB must be set to a logic 1 in order to transition out of the Test-Logic-Reset State. 2. The value shown adjacent to each state ...
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Test-Logic-Reset The test logic reset state is used to disable the TAP logic when the device is in normal mode operation. The state is entered asynchronously by asserting input, TRSTB. The state is entered synchronously regardless of the current TAP ...
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Boundary Scan Instructions The following is an description of the standard instructions. Each instruction selects a serial test data register path between input, TDI and output, TDO. BYPASS The bypass instruction shifts data from input, TDI to output, TDO ...
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Microprocessor Interface The QuadPHY 1G implements a management interface that uses a protocol defined in IEEE 802.3. This two-wire interface is used for configuration, control and status eight QuadPHY 1G devices and consists of MDC (management ...
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Figure 25 Register Access MDC PHYAD[4:2] FSM MDIO REGAD PHYAD[1:0] [4:0] Register Address Decode 32 Frames transmitted on the management interface have the frame structure shown in. The order of bit transmission is from left to right. Proprietary and Confidential ...
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Table 19 Management Interface Frame Format PRE ST READ 1 .... 1 01 WRITE 1 .... 1 01 PRE (Preamble the beginning of each transaction, the management interface controller sends a sequence of 32 contiguous logic 1 bits ...
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Figure 26 Behavior of MDIO During TA Field of a Read Transaction MDC MDIO DATA - 16-bit field. The first data bit transmitted and received is bit 15 (MSB) of the register being addressed. IDLE – logic state on MDIO ...
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Address Register (Hex) 0x17 Trunking Control 0x18 PMC Control 3 0x19 Auto-Negotiation Status 1 0x1A Auto-Negotiation Status 2 0x1B Packet Generator/Checker Control/Status 0x1C Packet Generator Count Control 0x1D Redundancy Control Register 0x1E Reserved/PMC Test 1 0x1F Reserved/PMC Test 2 Note: ...
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Normal Mode Register Description Normal mode registers are used to configure and monitor the operation of the QuadPHY 1G. Notes on Normal Mode Register Bits: 1. Writing values into unused register bits has no effect. However, to ensure software ...
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SPEED_SELECTION_MSB The SPEED_SELECTION_MSB bit is used in conjunction with the SPEED_SELECTION_LSB bit (bit 13) to select the speed of operation. Since the QuadPHY 1G only supports 1000Mbps operation, the SPEED_SELECTION_MSB is a read only bit that is always set to ...
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AN_ENABLE The Auto-Negotiation process is enabled by setting the AN_ENABLE bit to a logic 1. If the AN_ENABLE bit is enabled, the Speed Select and Duplex Mode bits have no effect on the link configuration other then providing status. If ...
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Register 0x01: GMII Status Bit Type Bit 15 R Bit 14 R Bit 13 R Bit 12 R Bit 11 R Bit 10 R Bit 9 R Bit 8 R Bit 7 R Bit 6 R Bit 5 R Bit ...
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LINK_STATUS When the LINK_STATUS bit is read as a logic 1, it indicates that the QuadPHY 1G has determined that a valid link has been established. When read as a logic 0, it indicates that the link is not valid. ...
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The QuadPHY 1G does not support full duplex link transmission and reception using the 100BASE-T2 signaling specification. Therefore, this bit returns a logic 0 when read. 10MBS_HALF_DUPLEX The QuadPHY 1G does not support half duplex link transmission and reception ...
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Register 0x02: GMII PHY Identifier 1 Bit Type Bit 15 R Bit 14 R Bit 13 R Bit 12 R Bit 11 R Bit 10 R Bit 9 R Bit 8 R Bit 7 R Bit 6 R Bit 5 ...
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Each octet is represented as a conventional two digit hexadecimal numeral where the first (left-most) digit of the pair is the more significant. The mapping of the OUI to the GMII PHY Identifier registers of the QuadPHY 1G is described ...
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Register 0x03: GMII PHY Identifier 2 Bit Type Bit 15 R Bit 14 R Bit 13 R Bit 12 R Bit 11 R Bit 10 R Bit 9 R Bit 8 R Bit 7 R Bit 6 R Bit 5 ...
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Register 0x04: GMII Auto-Negotiation Advertisement Bit Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 The GMII ...
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REMOTE_FAULT[1:0] The QuadPHY 1G device’s remote fault condition is encoded in bits 13:12 of the base page. Values are shown in Remote Fault Encoding Table shown below. The default value is 0x00b. The QuadPHY 1G ...
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Register 0x05: GMII Auto-Negotiation Link Partner Ability Base Page Bit Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 ...
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REMOTE_FAULT[1:0] The Link Partner’s remote fault condition is encoded in bits 13:12 of the base page. Values are shown in Remote Fault Encoding Table shown below. The default value is 0x00b. The Link Partner indicates ...
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Register 0x06: GMII Auto-Negotiation Expansion Bit Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Notes: 1. ...
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Register 0x07: GMII Auto-Negotiation Next Page Transmit Bit Type Bit 15 R/W Bit 14 R Bit 13 R/W Bit 12 R/W Bit 11 R Bit 10 R/W Bit 9 R/W Bit 8 R/W Bit 7 R/W Bit 6 R/W Bit ...
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MESSAGE_PAGE The MESSAGE_PAGE bit is used by the Next Page function to differentiate a Message Page from an Unformatted Page. The MESSAGE_PAGE bit is set as follows: Logic 0 = Unformatted Page. Logic 1 = Message Page. NEXT_PAGE The NEXT_PAGE ...
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Register 0x08: GMII Auto-Negotiation Link Partner Next Page Ability Bit Type Bit 15 R Bit 14 R Bit 13 R Bit 12 R Bit 11 R Bit 10 R Bit 9 R Bit 8 R Bit 7 R Bit 6 ...
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Logic 1 = will comply with message. MESSAGE_PAGE The MESSAGE_PAGE bit is used by the Next Page function to differentiate a Message Page from an Unformatted Page. The MESSAGE_PAGE bit is set as follows: Logic 0 = Unformatted Page. Logic ...
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Register 0x09 through 0x0E: Reserved Bit Type Bit 15 R Bit 14 R Bit 13 R Bit 12 R Bit 11 R Bit 10 R Bit 9 R Bit 8 R Bit 7 R Bit 6 R Bit 5 R ...
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Register 0x0F: GMII Extended Status Bit Type Bit 15 R Bit 14 R Bit 13 R Bit 12 R Bit 11 R Bit 10 R Bit 9 R Bit 8 R Bit 7 R Bit 6 R Bit 5 R ...
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PMC-Sierra Specific Registers Register 0x10: PMC Control 1 Bit Bit 15 R/W Bit 14 R Bit 13 R/W Bit 12 R Bit 11 R/W Bit 10 R Bit 9 R/W Bit 8 R Bit 7 R/W Bit 6 R/W ...
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COMMA_DETECT_SEL[1:0] These bits enable positive, negative, or both positive and negative comma detection. When COMMA_DETECT_SEL[1] is set to 1, positive comma detection is enabled. Setting COMMA_DETECT_SEL[ enables negative comma detection. ENABLE_CHN_A through D The ENABLE_CHN bit enables or ...
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Register 0x11: PMC Control 2 Bit Type Bit 15 R/W Bit 14 R/W Bit 13 R/W Bit 12 R/W Bit 11 R/W Bit 10 R/W Bit 9 R/W Bit 8 R/W Bit 7 R/W Bit 6 R/W Bit 5 R/W ...
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SOFT_RESET Soft Reset (Active High). This bit resets all the logic and state machines in the receive and transmit channels to their original state. This PLL, configuration and status register bits are not affected by the assertion of this bit. ...
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IPOEN The IPOEN bit controls the Internal Parallel Output Enable. This bit is logically ANDed with the POEN input terminal set to logic 1 the Parallel Outputs are enabled. CODE_VIOL_DIS_ENABLE The CODE_VIOL_DIS_ENABLE bit controls if the Internal ...
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Register 0x12: IDLE 1 Bit Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 The PMC IDLE ...
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Register 0x13: IDLE 2 Bit Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 The PMC IDLE ...
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Register 0x14: IDLE 1A Bit Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 The PMC IDLE_1A ...
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Register 0x15: IDLE 2A Bit Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 The PMC IDLE ...
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Register 0x16: Loopback Control Bit Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 The PMC Loopback ...
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The EN_PRI_SERIAL_LPBK_A:D and EN_SEC_SERIAL_LPBK_A:D bits are logically OR with the input terminal EN_SLPBK. Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2012433, Issue 4 QuadPHY 1G ASSP Telecom Standard Product Data Sheet Released 112 ...
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Register 0x17: Trunking Control Bit Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Notes: 1. This ...
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DESKEW_STATUS The DESKEW_STATUS bit when 0 indicates that the deskew state machine within the receive trunking logic has determined that word alignment across channels has been lost. This failure indication will be sustained until register 23 is read even if ...
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Register 0x18: PMC Control 3 Bit Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Notes: 1. ...
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RXCLK4 The RXCLK4 bit controls the enabling of the Receive Clocks while operating in LRRC, Trunking or Parallel Loopback Modes. If set to logic 1, the RBCD0 clock is output on the RBCA0, RBCB0, and RBCC0 pins and RBCD1 is ...
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A_CHAR_EN The A_CHAR_EN bit enables or disables the use of an Alignment Character to align data across channels. When the QuadPHY Trunking Mode and the A_CHAR_EN bit is set to a logic 1, the Trunking Control Register’s ...
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Register 0x19: Auto-Negotiation Status 1 Bit Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Notes: 1. ...
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Register 0x1A: Auto-Negotiation Status 2 Bit Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Notes: 1. ...
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Register 0x1B: Packet Generator/Checker Control/Status Bit Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Notes: 1. ...
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RXFIFO_RESYNC When 1, the RXFIFO_RESYNC bit indicates that the Receive FIFO within the channel has resynchronized its read and write pointers to avoid pointer collision. This resync indication will be sustained until register 0x1B is read. CODE_ERR_EXCEED When 1, the ...
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Register 0x1C: Packet Generator Count Control Bit Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 The ...
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CONT_TEST_GEN The CONT_TEST_GEN bit controls whether the Packet Generator for an associated channel will send continues frames will send the PKT_CNT[14 :0] number of frames. If the CONT_TEST_GEN bit is set to a logic 1, it will ...
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Register 0x1D: Redundancy Control Bit Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 The Redundancy Control ...
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RX_CHN_SEL_A:D The RX_CHAN_SEL_A:D bits control which high speed serial input is selected for channels A thru D. If the receive channel select bit for the associated channel is set to a logic 0, the primary high speed input is selected. ...
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Test Features Description 12.1 Packet Generator and Packet Comparator There is one packet generator and one packet comparator for each channel in the device. A packet generator is located within the transmit logic of each channel. A packet comparator ...
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The packet generator of a particular lane does not necessarily have to be used with the packet comparator of that same lane. In fact for a particular serial link, the packet generator of one device can communicate to the packet ...
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Figure 27 Serial Loopback Data Path with Packet Generator/Comparator Enabled TXDz[9:0] Packet Generator TXCKz RxFIFO RXDz[9:0] Packet Comparator REC_CLK RBCz[1:0] LOC_CLK Links between two different QuadPHY 1G devices can also be tested. Enabling the appropriate packet generator in the source ...
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Table 21 Instruction Register Length - 3 bits Instructions EXTEST IDCODE SAMPLE BYPASS BYPASS STCTEST BYPASS BYPASS Table 22 Identification Register Length Version number Part Number Manufacturer's identification code Device identification Proprietary and Confidential to PMC-Sierra, Inc., and for its ...
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Operation 13.1 Power-up The QuadPHY 1G device can start in hardware only mode, without any microprocessor interface in all major operational modes. However, a microprocessor interface is required for testing, debugging and for activating the PCS logic within the ...
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... The parallel output drivers of the PM8354 drive traces which connect to the input pins of a receiving device. The minimum high (V functions of silicon process variation, temperature and supply voltage of the PM8354. Additionally, voltage levels at the input pins of the receiving device will be affected by the following: · ...
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Clock Requirements REFCLK is a maximum 125 MHz ±100 ppm 40/60 or better oscillator. The maximum jitter allowed peak to peak, or approx 7 ps rms. REFCLK feeds a 2.5/1.8 V CMOS input. The oscillator requires ...
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Functional Timing This section outlines the functional timing for the MDC/MDIO serial port. The functional timing for the receive and transmit parallel ports is described in detail in Sections 10.2.3 and 10.2.4. 14.1 MDC/MDIO Interface The MDC/MDIO interface is ...
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Notes: 1. IDLE – Idle. The period when data transfer on MDIO is inactive. The MDC clock may stall until the next transfer or continue to run. 2. PRE[31:0] – Preamble. An optional stream 1’s which assures ...
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Absolute Maximum Ratings Maximum ratings are the worst case limits that the device can withstand without sustaining permanent damage. They are not indicative of normal mode operation conditions. Table 24 Maximum Ratings Case Temperature Under Bias Storage Temperature 1.8V ...
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Power Information 16.1 Power Requirements Table 25 Power Requirements Conditions Parameter 1 Ports Enabled IDD VDDQ = 1.8V IDDA mode IDDQ (10% data 125Mhz transition density) Total Power 1 Ports Enabled IDD VDDQ = 2.5V IDDA mode IDDQ (10% ...
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Conditions Parameter 1 Ports Enabled IDD VDDQ = 2.5V IDDA mode IDDQ (10% data 100Mhz transition density) Total Power 4 Ports Enabled IDD VDDQ = 1.8V IDDA mode IDDQ (50% data 100Mhz transition density) Total Power 4 Ports Enabled IDD ...
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Conditions Parameter 4 Ports Enabled IDD VDDQ = 2.5V IDDA mode IDDQ (50% data 93 Mhz transition density) Total Power Note: 1. Outputs loaded with 30 pF (if not otherwise specified), and a normal amount of traffic or signal activity. ...
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One 10 mF filtering cap should be used on each of the VDD and VDDQ power rails. Taiyo Yuden PN # LMK325BJ106MN or Panasonic PN # ECJ-3YB0J106K are the recommend components. In order to minimize the intrinsic jitter on the ...
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Figure 33 Recommended Power Supply Decoupling Use one 0.1uF capacitor for 1.8 V every two VDD pins 0.1u 10uF Use one 0.1uF capacitor for 1.8V/2.5V every two VDDQ pins 0.1u 10uF 1.8 V 0.47 ohm + 27uF 10uF Proprietary and ...
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D.C. Characteristics Unless otherwise stated, the following parameters are provided given the following conditions -40° 125° ±5% Table 26 D.C. Characteristics Symbol Parameter V Core power supply DD V I/O power ...
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Symbol Parameter C Input Capacitance IN (parallel interface and control terminals) C Output and IO Bidirectional Capacitance (parallel interface and control terminals) C Input Capacitance INHS (RDI terminals) C Output Capacitance OUTHS L Pin Inductance PIN Notes: 1. Input pin ...
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Interface Timing Characteristics Unless otherwise stated, the following parameters are provided given the following conditions -40° 125° ±5% 18.1 Reference Clock Table 27 Reference Clock Timing Symbol REFCLK REFCLK frequency for ...
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Figure 34 QuadPHY 1G Reset Timing RESET 18.3 MII Management Interface (MDC/MDIO) Table 29 MDIO Timing Symbol f MDCMAX t MDCHIGH t MDCLOW t MDCRISE t MDCFALL t MDIORISE t MDIOFALL t MDIO_S t MDIO_H t pMDIO t zMDIO Notes: ...
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Figure 36 MDIO Sourced by PHY MDC MDIO 18.4 JTAG Table 30 JTAG Port Interface Symbol Description — TCK Frequency — TCK Duty Cycle t TMS Set-up time to TCK STMS t TMS Hold time to TCK HTMS t TDI ...
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Figure 37 JTAG Port Interface Timing TCK TMS TDI TCK TDO TRSTB Notes on Input Timing 1. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the VDD/2 ...
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Maximum output propagation delays are measured with load on the outputs 18.5 Transmit Timing Table 31 Transmit Timing Number Symbol Parameter 1 t TXD setup time to TXCK (93.3 MHz) TS TXD setup time to TXCK ...
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RDH 6 t HRDH — t RDR — t RDF — t duty — B_sync — t RXFTOL t SKEW Notes: 1. The outputs are 50 ohm source series internally terminated and are designed to drive a 50 ...
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Figure 39 Parallel Receive Timing Diagram for LRRC, Trunking, and RRRC Mode RBCy RXDy[9:0] Figure 40 Parallel Receive Timing Diagram for HRRC Mode RBCy1 RBCy0 RXDy[9:0] 18.7 Receive Latency Table 33 Receive Latency Timing Number Symbol 5 t RXLAT Note: ...
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Figure 41 Receive Latency 18.8 Transmit Latency Table 34 Transmit Latency Timing Number Symbol 6 t TXLAT Note: 1. The transmitter latency, as shown in Figure 42, is defined as the time between the latching in of the parallel data ...
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... V DIFF Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2012433, Issue 4 QuadPHY 1G ASSP Telecom Standard Product Data Sheet TDO+ RDI+ 50 ohm 0.01 µf TDO- RDI- 50 ohm 0.01 µf Released High Speed Inputs 100 ohm PM8354 151 ...
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When viewing a data eye on an oscilloscope using a differential probe across terminals A and B, the top and bottom of the eye will have a maximum separation of V signal is measured using a single ended probe attached ...
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Table 37 Fibre Channel Jitter Specifications T Total output jitter J T Deterministic output jitter DJ R Total Jitter Tolerance RJT R Deterministic Jitter Tolerance DJT R Sinusoidal Jitter Tolerance SJT Notes: 1. Total jitter is composed of both deterministic ...
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Thermal Information This product is designed to operate over a wide temperature range and is suited for outside plant equipment. Table 38 Outside Plant Thermal Information Maximum long-term operating junction temperature (T term life. Maximum junction temperature (T continued ...
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Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2012433, Issue 4 QuadPHY 1G ASSP Telecom Standard Product Data Sheet Released 155 ...
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Mechanical Information This mechanical package diagram QuadPHY 1G’s 289 Pin CABGA Package is shown in Figure 45. After assembly, the QuadPHY 1G is tested to meet or exceed a 0.15mm (5.9mil) coplanarity specification. Proprietary and Confidential to PMC-Sierra, Inc., ...
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Figure 45 Mechanical Drawing 289 Pin CABGA A1 BALL D CORNER A1 BALL ID INDICATOR SEATING PLANE A1 NOTES: 1) ALL DIMENSIONS IN MILLIMETER. 2) DIMENSION aaa DENOTES PACKAGE BODY PROFILE. 3) DIMENSION bbb DENOTES PARALLEL. 4) ...
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Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2012433, Issue 4 QuadPHY 1G ASSP Telecom Standard Product Data Sheet Released 158 ...