21285-AB

Manufacturer Part Number21285-AB
DescriptionMicroprocessor, 21285 Core Logic For SA-110 Microprocessor
ManufacturerIntel Corporation
21285-AB datasheet
 


Specifications of 21285-AB

CaseBGADc99+/00+
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Page 53/159:

Configuration Read

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3.3.7

Configuration Read

Configuration read is completed when the SA-110 address is in the PCI configuration space.
Table 3-5
shows how the PCI address is derived from the configuration address.
The PCI byte enables for each data phase are derived from the SA-110 A/MAS signals. One
Dword is read.
The following general rules apply to the command transactions:
If the 21285 receives a target retry response, it repeats the configuration read command at the
first opportunity.
If the 21285 receives a master abort, it substitutes FFFFFFFFh for the read data and sets the
status register received master abort bit [29], which, if enabled, interrupts the SA-110.
If the 21285 receives a target abort, it substitutes FFFFFFFFh for the read data and sets the
status register received target abort bit [28], which, if enabled, interrupts the SA-110.
3.3.8
Special Cycle
Special cycle is completed when the SA-110 address is in the PCI IACK/Special space. The
special cycle is caused by an SA-110 write. The PCI address is undefined.
The PCI byte enables for each data phase are derived from the SA-110 A/MAS signals. One
Dword is written.
Special cycles are broadcast to all PCI agents, so devsel_l is not asserted and no errors can be
received.
3.3.9
IACK Read
IACK read is completed when the SA-110 address is in the PCI IACK/Special space. An IACK
read is caused by an SA-110 read. The PCI address is undefined.
The PCI byte enables for each data phase are derived from the SA-110 A/MAS signals. One
Dword is read.
The following general rules apply to the command transactions:
If the 21285 receives a target retry response, it repeats the IACK read at the first opportunity.
If the 21285 receives a master abort, it substitutes FFFFFFFFh for the read data and sets the
status register received master abort bit [29], which, if enabled, interrupts the SA-110.
If the 21285 receives a target abort, it substitutes FFFFFFFFh for the read data and sets the
status register received target abort bit [28], which, if enabled, interrupts the SA-110.
3.3.10
PCI Request Operation
The 21285 asserts req_l to act as bus master on the PCI for SA-110 and DMA originated
transactions. It deasserts req_l for two cycles when it receives a retry or disconnect response from
the target. However, if gnt_l is asserted, the 21285 can start a PCI transaction regardless of the
state of req_l.
21285 Core Logic for SA-110 Datasheet
Transactions
3-19